Calibration circuit and semiconductor memory device including the same
阅读说明：本技术 校准电路及包括该校准电路的半导体存储器件 (Calibration circuit and semiconductor memory device including the same ) 是由 崔训对 于 2019-08-05 设计创作，主要内容包括：本公开提供了校准电路及包括该校准电路的半导体存储器件。该校准电路包括：第一上拉单元和第二上拉单元,第一上拉单元和第二上拉单元均接收上拉代码并连接在与外部电阻器连接的焊盘和第一电源电压之间；下拉单元,该下拉单元连接在焊盘与第二电源电压之间并接收下拉代码；比较器,该比较器比较第一电压与参考电压,然后比较第二电压与参考电压；第一数字滤波器,该第一数字滤波器基于第一电压与参考电压的第一比较结果调整上拉代码；以及第二数字滤波器,该第二数字滤波器基于第二电压与参考电压的第二比较结果调整下拉代码。(The present disclosure provides a calibration circuit and a semiconductor memory device including the same. The calibration circuit includes: a first pull-up unit and a second pull-up unit each receiving a pull-up code and connected between a pad connected to an external resistor and a first power voltage; a pull-down unit connected between the pad and a second power voltage and receiving a pull-down code; a comparator that compares the first voltage with a reference voltage and then compares the second voltage with the reference voltage; a first digital filter that adjusts a pull-up code based on a first comparison result of a first voltage and a reference voltage; and a second digital filter that adjusts the pull-down code based on a second comparison of the second voltage to the reference voltage.)
1. A calibration circuit, comprising:
a first pull-up unit and a second pull-up unit connected between a pad connected to an external resistor and a first power supply voltage, the first pull-up unit and the second pull-up unit each configured to receive a pull-up code;
a pull-down unit connected between the pad and a second power supply voltage and configured to receive a pull-down code;
a comparator configured to:
comparing the first voltage with a reference voltage to generate a first comparison result, an
Comparing the second voltage with the reference voltage to generate a second comparison result,
the first voltage is generated based on the first pull-up unit and the external resistor,
the first voltage is generated at a common node connected to the pad, and the second voltage is based on the first and second pull-up units, the external resistor, and
the pull-down unit generates, the second voltage is generated at the common node;
a first digital filter configured to adjust the pull-up code based on the first comparison result; and
a second digital filter configured to adjust the pull-down code based on the second comparison result.
2. The calibration circuit of claim 1, wherein the first digital filter is configured to adjust the pull-up code such that a resistance value of the first pull-up unit is the same as a resistance value of the external resistor,
wherein the second digital filter is configured to adjust the pull-down code such that a resistance value of the pull-down unit is the same as a resistance value of the external resistor after the pull-up code is adjusted, and
wherein the first and second digital filters share the comparator that compares the first and second voltages of the common node with the reference voltage, respectively.
3. The calibration circuit of claim 2,
the first voltage is generated based on a resistance value of the external resistor connected between the second power supply voltage and the pad; and is
A resistance value of the first pull-up unit changes based on the pull-up code.
4. The calibration circuit of claim 3, wherein the first digital filter is configured to adjust the pull-up code such that a level of the first voltage is the same as a level of the reference voltage.
5. The calibration circuit of claim 2,
the second pull-up unit is configured to adjust the pull-up code in response to the first digital filter being electrically open between the pad and a first supply voltage; and is
The first pull-up unit and the second pull-up unit are configured to adjust the pull-down code in response to the second digital filter, connected between the pad and the first supply voltage.
6. The calibration circuit of claim 5, wherein the second voltage is determined based on a resistance value of the external resistor, resistance values of the first and second pull-up units, and a resistance value of the pull-down unit.
7. The calibration circuit of claim 6, wherein the second digital filter is configured to adjust the pull-down code such that the level of the second voltage is the same as the level of the reference voltage.
8. The calibration circuit of claim 6,
the first pull-up unit and the second pull-up unit are connected in parallel between the pad and the first power supply voltage; and is
The external resistor and the pull-down unit are connected in parallel between the pad and the second power supply voltage.
9. A semiconductor memory device comprising:
a calibration circuit configured to:
adjusting a first code such that a first resistance value of each of a plurality of first resistance units connected between a first pad and a first power supply voltage is the same as a resistance value of an external resistor connected to the first pad,
adjusting a second code such that a second resistance value of a second resistance unit connected between the first pad and a second power supply voltage is the same as a resistance value of the external resistor,
a first result is generated by comparing the first voltage to a reference voltage,
generating a second result by comparing a second voltage with the reference voltage,
the first voltage is generated at a common node connected to the first pad based on one of the plurality of first resistance units and the external resistor, and
the second voltage is generated at the common node based on the plurality of first resistance units, the second resistance unit, and the external resistor;
a memory cell array including dynamic random access memory cells connected to word lines and bit lines and configured to store data received through a second pad or data to be output through the second pad;
a row decoder configured to select at least one of the word lines;
a column decoder configured to select at least one column selection line of column selection lines connected to the bit line; and
an output driver configured to:
receiving the first code and the second code,
providing a termination resistance to the second pad based on the first code and the second code, an
Outputting data stored in the memory cell array through the second pad.
10. The semiconductor memory device of claim 9, wherein the calibration circuit is configured to:
not adjusting the second code while adjusting the first code; and is
Adjusting the second code after adjusting the first code.
11. The semiconductor memory device of claim 10, wherein the calibration circuit is further configured to:
a first control signal to be activated during a first time interval and a second control signal to be activated during a second time interval subsequent to the first time interval are generated.
12. The semiconductor memory device of claim 11, wherein the calibration circuit further comprises:
a first digital filter configured to be activated by the first control signal and to adjust the first code based on the first result; and
a second digital filter configured to be activated by the second control signal and to adjust the second code based on the second result.
13. The semiconductor memory device according to claim 11, wherein another first resistance unit other than the one first resistance unit among the plurality of first resistance units is activated only by the second control signal.
14. The semiconductor memory device according to claim 9, further comprising:
an on-die termination circuit configured to receive the first code and the second code and provide a termination resistance to a third pad; and
a command decoder configured to decode a ZQ command that activates the calibration circuit, a write command associated with the data, or a read command associated with the data, wherein the ZQ command, the write command, and the read command are received through the third pad.
15. The semiconductor memory device according to claim 14, further comprising:
a mode register configured to store an operation code based on a mode register setting command,
wherein the command decoder is further configured to decode the mode register set command.
16. The semiconductor memory device according to claim 15, wherein the output driver is configured to set a resistance value of a termination resistor connected to the second pad based on the operation code.
17. A semiconductor memory device comprising:
a calibration circuit configured to:
operating based on the first power supply voltage and the second power supply voltage,
the first code and the second code are adjusted using a resistance value of an external resistor connected to a first pad of the semiconductor memory device,
generating a first result by comparing a first voltage generated at a common node of the semiconductor memory device based on a first resistance value determined based on the first code and a resistance value of the external resistor, with a reference voltage, the common node being connected to the first pad, and
generating a second result by comparing a second voltage generated at the common node based on a second resistance value determined based on the first code, a resistance value of the external resistor, and a third resistance value based on the second code with the reference voltage;
an output driver configured to operate based on the first and second power supply voltages, receive the first and second codes, and adjust a resistance value of a termination resistor connected to a second pad based on the first and second codes;
a memory cell array including dynamic random access memory cells connected to word lines and bit lines, the memory cell array configured to operate based on a third power supply voltage and a fourth power supply voltage and to store data received through the second pad or data to be output through the second pad;
a row decoder configured to select at least one of the word lines; and
a column decoder configured to select at least one of column selection lines connected to the bit line.
18. The semiconductor memory device according to claim 17, wherein the common node is electrically connected to the first pad.
19. The semiconductor memory device of claim 17, wherein the calibration circuit is configured to:
adjusting the first code based on the first result; and
adjusting the second code based on the second result.
20. The semiconductor memory device according to claim 17, wherein the second resistance value is half of the first resistance value.
Technical Field
Various example embodiments of the inventive concepts described herein relate to a calibration circuit, a calibration system, a semiconductor memory device including the calibration circuit, and/or a method of using the calibration circuit, and more particularly, to a calibration circuit including a common node shared by a pull-up calibration path and a pull-down calibration path, a semiconductor memory device including the calibration circuit, a system including the calibration circuit, and/or a method of using the calibration circuit.
Background
Signals transmitted along the transmission line may be reflected at the end of the transmission line. In addition, signal reflections may have an effect on the transmission of the signal. The termination resistors may be used to match impedances between devices exchanging signals over the transmission lines and may reduce signal reflections. For impedance matching, a termination resistor (i.e., an on-die termination (ODT) circuit) may be included in a memory device that receives commands and addresses from a memory controller at high speed and exchanges data with the memory controller at high speed.
The value (e.g., resistance value) of the termination resistor in the memory device may vary with process, voltage, and temperature. To this end, the memory device may comprise a calibration circuit for calibrating the value of the termination resistor. A conventional calibration circuit includes a pull-up calibration path and a pull-down calibration path that are separate from each other. In this case, each path may be affected by PVT (process, voltage, temperature) variations.
Disclosure of Invention
Various example embodiments of the inventive concepts provide a calibration circuit including a common node shared by a pull-up calibration path and a pull-down calibration path, a system including the calibration circuit, a semiconductor memory device including the calibration circuit, and/or a method of using the calibration circuit.
According to at least one example embodiment, a calibration circuit may include: a first pull-up unit and a second pull-up unit connected between a pad connected to an external resistor and a first power supply voltage, the first pull-up unit and the second pull-up unit each configured to receive a pull-up code; a pull-down unit connected between the pad and a second power supply voltage and configured to receive a pull-down code; a comparator configured to compare a first voltage and a reference voltage to generate a first comparison result, compare a second voltage and the reference voltage to generate a second comparison result, the first voltage being generated based on the first and second pull-up units, the external resistor and the pull-down unit, the first voltage being generated at a common node connected to the pad, the second voltage being generated based on the first and second pull-up units, the external resistor and the pull-down unit, the second voltage being generated at the common node; a first digital filter configured to adjust the pull-up code based on the first comparison result; and a second digital filter configured to adjust the pull-down code based on the second comparison result.
According to at least one example embodiment, a semiconductor memory device may include: a calibration circuit configured to: adjusting a first code such that a first resistance value of each of a plurality of first resistance units connected between a first pad and a first power supply voltage is the same as a resistance value of an external resistor connected to the first pad, adjusting a second code such that a second resistance value of a second resistance unit connected between the first pad and a second power supply voltage is the same as a resistance value of the external resistor, generating a first result by comparing a first voltage generated at a common node connected to the first pad based on one of the plurality of first resistance units and the external resistor and a reference voltage, generating a second result by comparing a second voltage generated at the common node connected to the first pad based on the plurality of first resistance units and the reference voltage, and the second voltage generated at the common node based on the plurality of first resistance units, The second resistance unit and the external resistor are generated at the common node; a memory cell array including a Dynamic Random Access Memory (DRAM) cell connected to a word line and a bit line and configured to store data received through a second pad or data to be output through the second pad; a row decoder configured to select at least one of the word lines; a column decoder configured to select at least one column selection line of column selection lines connected to the bit line; and an output driver configured to: receiving the first code and the second code, providing a termination resistance to the second pad based on the first code and the second code, and outputting data stored in the memory cell array through the second pad.
According to at least one example embodiment, a semiconductor memory device may include: a calibration circuit configured to: operating based on a first power supply voltage and a second power supply voltage, adjusting a first code and a second code using a resistance value of an external resistor connected to a first pad of the semiconductor memory device, generating a first result by comparing a first voltage generated at a common node of the semiconductor memory device based on a first resistance value with a reference voltage, the first resistance value is determined based on the first code and a resistance value of the external resistor, the common node is connected to the first pad, and generating a second result by comparing a second voltage generated at the common node based on a second resistance value with the reference voltage, the second resistance value is determined based on the first code, a resistance value of the external resistor, and a third resistance value based on the second code; an output driver configured to operate based on the first and second power supply voltages, receive the first and second codes, and adjust a resistance value of a termination resistor connected to a second pad based on the first and second codes; a memory cell array including Dynamic Random Access Memory (DRAM) cells connected to word lines and bit lines, the memory cell array configured to operate based on a third power supply voltage and a fourth power supply voltage and to store data received through the second pad or data to be output through the second pad; a row decoder configured to select at least one of the word lines; and a column decoder configured to select at least one of the column selection lines connected to the bit line.
Drawings
Fig. 1 and 2 are block diagrams illustrating a calibration circuit according to at least one example embodiment of the inventive concepts.
Fig. 3 is a block diagram illustrating a pull-up unit of fig. 1 and 2 according to at least one example embodiment.
Fig. 4 is a block diagram illustrating the pull-down unit of fig. 1 and 2 according to at least one example embodiment.
Fig. 5 is a block diagram illustrating the calibration circuit of fig. 1 and 2 according to at least one example embodiment.
Fig. 6 is a block diagram illustrating the calibration circuit of fig. 1 and 2 according to at least one example embodiment.
Fig. 7 and 8 are block diagrams illustrating a calibration circuit according to at least one example embodiment of the inventive concepts.
Fig. 9 and 10 are block diagrams illustrating a calibration circuit according to at least one example embodiment of the inventive concepts.
Fig. 11 is a flowchart illustrating an operation method of a calibration circuit according to at least one example embodiment of the inventive concepts.
Fig. 12 is a block diagram illustrating a memory device to which a calibration circuit according to at least one example embodiment of the inventive concepts is applied.
Fig. 13 is a timing diagram of a calibration circuit in a case where a ZQ calibration code is input to the memory device of fig. 12 according to at least one example embodiment.
Fig. 14 is a block diagram illustrating the output driver of fig. 12 according to at least one example embodiment.
Detailed Description
Hereinafter, various exemplary embodiments of the inventive concept will be described in detail and clearly so that those skilled in the art can easily implement the exemplary embodiments of the inventive concept.
Fig. 1 and 2 are block diagrams illustrating a calibration circuit according to at least one example embodiment of the inventive concepts. Fig. 1 and 2 will be described together. The
The
The pull-up units 120_1 and 120_2 (e.g., pull-up transistors and/or pull-up resistors, etc.) may receive the pull-up code PUCODE, respectively. According to the pull-up code PUCODE, the pull-up units 120_1 and 120_2 may be connected between the power supply voltage VDDQ and the
The
The first
A pull-down unit 150 (e.g., a pull-down transistor and/or a pull-down resistor, etc.) may be connected between the
Like the first
The
For on-die termination, the
The pull-up code PUCODE may be adjusted via the first path (e.g., the pull-up code PUCODE may be transmitted via the first path). The first path may include one of the pull-up units 120_1 and 120_2, the
The
The level of the voltage VDIV (e.g., a voltage value of VDIV) may be determined by a divided voltage determined according to a difference between the power supply voltages VDDQ and VSSQ, the pull-up unit 120_1 and/or the external resistor RZQ, and the like. Since the pull-up unit 120_2 is not activated, the pull-up unit 120_1 and the external resistor RZQ may be connected in series between the power supply voltages VDDQ and VSSQ. For example, in the case where the power supply voltage VSSQ is a ground voltage and the resistance value of the pull-up unit 120_1 is "RU" that is changed according to the pull-up code PUCODE (e.g., set based on the pull-up code PUCODE), the level of the voltage VDIV may be equal to "VDDQ × [ RZQ ]/[ RU + RZQ ]", but the example embodiments are not limited thereto.
The first
After adjusting the pull-up code PUCODE through the first path, the
The pull-down code PDCODE may be adjusted over the second path (e.g., the pull-down code PDCODE may be transmitted over the second path). The second path may include the pull-down
The
The level of the voltage VDIV (e.g., a voltage value of VDIV, etc.) may be determined by a divided voltage determined according to a difference between the power supply voltages VDDQ and VSSQ, the pull-up units 120_1 and 120_2, the external resistor RZQ, and/or the pull-down
The first group (e.g., including the pull-up cells 120_1 and 120_2) and the second group (e.g., including the external resistor RZQ and the pull-down cell 150) may be connected in series between the power voltage VDDQ and the power voltage VSSQ, however, example embodiments are not limited thereto. For example, in the case where the power supply voltage VSSQ is the ground voltage, the resistance value of each of the pull-up cells 120_1 and 120_2 is a fixed "RU" based on the pull-up code PUCODE, and the resistance value of the pull-down
The second
As described above, the voltage VDIV of the common node generated through the first path (e.g., transmitted through the first path) may be determined by voltage division according to the difference between the power supply voltages VDDQ and VSSQ, one pull-up unit 120_1, and/or the external resistor RZQ, etc. The voltage VDIV of the common node generated through the second path may be determined by voltage division according to a difference between the power supply voltages VDDQ and VSSQ, the two pull-up units 120_1 and 120_2, the external resistor RZQ, and/or the pull-down
In at least one example embodiment, the
Unlike the above-described exemplary embodiments, the calibration unit of the conventional art may have a first comparator for adjusting the pull-up code PUCODE and another comparator (e.g., a second comparator) for adjusting the pull-down code PDCODE in the calibration circuit, and thus PVT variations may occur at the respective comparators. Also, in another calibration unit of the conventional art, nodes generating the voltage VDIV are different from each other and do not share a common node, and PVT variations may occur at each corresponding node. In contrast, the
In at least one example embodiment,
Fig. 3 is a block diagram illustrating a pull-up unit of fig. 1 and 2 according to at least one example embodiment. The pull-up unit 120_1 of fig. 3 may be the pull-up unit 120_1 of fig. 1 and 2, but is not limited thereto.
Pull-up unit 120_1 may include a processor coupled to receive pull-up code PUCODE [ 0: n ] (N is a natural number) and the
The pull-up unit 120_1 may further include a transistor turned on during the calibration operation and/or a resistor Rum connected to the transistor, but is not limited thereto. The control signal ZQCAL _ ENB may indicate a calibration operation interval. The calibration operation interval may include an interval (e.g., time interval, time period, etc.) to adjust the pull-up code PUCODE and an interval (e.g., time interval, time period, etc.) to adjust the pull-down code PDCODE. For example, the control signal ZQCAL _ ENB may have a logic "0" in an interval of adjusting the pull-up code pulse and an interval of adjusting the pull-down code PDCODE, and may electrically connect the power supply voltage VDDQ and the resistor Rum, but the example embodiments are not limited thereto. The resistor Rum may be electrically connected between the power supply voltage VDDQ and the
The combined resistance value (or equivalent resistance value) of the pull-up unit 120_1 may be determined by the resistor Rum and Rus and a switch based on the control signal ZQCAL _ ENB and the pull-up code pulse. For example, when the control signal ZQCAL _ ENB is activated and finally the pull-up code is provided to the pull-up unit 120_1, the combined resistance value of the pull-up unit 120_1 may be the same as the resistance value (e.g., 240 Ω) of the external resistor RZQ.
In at least one example embodiment, unlike the illustration of fig. 3, the position of the switch and the position of the resistor Rum and Rus may be interchangeable. For example, the resistor Rum and Rus may be connected between the power supply voltage VDDQ and the switch, but example embodiments are not limited thereto. As another example, a switch may be connected between the resistor Rum and Rus and the
In at least one example embodiment, the pull-up unit 120_2 of fig. 1 and 2 may be implemented to be the same as the pull-up unit 120_1 of fig. 3, but is not limited thereto. However, when the pull-up code PUCODE is adjusted, all switches connected to the resistor Rum and Rus of the pull-up unit 120_2 may be turned off. When adjusting the pull-down code PDCODE, the final pull-up code may be supplied to the switch connected to the resistor Rus of the pull-up unit 120_ 2. In adjusting the pull-down code PDCODE, instead of the control signal ZQCAL _ ENB, another control signal ZQPD _ ENB may be provided to a switch connected to the resistor Rum of the pull-up unit 120_ 2. The control signal ZQPD _ ENB may be an inverted version of the second control signal ZQPD _ EN and may turn on a switch connected to the resistor Rum of the pull-up unit 120_2 when the pull-down code PDCODE is adjusted.
Fig. 4 is a block diagram illustrating the pull-down unit of fig. 1 and 2 according to at least one example embodiment. The pull-down
Pull-down
The pull-down
The combined resistance value of the pull-down
In at least one example embodiment, unlike the illustration of fig. 4, the position of the switch and the position of resistors Rdm and Rds may be interchangeable. For example, resistors Rdm and Rds may be connected between supply voltage VSSQ and a switch or the like. As another example, switches may be connected between resistors Rdm and Rds and
In at least one example embodiment, the pull-up code PUCODE [ 0: n ] and a pull-down code PDCODE [ 0: n ], i.e., equal to the description of (N +1), but the pull-up code PUCODE [ 0: n ] and a pull-down code PDCODE [ 0: n ] may be different from each other in number of bits. The number of switches of the pull-up unit 120_1 and the number of switches of the pull-down
Fig. 5 is a block diagram illustrating the calibration circuit of fig. 1 and 2 according to at least one example embodiment. The
As described above, when adjusting the pull-up code PUCODE, the pull-up code PUCODE may be provided to the pull-up unit 120_1, but not to the pull-up unit 120_ 2. When the second control signal ZQPD _ EN is not activated, the
When the second control signal ZQPD _ EN is activated, the
Fig. 6 is a block diagram illustrating the calibration circuit of fig. 1 and 2 according to at least one example embodiment. The
Unlike the above example, the pull-up code PUCODE of the first
The
Fig. 7 and 8 are block diagrams illustrating a calibration circuit according to at least one example embodiment of the inventive concepts. Fig. 7 and 8 will be described together. The
Unlike the
The level of the voltage VDIV may be determined by a divided voltage determined according to the difference between the power supply voltages VDDQ and VSSQ, the four pull-up units 220_1 to 220_4, and the external resistor RZQ, but is not limited thereto. The pull-up units 220_1 to 220_4 may be connected in parallel, but are not limited thereto. For example, in the case where the power supply voltage VSSQ is the ground voltage and the resistance value of each of the pull-up cells 220_1 to 220_4 is "RU", the level of the voltage VDIV may be "VDDQ × [ RZQ ]/[ (RU/4) + RZQ ]". Unlike the case of fig. 1 and 2, the reference voltage VREFZQ may be previously set to 'VDDQ × 0.8' such that the resistance value of each of the pull-up units 220_1 to 220_4 is the same as that of the external resistor RZQ, but example embodiments are not limited thereto, and for example, the reference voltage may be set in real time. As the number of pull-up cells included in the first path increases, the level of the reference voltage VREFZQ may also increase. The number of pull-up cells and the level of the reference voltage VREFZQ are not limited to the above example. The number of pull-up units may be determined according to the level of the reference voltage VREFZQ set in advance and/or set in real time. For example, in the case where the number of pull-up cells is "M", the level of the reference voltage VREFZQ may be "VDDQ × [ RZQ ]/[ RZQ/(M/2) + RZQ ]". The first
As in the
The level of the voltage VDIV may be determined by a divided voltage determined according to (e.g., based on) a difference between the power supply voltages VDDQ and VSSQ, the eight pull-up units 220_1 to 220_8, the external resistor RZQ, and/or the pull-down
A set of pull-up cells 220_1 to 220_8 and a set of external resistors RZQ and pull-
Fig. 9 and 10 are block diagrams illustrating a calibration circuit according to at least one example embodiment of the inventive concepts. Fig. 9 and 10 will be described together. The
Unlike the above example, the external resistor RZQ may be connected between the power supply voltage VDDQ and the
The
The first
The pull-up
The second
Unlike the
The pull-down code PDCODE may be adjusted through the first path, but is not limited thereto. The first path may include the pull-down cells 320_1 to 320_4, the
The level of the voltage VDIV may be determined by a divided voltage determined according to the difference between the power supply voltages VDDQ and VSSQ, the pull-down units 320_1 to 320_4, and/or the external resistor RZQ, etc. The pull-down units 320_1 to 320_4 may be connected in parallel, but are not limited thereto. For example, in a case where the power supply voltage VSSQ is a ground voltage and the resistance value of each of the pull-down units 320_1 to 320_4 is "RD", the level of the voltage VDIV may be "VDDQ × [ RD/4]/[ RZQ + (RD/4) ]". The reference voltage VREFZQ may be set to 'VDDQ × 0.2' in advance and/or in real time such that the resistance value of each of the pull-down units 320_1 to 320_4 is the same as that of the external resistor RZQ. As the number of pull-down cells included in the first path increases, the level of the reference voltage VREFZQ may decrease. The number of pull-down cells and the level of the reference voltage VREFZQ are not limited to the above example. The number of pull-down units may be determined according to a level of the reference voltage VREFZQ set in advance and/or set in real time. For example, in the case where the number of pull-down cells is "M", the level of the reference voltage VREFZQ may be "VDDQ × [ RZQ/(M/2) ]/[ RZQ/(M/2) + RZQ ]". The first
The
The level of the voltage VDIV may be determined by a divided voltage determined according to a difference between the power supply voltages VDDQ and VSSQ, the pull-down units 320_1 to 320_8, the external resistor RZQ, and/or the pull-up
A set of external resistors RZQ and the pull-up
Fig. 11 is a flowchart illustrating an operation method of a calibration circuit according to at least one example embodiment of the inventive concepts. Fig. 11 will be described with reference to fig. 1 to 10. Both the
In operation S110, the
In operation S120, the
In operation S130 after operation S120, the
In operation S140, the
Fig. 12 is a block diagram illustrating a memory device to which a calibration circuit according to at least one example embodiment of the inventive concepts is applied. The memory device 1000 may also be referred to as a "semiconductor memory device". The memory device 1000 may include pads 1111 to 1114, a calibration circuit 1200, input buffers 1311 to 1313, ODT circuits 1321 and 1322, an output driver 1323, a memory cell array 1410, a row decoder 1420, a column decoder 1430, a write driver and an input/output sense amplifier 1440, a command decoder 1450, an address register 1460, a mode register 1470, and/or a serializer and deserializer 1480, and the like, but is not limited thereto.
A command CMD may be input to the pad 1111 from the outside of the memory device 1000. The pads 1111 may also be referred to as "terminals" or "pins". The command CMD may be included in only unidirectional signals (e.g., CS _ n, ACT _ n, RAS _ n, CAS _ n, WE _ n, etc.) input to the memory device 1000, and the pad 1111 may be an input pad.
An address ADD may be input to the pad 1112 from the outside of the memory device 1000. The address ADD may be included in only unidirectional signals (e.g., a0, a1, a2, etc.) input to the memory device 1000, and the pad 1112 may be an input pad. The memory device 1000 may receive a row address RA and a column address CA indicating locations of memory cells in the memory cell array 1410 through the pads 1112. In addition, the memory device 1000 may also receive an operation code OPCODE for setting an operation mode of the memory device 1000 through the pad 1112.
Write Data (WDATA) may be input to pad 1113 from outside of memory device 1000 (e.g., an external source, etc.). Internally Read Data (RDATA) of the memory device 1000 may be output to the pad 1113. DQ signals, including write data or read data, may be input to memory device 1000 through pad 1113 or may be output from memory device 1000 through pad 1113. The DQ signal may be a bidirectional signal, and the pad 1113 may be a data input/output pad, but example embodiments are not limited thereto. For example, the middle level "[ VOL + VOH ]/2" of the first level VOL of the voltage corresponding to logic "0" of the DQ signal and the second level VOH of the voltage corresponding to logic "1" of the DQ signal may be the same as the level of the reference voltage VREFZQ described above, and the level of the reference voltage VREFZQ may be referred to as "center level" or "common mode level" of the DQ signal. The reference voltage VREFZQ may be predetermined according to the protocol of the memory device 1000. For example, in the case of transmitting a DQ signal using a Center Tap Termination (CTT) scheme, the level of the reference voltage VREFZQ may be "VDDQ × 0.5", but is not limited thereto. For another example, in the case of transmitting a DQ signal using a virtual open drain (POD) termination scheme, the level of the reference voltage VREFZQ may be "VDDQ × 0.8" or the like. For another example, in the case of transmitting a DQ signal using a ground termination scheme, the level of the reference voltage VREFZQ may be "VDDQ × 0.2" or the like. The level of the reference voltage VREFZQ is not limited to the above example.
The external resistor RZQ described with reference to fig. 1, 2, 7, 8, 9, and 10 may be connected to the pad 1114. For example, pad 1114 may be referred to as a "ZQ pad" and may be
The calibration circuit 1200 may be the
The input buffer 1311 may receive a command CMD through the pad 1111, and may provide the command CMD to the command decoder 1450. Input buffer 1312 may receive address ADD through pad 1112 and may provide address ADD to address register 1460. Unlike the illustration, the input buffer 1312 may receive the command/address CA through the pad 1112, and may provide the command/address CA to the command decoder 1450 and the address register 1460, but is not limited thereto. The input buffer 1313 may receive write data through the pad 1113, and may provide the write data to the serializer and deserializer 1480, etc.
The ODT circuit 1321 may provide a termination resistor connected to the pad 1111 according to a pull-up code pulse and a pull-down code PDCODE. The ODT circuit 1321 may provide a termination resistor to an end of a transmission line for transmitting a command CMD from a memory controller (not shown) to the memory device 1000.
ODT circuit 1322 may provide termination resistors connected to pads 1112 according to and/or based on pull-up code PUCODE and pull-down code PDCODE. The ODT circuit 1322 may provide a termination resistor to an end of a transmission line for transmitting the address ADD from the memory controller to the memory device 1000, but is not limited thereto.
The output driver 1323 may receive read data from the serializer and deserializer 1480 and may output the read data to the memory controller through the pad 1113, but is not limited thereto. In addition, the output driver 1323 may receive a pull-up code PUCODE and a pull-down code PDCODE. The output driver 1323 may provide a termination resistor connected to the pad 1113 according to the pull-up code pulse and the pull-down code PDCODE. The output driver 1323 may provide a termination resistor to an end of a transmission line for transmitting a data input/output signal (DQ signal) between the memory controller and the memory device 1000, but is not limited thereto.
In the case where the pull-up code PUCODE and the pull-down code PDCODE are not provided to the ODT circuits 1321 and 1322 and the output driver 1323, the termination resistors to be provided by the ODT circuits 1321 and 1322 and the output driver 1323 may affect PVT variations. The calibration circuit 1200 may generate the pull-up code PUCODE and the pull-down code PDCODE such that the termination resistors provided by the ODT circuits 1321 and 1322 and the output driver 1323 are determined according to the external resistor RZQ without affecting PVT variations.
In at least one example embodiment, the number of pads 1111 for receiving the command CMD may be at least one or more. The memory device 1000 may include pads for receiving a command CMD, input buffers respectively connected to the pads, and/or ODT circuits, but is not limited thereto. As in the above description, the number of pads 1112 for receiving the address ADD may be at least one or more. The memory device 1000 may include pads for receiving an address ADD, input buffers respectively connected to the pads, and/or ODT circuits, but is not limited thereto. In addition, the memory device 1000 may include pads for receiving both commands CMD and addresses ADD, input buffers respectively connected to the pads, and/or ODT circuits, but is not limited thereto. As in the above description, the number of the pads 1113 may be at least one or more. The memory device 1000 may include pads for data input/output and input buffers and output drivers connected to the pads.
The memory cell array 1410 may include memory cells connected to word lines WL and bit lines. The word lines WL and the bit lines may be arranged to be perpendicular to each other. For example, the memory cells may be Dynamic Random Access Memory (DRAM) cells, Static Random Access Memory (SRAM) cells, Thyristor Random Access Memory (TRAM) cells, NAND flash memory cells, NOR flash memory cells, Resistive Random Access Memory (RRAM) cells, Ferroelectric Random Access Memory (FRAM) cells, phase change random access memory (PRAM) cells, Magnetic Random Access Memory (MRAM) cells, and/or the like. For example, the memory cell array 1410 may include DRAM cells, and the memory device 1000 may be a double data rate synchronous DRAM (DDR SDRAM), DDR2SDRAM, DDR3SDRAM, DDR4SDRAM, DDR5SDRAM, Low Power Double Data Rate (LPDDR) SDRAM, LPDDR2SDRAM, LPDDR3SDRAM, LPDDR4SDRAM, LPDDR5SDRAM, High Bandwidth Memory (HBM), HBM2, HBM3, or the like. Data received through the pad 1113 may be stored to the memory cell array 1410. Data stored in the memory cell array 1410 may be output through the pad 1113.
The row decoder 1420 may decode a row address RA and may select at least one word line WL. For example, the row decoder 1420 may select at least one word line WL when an activation command, a refresh command, or the like is input to the memory device 1000. When a precharge command is input to the memory device 1000, the row decoder 1420 may precharge a selected word line.
The column decoder 1430 may decode a column address CA and may select at least one column selection line CSL. One column selection line may be connected to at least two or more bit lines (e.g., 8 bit lines). The number of bit lines connected to one column select line may be determined based on a prefetch size, a burst length, and the like. For example, when a read command, a write command, or the like is input to the memory device 1000, the column decoder 1430 may select at least one column selection line CSL. For convenience of explanation, the column selection line CSL and the word line WL are shown in fig. 12 to be parallel to each other, but the column selection line CSL may be arranged to be perpendicular to the word line WL.
The write driver and input/output sense amplifier 1440 may receive write data from the serializer and deserializer 1480 and may write the write data to the memory cell selected by the row decoder 1420 and the column decoder 1430 through the global input/output line GIO, but is not limited thereto. The write driver and the input/output sense amplifier 1440 may read data from the selected memory cell through the global input/output line GIO and may provide the read data to the serializer and deserializer 1480, but is not limited thereto.
The command decoder 1450 may receive and decode the command CMD from the input buffers 1311 and 1312. For example, the command decoder 1450 may decode an activate command, a precharge command, and/or a refresh command, and may control the row decoder 1420 based on the decoded command(s). For example, the command decoder 1450 may decode a write command or a read command, and may control the column decoder 1430 and the like. In addition, the command decoder 1450 may decode a Mode Register Set (MRS) command and may control the address register 1460 such that the operation code OPCODE is stored to the mode register 1470 or the like.
As another example, the command decoder 1450 may decode the ZQ calibration command and may provide the control signal ZQCAL _ EN to the calibration circuit 1200. For example, the ZQ calibration commands may be generated by the memory controller for impedance matching of the memory device 1000. When the control signal ZQCAL _ ENB is activated, the calibration circuit 1200 may start the ZQ calibration operation. The ZQ calibration operation may indicate an operation of adjusting the pull-up code PUCODE and the pull-down code PDCODE, and may be referred to as an "impedance calibration operation".
Address register 1460 may receive and temporarily store address ADD from input buffer 1312. The address register 1460 may provide a row address RA to the row decoder 1420 under the control of the command decoder 1450. Address register 1460 may provide column address CA to column decoder 1430 under control of command decoder 1450. The address register 1460 may provide an operation code OPCODE to the mode register 1470 under the control of the command decoder 1450.
The mode register 1470 may store an operation code or value for setting an operation mode of the memory device 1000, but is not limited thereto. For example, mode register 1470 may store an operation code to set the value of the termination resistor provided to each of pads 1111, 1112, and 1113. For example, the value of the termination resistor may be set to any one of RZQ/1, RZQ/2, RZQ/3, ·, and RZQ/K (here, K is a natural number) according to the operation code.
The serializer and deserializer 1480 may receive write data from the input buffer 1313 and may parallelize bits of the write data. The serializer and deserializer 1480 may provide write data including the parallelized bits to the write driver and input/output sense amplifiers 1440. The serializer and deserializer 1480 may receive read data from the write driver and input/output sense amplifier 1440 and may serialize the bits of the read data. The serializer and deserializer 1480 may provide read data including the serialized bits to the output driver 1323.
In at least one example embodiment, the memory cell array 1410, the row decoder 1420, the column decoder 1430, the write driver and the input/output sense amplifier 1440, the command decoder 1450, the address register 1460, the mode register 1470, and/or the serializer and deserializer 1480, etc., may operate based on the power supply voltages VDD and VSS. In contrast, the circuits connected to the pads 1111 to 1114 may operate based on the power supply voltages VDDQ and VSSQ instead of the power supply voltages VDD and VSS. For example, the calibration circuit 1200, the input buffers 1311 to 1313, the ODT circuits 1321 and 1322, and/or the output driver 1323 and the like may operate based on the supply voltages VDDQ and VSSQ. The circuit operating based on the supply voltages VDDQ and VSSQ may be independent of the supply voltages VDD and VSS and may not affect noise generated by and/or corresponding to the supply voltages VDD and VSS. Of course, unlike the illustration of fig. 12, the circuits connected to the pads 1111 to 1114 may operate based on the power supply voltages VDD and VSS.
Fig. 13 is a timing diagram of a calibration circuit in a case where a ZQ calibration code is input to the memory device of fig. 12 according to at least one example embodiment. Fig. 13 will be described with reference to fig. 12, but is not limited thereto. In the case where the ZQ calibration command is input to the memory device 1000, the command decoder 1450 may activate the control signal ZQCAL _ EN at time T1, but example embodiments are not limited thereto.
At time T2, the controller of the calibration circuit 1200 (refer to
At time T3, the controller of the calibration circuit 1200 may not activate the first control signal ZQPU _ EN. At time T3, the new pull-up code (i.e., the final pull-up code) adjusted by the calibration operation may be stored to the register (refer to
At time T4, the controller of the calibration circuit 1200 may activate the second control signal ZQPD _ EN. The calibration circuit 1200 may adjust or calibrate the pull-down code PDCODE starting at time T4.
At time T5, the controller of the calibration circuit 1200 may not activate the second control signal ZQPD _ EN. At time T5, the new pull-down code (i.e., the final pull-down code) adjusted by the calibration operation may be stored to the register (refer to
At time T6, command decoder 1450 may not activate control signal ZQCAL _ EN. For example, the calibration circuit 1200 may complete the ZQ calibration operation within a desired and/or preset time corresponding to the time interval from time T1 to time T6.
Fig. 14 is a block diagram illustrating the output driver of fig. 12 according to at least one example embodiment. Fig. 14 will be described with reference to fig. 12. But is not limited thereto. The output driver 1323 may include pull-up units 1323_11 to 1323_17 connected between the power supply voltage VDDQ and the pad 1113 and the like, but is not limited thereto. The output driver 1323 may include pull-down units 1323_21 to 1323_27 connected between the pad 1113 and the power supply voltage VSSQ, but is not limited thereto.
The pull-up codes PUCODE generated by the calibration circuit 1200 may be provided to the pull-up units 1323_11 to 1323_17, respectively. The resistance value of each of the pull-up units 1323_11 to 1323_17 based on the pull-up code PUCODE may be the same as the resistance value of the external resistor RZQ. The configuration of each of the pull-up units 1323_11 to 1323_17 may be the same as that of the above-described pull-up unit 120_1, 120_2, 220_ i (i is one of 1 to 8) or the pull-up
The pull-down code PDCODE generated by the calibration circuit 1200 may be provided to the pull-down units 1323_21 to 1323_27, respectively. The resistance value of each of the pull-down units 1323_21 to 1323_27 based on the pull-down code PDCODE may be the same as the resistance value of the external resistor RZQ. The configuration of each of the pull-down units 1323_21 to 1323_27 may be the same as that of the above-described pull-down
In at least one example embodiment, the number of pull-up units electrically connected between the power supply voltage VDDQ and the pad 1113 among the pull-up units 1323_11 to 1323_17 may be determined according to an operation code for adjusting a termination resistance value of the pad 1113 stored in the mode register 1470. The number of pull-down cells electrically connected between the pad 1113 and the power supply voltage VSSQ among the pull-down cells 1323_21 to 1323_27 may be determined according to the operation code stored in the mode register 1470. The termination resistance value may decrease as the number of pull-up cells electrically connected between the power supply voltage VDDQ and the pad 1113 and the number of pull-down cells electrically connected between the pad 1113 and the power supply voltage VSSQ increase. Accordingly, the number of the pull-up units 1323_11 to 1323_17 and the number of the pull-down units 1323_21 to 1323_27 are not limited to the illustration of fig. 14, and may be "K" described with reference to fig. 12.
The calibration circuit according to at least one example embodiment of the inventive concept may adjust both the pull-up code and the pull-down code by using a common node shared by the pull-up calibration path and the pull-down calibration path and one comparator connected to the common node. Accordingly, PVT variation of the calibration circuit may be improved, and a block margin tool (RMT) of a semiconductor memory device including the calibration circuit may be improved.
Although some example embodiments of the inventive concept have been described with reference to example embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.