Semiconductor device and method for manufacturing the same
阅读说明：本技术 半导体器件以及该半导体器件的制造方法 (Semiconductor device and method for manufacturing the same ) 是由 严大成 于 2019-03-15 设计创作，主要内容包括：半导体器件以及该半导体器件的制造方法。一种半导体器件包括：多个导电图案,其在第一方向上层叠并彼此间隔开以形成阶梯结构；阶梯绝缘层,其与阶梯结构交叠；接触插塞,其在第一方向上延伸穿过阶梯绝缘层以与导电图案的各个接触部分接触；以及屏障图案,其设置在阶梯绝缘层的侧壁上。(A semiconductor device and a method of manufacturing the semiconductor device. A semiconductor device includes: a plurality of conductive patterns stacked in a first direction and spaced apart from each other to form a stepped structure; a step insulating layer overlapping the step structure; contact plugs extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive patterns; and a barrier pattern disposed on a sidewall of the step insulating layer.)
1. A semiconductor device, comprising:
a conductive pattern, wherein a plurality of the conductive patterns are stacked in a first direction and spaced apart from each other to form a stepped structure;
a step insulating layer overlapping the step structure;
a contact plug extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive pattern exposed through the stepped structure; and
a barrier pattern disposed on a sidewall of the step insulating layer.
2. The semiconductor device of claim 1, wherein interfaces between the sidewalls of the step insulating layer and the barrier pattern are aligned with sidewalls of the conductive pattern, respectively.
3. The semiconductor device according to claim 1, wherein a plurality of the barrier patterns are spaced apart from each other in a direction in which the contact portion extends.
4. The semiconductor device according to claim 1, wherein a plurality of the barrier patterns are provided at different levels in the first direction.
5. The semiconductor device according to claim 1, wherein each of the contact plugs is disposed between adjacent barrier patterns of the plurality of barrier patterns.
6. The semiconductor device as set forth in claim 1,
wherein the barrier pattern includes a first barrier pattern disposed at a first side of a first contact plug among the plurality of contact plugs and a second barrier pattern disposed at a second side of the first contact plug, and
wherein the first side and the second side are opposite sides of the first contact plug.
7. The semiconductor device as set forth in claim 6,
wherein the first contact plug is in contact with a sidewall of one of the first and second barrier patterns and is spaced apart from the other of the first and second barrier patterns.
8. The semiconductor device of claim 6, wherein the first contact plug is spaced apart from the first and second barrier patterns.
9. The semiconductor device according to claim 6, wherein the first contact plug comprises:
a first portion extending along a sidewall of one of the first and second barrier patterns and spaced apart from the other of the first and second barrier patterns; and
a second portion protruding from the first portion and overlapping a top surface of the one of the first and second barrier patterns.
10. The semiconductor device according to claim 1, wherein a width of each of the barrier patterns is smaller than a width of each of the contact portions in a direction in which the contact portions extend.
11. The semiconductor device of claim 1, wherein the barrier pattern comprises a different material than the step insulating layer.
12. The semiconductor device of claim 1, wherein the barrier pattern comprises a conductive material.
13. The semiconductor device of claim 1, wherein the barrier pattern comprises at least one of polysilicon, a nitride layer, a titanium nitride layer, and a metal layer.
14. The semiconductor device of claim 1, further comprising:
an interlayer insulating layer disposed between the plurality of conductive patterns;
a channel layer passing through the interlayer insulating layer and the conductive pattern; and
a multi-layer memory layer disposed between each of the conductive patterns and the channel layer.
15. The semiconductor device of claim 1, further comprising a support structure extending in the first direction through at least one of the plurality of conductive patterns,
wherein at least one of the plurality of barrier patterns is disposed between one of the plurality of support structures and one of the plurality of contact plugs.
16. A semiconductor device, comprising:
a conductive pattern including a contact portion, wherein the conductive pattern extends in a horizontal direction;
a first barrier pattern disposed at a first level higher than the conductive pattern;
a second barrier pattern disposed at a second level higher than the conductive pattern, the second level being lower than the first level, wherein the second barrier pattern is spaced apart from the first barrier pattern in the horizontal direction; and
a contact plug disposed between the first barrier pattern and the second barrier pattern, wherein the contact plug extends in a vertical direction to contact the contact portion.
17. The semiconductor device of claim 16, further comprising a step insulating layer disposed between the first and second barrier patterns and the conductive pattern.
18. The semiconductor device of claim 16, wherein the first and second barrier patterns comprise at least one of polysilicon, a nitride layer, a titanium nitride layer, and a metal layer.
19. The semiconductor device of claim 16, wherein the contact plug is in contact with a sidewall of one of the first and second barrier patterns and spaced apart from the other of the first and second barrier patterns.
20. The semiconductor device of claim 16, wherein the contact plug is spaced apart from the first and second barrier patterns.
21. The semiconductor device of claim 16, wherein the contact plug extends along sidewalls and a top surface of one of the first and second barrier patterns and is spaced apart from the other of the first and second barrier patterns.
22. A method of manufacturing a semiconductor device, the method comprising:
forming a stepped laminate structure including first material layers and second material layers alternately laminated;
forming a step insulating layer overlapping the step laminated structure;
forming a plurality of barrier patterns spaced apart from each other on sidewalls of the step insulating layer; and
forming a contact plug through the stepped insulating layer between the plurality of barrier patterns.
23. The method of claim 22, wherein the step of forming the barrier pattern comprises the steps of:
forming a barrier layer on a surface of the step insulating layer; and
the barrier layer is etched to expose a top surface of the step insulating layer.
24. The method of claim 22, further comprising forming a channel layer through the stepped, stacked structure.
25. The method of claim 22, wherein the barrier pattern comprises a conductive material.
26. The method of claim 22, wherein each of the barrier patterns comprises at least one of polysilicon, a nitride layer, a titanium nitride layer, and a metal layer.
27. The method of claim 22, wherein the first and second portions are selected from the group consisting of,
wherein the plurality of barrier patterns include a first barrier pattern disposed at a first side of a first contact plug among the plurality of contact plugs and a second barrier pattern disposed at a second side of the first contact plug, and
wherein the first side and the second side are opposite sides of the first contact plug.
28. The method of claim 27, wherein the first contact plug is in contact with a sidewall of one of the first and second barrier patterns and is spaced apart from the other of the first and second barrier patterns.
29. The method of claim 27, wherein the first contact plug is spaced apart from the first barrier pattern and the second barrier pattern.
30. The method of claim 27, wherein the first contact plug overlaps one of the first and second barrier patterns and is spaced apart from the other of the first and second barrier patterns.
Technical Field
Various embodiments relate generally to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a conductive pattern in contact with a contact plug and a method of manufacturing the same.
Background
The semiconductor device may include a plurality of memory cells capable of storing data. The memory cell may be coupled to the conductive pattern. An operating voltage for controlling the memory cell may be applied to the conductive pattern. An operating voltage applied from the peripheral circuit may be applied to the conductive pattern via the contact plug. Thus, the contact plug and the conductive pattern need to be accurately aligned when manufacturing the semiconductor device.
When the contact plug and the conductive pattern are misaligned, different conductive patterns may be coupled to a single contact plug. Therefore, bridging of adjacent conductive pattern interconnects may result. Due to the bridging, an operation error of the semiconductor device may occur.
A three-dimensional semiconductor device configured such that memory cells are stacked in a vertical direction is provided to improve the integration density of the memory cells. In the three-dimensional semiconductor device, conductive patterns coupled to gates of memory cells may be stacked to be spaced apart from each other. Due to these structural characteristics of the three-dimensional semiconductor device, bridging between conductive patterns caused by misalignment between contact plugs may easily occur.
Disclosure of Invention
According to an embodiment, a semiconductor device may include: conductive patterns stacked in a first direction and spaced apart from each other to form a stepped structure; a step insulating layer overlapping the step structure; contact plugs extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive patterns; and a barrier pattern disposed on a sidewall of the step insulating layer. The contact portion of the conductive pattern is exposed through the stepped structure.
According to an embodiment, a semiconductor device may include: a conductive pattern including a contact portion and extending in a horizontal direction; a first barrier pattern disposed at a first level higher than the conductive pattern; a second barrier pattern disposed at a second level lower than the first level higher than the conductive pattern and spaced apart from the first barrier pattern in a horizontal direction; and a contact plug disposed between the first barrier pattern and the second barrier pattern and extending in a vertical direction to contact the contact portion.
According to an embodiment, a method of manufacturing a semiconductor device may include: forming a stepped laminate structure including first material layers and second material layers alternately laminated; forming a step insulating layer overlapping the step laminated structure; forming barrier patterns spaced apart from each other on sidewalls of the step insulating layer; and forming a contact plug between the barrier patterns through the step insulating layer.
Drawings
Fig. 1A, 1B, 1C, and 1D are cross-sectional views illustrating a semiconductor device according to an embodiment of the present disclosure.
Fig. 2A and 2B are diagrams illustrating a three-dimensional semiconductor device according to an embodiment of the present disclosure.
Fig. 3A and 3B are cross-sectional views illustrating the three-dimensional semiconductor device illustrated in fig. 2A.
Fig. 4A, 4B, 4C, 4D, 4E, 4F, 4G, and 4H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 5 is a cross-sectional view illustrating a three-dimensional semiconductor device according to an embodiment of the present disclosure.
Fig. 6A, 6B, 6C, 6D, 6E, and 6F are cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the present disclosure.
Fig. 7A, 7B, and 7C are cross-sectional views illustrating a three-dimensional semiconductor device according to various embodiments of the present disclosure.
Fig. 8 is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure.
Fig. 9 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.
Fig. 10 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure.
Detailed Description
The technical spirit of the present disclosure may include examples to which various modifications and changes may be applied and which include various forms of embodiments. Hereinafter, various embodiments of the present disclosure are described so that those skilled in the art to which the present disclosure pertains can easily realize the technical spirit of the present disclosure.
Although terms such as "first" and "second" may be used to describe various components, these components should not be construed as limited to the above terms. The above terms are used to distinguish one component from another component, e.g., a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the concept according to the present disclosure.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Moreover, other expressions describing a relationship between components (e.g., "between," "directly between," or "adjacent to" and "directly adjacent to") may be similarly construed.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms in this disclosure are intended to include the plural forms as well, unless the context clearly indicates otherwise. In this specification, it should be understood that the terms "comprises" or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
Embodiments of the present disclosure provide a semiconductor device capable of improving operational reliability and a method of manufacturing the semiconductor device.
Fig. 1A to 1D are cross-sectional views illustrating a semiconductor device according to an embodiment of the present disclosure. Fig. 1A to 1D are cross-sectional views of a part of a semiconductor device for illustrating alignment between a contact portion of a conductive pattern and a contact plug.
Referring to fig. 1A to 1D, the semiconductor device may include a conductive pattern CP, a contact plug CT, and a barrier pattern BP.
The conductive patterns CP may be stacked in the first direction I to be spaced apart from each other. The conductive patterns CP may include contact portions CTP, respectively. The conductive patterns CP may be stacked on each other to form a stepped structure to expose the contact portion CTP. Each interlayer insulating layer ILD may be disposed under each conductive pattern CP. In other words, the interlayer insulating layer ILD and the conductive pattern CP may be alternately stacked in the first direction I. In order to individually control the conductive patterns CP, the conductive patterns CP may be electrically insulated from each other through respective interlayer insulating layers ILD. Each conductive pattern CP may extend in a horizontal direction crossing the first direction I. For example, each conductive pattern CP may extend in the second direction II crossing the first direction I. The contact portion CTP of the conductive pattern CP may be arranged in the second direction II (e.g., a direction in which the contact portion CTP extends). From a vertical angle, the contact portions CTP of the conductive pattern CP may be arranged at different levels from each other.
The contact plugs CT may be respectively in contact with the contact portions CTP, and may extend in the first direction I. The contact plug CT may pass through the step insulating layer SI covering the contact portion CTP. Each contact plug CT may include a first portion P1 passing through the stepped insulation layer SI and a second portion P2 protruding further from the first portion P1 in the first direction I beyond the stepped insulation layer SI.
The step insulating layer SI may overlap a step structure defined by the conductive pattern CP and the interlayer insulating layer ILD. The step insulating layer SI may include a plurality of sidewalls defined by a step shape.
The barrier patterns BP may be respectively disposed on sidewalls of the step insulating layer SI. The barrier patterns BP may be spaced apart from each other in the second direction II. From a perpendicular angle, the barrier patterns BP may be arranged at different levels from each other.
The barrier patterns BP may overlap with the contact portions CTP, respectively, and the contact portions CTP may be opened between the barrier patterns BP.
Each barrier pattern BP may have a first width W1 from a boundary between the contact portions CTP toward an end of each contact portion CTP in a plan view. In the second direction II, the first width W1 may be less than the second width W2 of each contact portion CTP.
Each barrier pattern BP may include a material that may be used as an etch stop layer during a process of forming the contact plug CT. More specifically, each barrier pattern BP may include a material different from the step insulating layer SI. In other words, the material of the barrier patterns BP and the material of the stepped insulating layer SI may have a mutual etch selectivity such that each barrier pattern BP may serve as an etch stop layer when the stepped insulating layer SI is etched. For example, the step insulating layer SI may include an oxide layer, and the barrier pattern BP may include a conductive material or a nitride layer. More specifically, the barrier pattern BP may include at least one of polysilicon, a nitride layer, a titanium nitride layer, and a metal layer.
The barrier pattern BP may be used as an etch stop layer when forming the contact plug CT. Therefore, even when the contact plugs CT overlap the barrier pattern BP, the contact plugs CT are less likely to pass through the barrier pattern BP. Thus, according to the embodiment of the present disclosure, the alignment margin of the contact plug CT may further ensure as much as the first width W1 of the barrier pattern BP by the barrier pattern BP.
Each contact plug CT may be disposed between each pair of barrier patterns BP adjacent to each other. The layouts of the contact plugs CT and the barrier patterns BP may vary within a margin of error of the process.
The contact plugs CT may include first contact plugs CTa. The barrier pattern BP may include a first barrier pattern BP1 and a second barrier pattern BP2 disposed at opposite sides of the first contact plug CTa. The first contact plugs CTa may be any one of the contact plugs CT, and the first barrier pattern BP1 and the second barrier pattern BP2 may be any one pair of barrier patterns BP adjacent in the second direction II. Hereinafter, the first contact plugs CTa, the first barrier patterns BP1, and the second barrier patterns BP2 may be described with respect to various layouts of the contact plugs CT and the barrier patterns BP as examples. The layout of the first contact plugs CTa may be applied to the respective contact plugs CT, and the layouts of the first barrier pattern BP1 and the second barrier pattern BP2 may be applied to the barrier patterns BP, respectively. A conductive pattern contacting the first contact plug CTa among the conductive patterns CP may be defined as a first conductive pattern CPa, and a contact portion of the first conductive pattern CPa may be defined as a first contact portion CTPa.
The first barrier pattern BP1 may be disposed at a first level LV1 higher than the first conductive pattern CPa. The second barrier pattern BP2 may be spaced apart from the first barrier pattern BP1 in a plan view (e.g., spaced apart from the first barrier pattern BP1 in a horizontal direction), and may be disposed at a second level LV2 lower than the first level LV1, which is higher than the first conductive pattern CPa, from a vertical angle. The first conductive pattern CPa may extend in a horizontal direction and have a first contact portion CTPa overlapping the first barrier pattern BP 1. The first contact portion CTPa may extend to protrude further beyond the first barrier pattern BP1 in the second direction II. In other words, the first contact portion CTPa may extend between the first barrier pattern BP1 and the second barrier pattern BP2 in a plan view. In an embodiment, the step insulating layer SI may be disposed between the first and second barrier patterns (BP1 and BP2) and the first conductive pattern CPa.
The first contact plugs CTa may be disposed between the first barrier pattern BP1 and the second barrier pattern BP2, and may be in contact with the first contact portions CTPa. In an embodiment, the first contact plug CTa may extend in a vertical direction to contact the first contact portion CTPa.
Referring to fig. 1A, the first contact plugs CTa may be in contact with sidewalls of the second barrier pattern BP2 and may be spaced apart from the first barrier pattern BP 1. More specifically, the first portions P1 of the first contact plugs CTa may contact sidewalls of the second barrier patterns BP2 and pass through the stepped insulation layer SI. The second portion P2 of the first contact plug CTa may linearly protrude from the first portion P1 in the first direction I without overlapping the top surface of the second barrier pattern BP 2.
Although not shown in fig. 1A, the first contact plugs CTa may contact sidewalls of the first barrier patterns BP1 and may linearly protrude in the first direction I to be spaced apart from the second barrier patterns BP 2.
Referring to fig. 1B, the first contact plugs CTa may overlap the top surface of the second barrier pattern BP2 and contact the sidewalls of the second barrier pattern BP2 and be spaced apart from the first barrier pattern BP 1. More specifically, the first portions P1 of the first contact plugs CTa may contact sidewalls of the second barrier patterns BP2 and pass through the stepped insulation layer SI. The second portion P2 of the first contact plug CTa may protrude from the first portion P1 in the second direction II to overlap the top surface of the second barrier pattern BP 2. The second portion P2 of the first contact plug CTa may extend in the first direction I. The first contact plugs CTa may overlap the top surfaces of the second barrier patterns BP2 within the range of the first width W1 ensured by the second barrier patterns BP 2. The second barrier pattern BP2 may be used as an etch stop layer during the manufacturing process of the contact hole filled by the first contact plug CTa. Thus, even when the second portion P2 of the first contact plug CTa overlaps the top surface of the second barrier pattern BP2, the first contact plug CTa is less likely to pass through the second barrier pattern BP 2.
Referring to fig. 1C, the first contact plug CTa may pass through the step insulating layer SI to contact the first contact portion CTPa at a position spaced apart from the first and second barrier patterns BP1 and BP 2.
Referring to fig. 1D, the first contact plugs CTa may overlap the top surface of the first barrier pattern BP1 and contact the sidewalls of the first barrier pattern BP1 and be spaced apart from the second barrier pattern BP 2. More specifically, the first portions P1 of the first contact plugs CTa may contact sidewalls of the first barrier patterns BP1 and pass through the stepped insulation layer SI. The second portion P2 of the first contact plug CTa may protrude from the first portion P1 in a horizontal direction to overlap the top surface of the first barrier pattern BP 1. The second portion P2 of the first contact plug CTa may extend in the first direction I. The first contact plugs CTa may overlap the top surfaces of the first barrier patterns BP1 within the range of the first width W1 ensured by the first barrier patterns BP 1. The first barrier pattern BP1 may be used as an etch stop layer during a manufacturing process of the contact hole filled with the first contact plug CTa. Thus, even when the second portion P2 of the first contact plug CTa overlaps the top surface of the first barrier pattern BP1, the first contact plug CTa is less likely to pass through the first barrier pattern BP 1.
When the barrier pattern BP shown in fig. 1A, 1B, or 1D includes a conductive material, each barrier pattern BP may contact each contact plug CT. Therefore, the barrier pattern BP may reduce the resistance of the contact plug CT.
The structures illustrated in fig. 1A to 1D are applicable to various semiconductor devices including memory cells arranged in a two-dimensional structure or various semiconductor devices including memory cells arranged in a three-dimensional structure.
Fig. 2A and 2B are diagrams illustrating a three-dimensional semiconductor device according to an embodiment of the present disclosure. More specifically, fig. 2A is a plan view illustrating a word line of the three-dimensional semiconductor device according to the embodiment, and fig. 2B is an enlarged view of an X region illustrated in fig. 2A.
Referring to fig. 2A, the three-dimensional semiconductor device according to the embodiment of the present disclosure may include a stepped stack structure SWS divided by a cutting structure CU. Each of the staircase stacked structures SWS may include a plurality of word lines WL stacked to be spaced apart from each other. The word lines WL may be conductive patterns extending from gates of the memory cells. Each of the stair-step stacked structures SWS may include a cell array region CAR and a contact region CTR.
The cell array region CAR of each stepped stack structure SWS may be penetrated by the channel pillar PL. The outer wall of each channel pillar PL may be surrounded by a plurality of memory layers ML. The contact region CTR of each stepped stacked structure SWS may include a contact portion CTP _ W of the word line WL. The word line WL may form a stepped structure to expose the contact portion CTP _ W.
The three-dimensional semiconductor device according to the embodiment of the present disclosure may include a barrier pattern BP. The barrier patterns BP may be separated from each other by a cutting structure CU. In a plan view, the barrier pattern BP may extend along sidewalls of the word lines WL.
The three-dimensional semiconductor device according to the embodiment of the present disclosure may include contact plugs WCT respectively contacting the word lines WL. Each contact plug WCT may be disposed on an end of each contact portion CTP _ W. The contact plugs WCT may be coupled to the barrier patterns BP, respectively. Each stepped stacked structure SWS may be penetrated by the support structure SP. Each barrier pattern BP may be disposed between one of the support structures SP and one of the contact plugs WCT. The support structure SP and the contact plug WCT may be arranged collinearly. However, the embodiments of the present disclosure are not limited thereto. For example, the support structures SP and the contact plugs WCT may be arranged in a zigzag format or may be arranged tiltably.
Referring to fig. 2B, each channel pillar PL may include a vertical channel VCH including a semiconductor layer. For example, the vertical channel VCH may include a silicon layer. The vertical channel VCH may have various structures. For example, the vertical channel VCH may have a circular cross-section defining a core region COA. The core region COA may be completely filled by the vertical channel VCH. In another example, the core region COA may be filled with at least one of an insulating layer and a doped semiconductor layer.
The multi-layer memory layer ML may be disposed between the channel pillars PL and the word lines WL. The multi-layer memory layer ML may include a tunnel insulating layer TI configured to surround the vertical channel VCH, a data storage layer DL configured to surround the tunnel insulating layer TI, and a blocking insulating layer BI configured to surround the data storage layer DL. The data storage layer DL may store data changed using Fowler-Nordheim (Fowler-Nordheim) tunneling caused by a voltage difference between the word line WL and the vertical channel VCH. For this operation, the data storage layer DL may include various materials, such as a nitride layer capable of trapping charges. However, embodiments of the present disclosure are not limited thereto, and the data storage layer DL may include silicon, a phase change material, nanodots, and the like. The blocking insulating layer BI may include an oxide layer capable of blocking charges. The tunnel insulating layer TI may include a silicon oxide layer that can perform charge tunneling.
Memory cells may be formed at the intersections of word lines WL and vertical channels VCH. The vertical channel VCH may serve as a channel of the memory cell.
Fig. 3A and 3B are cross-sectional views illustrating the three-dimensional semiconductor device illustrated in fig. 2A. More specifically, fig. 3A is a cross-sectional view taken along line a-a 'of fig. 2A, and fig. 3B is a cross-sectional view taken along line B-B' of fig. 2A.
Referring to fig. 3A and 3B, respective interlayer insulating layers ILD may be disposed between respective pairs of word lines WL adjacent to each other. The stacked structure of the interlayer insulating layer ILD and the word line WL may be the same as the stacked structure of the interlayer insulating layer ILD and the conductive pattern CP shown in fig. 1A to 1D.
The stacked structure of the interlayer insulating layer ILD and the word line WL may be covered by a step insulating layer SI. The step insulating layer SI may have the same structure and include the same material as the step insulating layer SI shown in fig. 1A to 1D. A part of the step insulating layer SI may be penetrated by the contact plug WCT as shown in fig. 3A. The arrangement of the contact plugs WCT is not limited to the example shown in fig. 3A, and may be the same as one of the arrangements of the contact plugs CT shown in fig. 1A to 1D.
The barrier pattern BP may be formed on sidewalls of the step insulating layer SI. The barrier pattern BP may include the same material and have the same layout as the barrier pattern BP shown in fig. 1A to 1D.
As shown in fig. 3A, the stacked structure of the interlayer insulating layer ILD and the word line WL may be further penetrated by the support structure SP. The support structure SP may extend in a stacking direction of the interlayer insulating layer ILD and the word line WL, and support the stacked structure when forming the three-dimensional semiconductor device. The support structure SP may include an insulating material. For example, the support structure SP may include an oxide layer. In some embodiments, the support structure SP may be omitted.
Referring to fig. 3B, the interfaces between the respective sidewalls of the stepped insulating layer SI and the respective barrier patterns BP may be aligned with the sidewalls of the respective word lines WL.
Fig. 4A to 4H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. More specifically, fig. 4A to 4H are cross-sectional views showing a sectional view taken along line a-a' of fig. 2A, which shows a staged manufacturing process.
Referring to fig. 4A, the stepped laminate structure ST includes first material layers 111 and second material layers 113 alternately laminated on a pre-formed lower structure (not shown). The infrastructure can include various compositions. According to an embodiment, the lower structure may include a tube gate PG shown in fig. 5. According to another embodiment, the lower structure may include the source dopant region SDA shown in fig. 7A and 7B. According to another embodiment, the lower structure may include a dopant region DA1 as shown in fig. 7C.
The
According to the first embodiment, the
According to the second embodiment, the
According to the third embodiment, the
The
Subsequently, a
Referring to fig. 4B, a
Referring to fig. 4C, the
Referring to fig. 4D, a planarized
Fig. 4E and 4F show the first embodiment described with reference to fig. 4A as an example.
Referring to fig. 4E, a support structure 161 may be formed. The manufacturing process of the support structure 161 may be omitted in some embodiments. For example, according to the second embodiment described with reference to fig. 4A, the manufacturing process of the support structure 161 may be omitted.
After forming the support structure 161, the
Referring to fig. 4F, the gate regions GA shown in fig. 4E may be filled with
The conductive material may flow into the gate region GA shown in fig. 4E through the slit of the cutting structure CU shown in fig. 2A. Each of the
Although not shown, after the
Fig. 4E and 4F show the first embodiment described with reference to fig. 4A, wherein the second material layer is replaced by a conductive pattern. However, the present disclosure is not limited thereto.
For example, according to the second embodiment described with reference to fig. 4A, the process of replacing the second material layer with the conductive pattern may be omitted, and the subsequent process shown in fig. 4G may be performed. In another example, according to the third embodiment described with reference to fig. 4A, the subsequent process shown in fig. 4G may be performed after the first material layer is replaced by the insulating layer.
Referring to fig. 4G, a
Referring to fig. 4H, each of the contact holes 190 may be filled with a conductive material. Thereby, the
Fig. 5 is a cross-sectional view illustrating a three-dimensional semiconductor device according to an embodiment of the present disclosure. The semiconductor device shown in fig. 5 may include the structure shown in fig. 2A and 2B.
Referring to fig. 5, the three-dimensional memory device may include a memory string MCR. The memory string MCR may be defined along the pipe channel PCH and at least one pair of first and second vertical channels VCH1 and VCH2 coupled to the pipe channel PCH. Although fig. 5 illustrates the memory string MCR including the first and second vertical channels VCH1 and VCH2 coupled to the pipe channel PCH and defined as a U-shape for convenience of explanation, the memory string MCR may have various structures such as a W-shape.
Each of the first vertical channel VCH1 and the second vertical channel VCH2 may extend in the first direction I. The first vertical channel VCH1 may pass through the first stepped stacked structure SWS1 and the second vertical channel VCH2 may pass through the second stepped stacked structure SWS 2. Each of the first and second step lamination structures SWS1 and SWS2 may include contact portions CTP _ S and CTP _ W. The contact portions CTP _ S and CTP _ W may be arranged in a second direction II crossing the first direction I. Although fig. 5 shows only the contact portions CTP _ S and CTP _ W of the second stepped stack structure SWS2, the first stepped stack structure SWS1 may also include contact portions arranged in the second direction II.
The first and second stepped stacked structures SWS1 and SWS2 may have the same stacked structure. The first and second stepped stacked structures SWS1 and SWS2 may be separated from each other by a cutting structure CU and may be adjacent to each other in the third direction III. The third direction III may intersect the first direction I and the second direction II.
The stacked structure of each of the first and second stepped stacked structures SWS1 and SWS2 may include interlayer insulating layers ILD and conductive patterns DSL, WLd, SSL, and WLs that are alternately stacked. More specifically, the conductive pattern of the first cascade stack structure SWS1 may include drain-side word lines WLd stacked to be spaced apart from each other and at least one drain select line DSL disposed over the drain-side word lines WLd. The conductive pattern of the second stepped stack structure SWS2 may include source-side word lines WLs stacked to be spaced apart from each other and at least one source selection line SSL disposed above the source-side word lines WLs.
The first and second step lamination structures SWS1 and SWS2 may be covered by a step insulating layer SI, and the step insulating layer SI may be penetrated by the cutting structure CU. The first vertical channel VCH1 and the second vertical channel VCH2 may extend to pass through the step insulating layer SI.
The tube channel PCH may be embedded in the tube gate PG disposed under the first and second step-stacked structures SWS1 and SWS 2. The tube gate PG may include various conductive materials. For example, the tube gate PG may include a doped silicon layer as a multi-layer stack. The cutting structure CU may overlap the tube gate PG.
The pipe channel PCH may be integrated with the first vertical channel VCH1 and the second vertical channel VCH 2. As described above, the channel layer CH including the pipe channel PCH, the first vertical channel VCH1, and the second vertical channel VCH2 may be used as a channel of the memory string MCR. The channel layer CH may include a semiconductor layer such as a silicon layer.
The multi-layer memory layer ML may extend along an outer wall of the channel layer CH. In an embodiment, the multi-layer memory layer ML may be disposed between the respective conductive patterns (DSL, WLd, SSL, and WLs) and the channel layer CH. The multi-layer memory layer ML may include the material layers described with reference to fig. 2B. The core region of the channel layer CH may be filled with the core insulating layer CO. The core insulating layer CO may have a height less than the first and second vertical channels VCH1 and VCH 2. The first and second doped semiconductor patterns CAP1 and CAP2 may be disposed at opposite sides of the core insulating layer CO. The first doped semiconductor pattern CAP1 may function as a drain junction. The second doped semiconductor pattern CAP2 may serve as a source junction. Each of the first and second doped semiconductor patterns CAP1 and CAP2 may include a doped silicon layer.
The barrier pattern BP may be formed on sidewalls of the step insulating layer SI. The barrier pattern BP and the step insulating layer SI may be covered by the planarization insulating pattern PD. The structure and material of each of the barrier pattern BP and the step insulating layer SI may be the same as those described with reference to fig. 1A to 1D. The planarization insulating pattern PD and the step insulating layer SI may be penetrated by the support structure SP extending in the first direction I. The support structure SP may pass through contact portions CTP _ S and CTP _ W of each of the first and second stepped stacked structures SWS1 and SWS 2. According to an embodiment, the support structure SP may pass through at least one of the conductive patterns DSL, WLd, SSL, and WLs.
The etch stop layer ES and the first, second, and third upper insulating layers UI1, UI2, and UI3 may be stacked on the planarization insulating pattern PD. The etch stop layer ES may include a nitride layer. The first upper insulating layer UI1 may be formed on the etch stop layer ES and may include an oxide layer. The etch stop layer ES and the first upper insulating layer UI1 may be penetrated by the contact plugs CT1, CT2, SCT, and WCT.
The contact plugs CT1, CT2, SCT, and WCT may include first and second contact plugs CT1 and CT2 disposed at the cell region CAR and select and word contact plugs SCT and WCT disposed at the contact region CTR. The first contact plug CT1 may contact the first doped semiconductor pattern CAP 1. The second contact plug CT2 may contact the second doped semiconductor pattern CAP 2. The select contact plug SCT may be in contact with a select line (e.g., SSL). The word contact plugs WCT may contact word lines (e.g., WLs). The select contact plugs SCT and the word contact plugs WCT may also pass through the planarized insulation pattern PD and the stepped insulation layer SI. Each barrier pattern BP may be disposed between the contact plug and the support structure adjacent to each other. In other words, one of the barrier patterns BP may be disposed between one of the support structures SP disposed at the contact region CTR and one of the contact plugs (SCT and WCT).
The common source line CSL and the first connection wire LL1 may be formed on the first upper insulating layer UI 1. The common source line CSL may be coupled to the second contact plugs CT2, and the first connection conductive line LL1 may be coupled to the contact plugs SCT and WCT disposed at the contact region CTR, respectively. Each of the first connection wires LL1 may be used as a pad to increase contact margin.
The common source line CSL and the first connection wire LL1 may pass through the second upper insulating layer UI2 stacked on the first upper insulating layer UI 1.
The third upper insulating layer UI3 formed on the second upper insulating layer UI2 may be penetrated by the upper contact plug UCT. Each upper contact plug UCT may contact each first connection wire LL 1.
The first connection wires LL1 may be coupled to second connection wires LL2 formed on the third upper insulating layer UI3 via upper contact plugs UCT, respectively. The second connection wire LL2 may be provided on the same layer as the bit line BL. The bit line BL may be electrically coupled to the first doped semiconductor pattern CAP1 via a first contact plug CT1 extending to pass through the second and third upper insulating layers UI2 and UI 3.
According to the structure shown in fig. 5, a drain select transistor may be formed at an intersection of the first vertical channel VCH1 and the drain select line DSL, and a drain-side memory cell may be formed at an intersection of the first vertical channel VCH1 and the drain-side word line WLd. The drain-side memory cell and the drain select transistor may be coupled in series by a first vertical channel VCH 1.
In addition, a source select transistor may be formed at an intersection of the second vertical channel VCH2 and a source select line SSL, and a source side memory cell may be formed at an intersection of the second vertical channel VCH2 and a source side word line WLs. The source side memory cell and the source select transistor may be coupled in series by a second vertical channel VCH 2.
The source side memory cell and the drain side memory cell may be coupled in series by a transistor formed at an intersection of the transistor channel PCH and the transistor gate PG.
Thus, the memory string MCR shown in fig. 5 may include a drain select transistor, a drain-side memory cell, a pipe transistor, a source-side memory cell, and a source select transistor, which are coupled in series by a channel layer CH including a pipe channel PCH, a first vertical channel VCH1, and a second vertical channel VCH 2.
Fig. 6A to 6F are cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the present disclosure. The manufacturing method shown in fig. 6A to 6F can be used to form the semiconductor device shown in fig. 5. Fig. 6A to 6F are cross-sectional views taken along the second direction II shown in fig. 5 illustrating the manufacturing process. Fig. 6A to 6F show cross sections of a portion extending to the peripheral region PERI. Peripheral circuits for controlling the memory strings may be disposed at the peripheral region PERI.
Referring to fig. 6A, an active region may be defined by an
Thereafter, a lower insulating
Thereafter, the stepped stack structure ST described with reference to fig. 4A may be formed on the tube gate 205PG including the tube trench PT. The stepped stack structure ST may extend from the cell array region CAR of the
Subsequently, the stepped laminate structure ST may be etched through an etching process in which the
Thereafter, a
Referring to fig. 6B, the
Thereafter, an insulating layer 251 covering the
Referring to fig. 6C, a portion of the insulating layer may be etched by an etching process using a mask pattern (not shown) blocking the peripheral region PERI as an etching barrier to reduce a step of the insulating layer 251 of fig. 6B caused by the stepped laminate structure ST. Thereby, the insulating pattern 251P1 may be formed. After the insulating patterns 251P1 are formed, the mask pattern may be removed.
Referring to fig. 6D, in order to further planarize the surface of the insulating patterns 251P1 shown in fig. 6C, the surface of the insulating patterns 251P1 may be polished by a planarization process such as Chemical Mechanical Polishing (CMP). Thereby, the planarization insulating pattern 251P2 may be formed. A planarization process may be performed to expose a portion of the surface of the doped
Referring to fig. 6E, the
Referring to fig. 6F, a portion of the material layer of the stepped laminate structure may be replaced with the conductive pattern 271 using the process described with reference to fig. 4E and 4F.
Subsequently, an
Thereafter, an upper insulating
Thereafter, contact plugs 291SCT, 291WCT, 293, and 295 may be formed. The contact plugs 291SCT, 291WCT, 293, and 295 may pass through the upper insulating
The contact plugs 291SCT and 291WCT may be provided to have one of the layouts described with reference to fig. 1A to 1D. The
Subsequently, subsequent processes for forming the common source line CSL, the first connection wiring LL1, the upper contact plugs UCT, the bit line BL, and the second connection wiring LL2 shown in fig. 5 may be continued.
Fig. 7A to 7C are cross-sectional views illustrating a three-dimensional semiconductor device according to various embodiments of the present disclosure.
Referring to fig. 7A to 7C, the three-dimensional semiconductor device may include a straight type memory string MCR'. The memory string MCR' may include a vertical channel VCH passing through at least a portion of the staircase stacked structure SWS.
The stepped stack structure SWS may include interlayer insulating layers ILD and conductive patterns SSL, WL, and DSL alternately stacked with each other. More specifically, the conductive pattern of the stair-step stacked structure SWS may include word lines WL stacked to be spaced apart from each other, at least one drain select line DSL disposed above the word lines WL, and at least one source select line SSL disposed below the word lines WL. The stepped stacked structure SWS may be covered by a stepped insulating layer SI.
Referring to fig. 7A, the vertical channel VCH may completely pass through the stepped stack structure SWS. The vertical channel VCH may include a bottom surface in direct contact with the source dopant region SDA disposed under the stepped stack structure SWS.
Referring to fig. 7B, the vertical channel VCH may be coupled to the source dopant region SDA disposed under the stair-step stacked structure SWS via the lower channel LPC disposed under the vertical channel VCH. The vertical channel VCH may pass entirely through the word line WL of the stair-step stacked structure SWS, and the lower channel LPC may pass entirely through the source select line SSL. The lower channel LPC may be formed using a growth method such as an epitaxial growth method in which the source dopant region SDA is used as a seed layer or a deposition method using a semiconductor layer. The lower channel LPC may function as a channel of the source selection transistor, and a sidewall of the lower channel LPC may be surrounded by the gate insulating layer GI. The lower channel LPC may comprise a doped semiconductor layer.
The source dopant region SDA shown in fig. 7A and 7B may include a doped semiconductor layer and serve as a source junction or a common source line. The sidewalls of the vertical channel VCH shown in fig. 7A and 7B may be surrounded by the multi-layer memory layer ML described above with reference to fig. 2B.
Referring to fig. 7C, the vertical channel VCH may extend into the first and second dopant regions DA1 and DA2 disposed under the stair-step stacked structure SWS. The first dopant region DA1 and the second dopant region DA2 may be doped with source dopants or well dopants. For example, each of the first and second dopant regions DA1 and DA2 may include a doped semiconductor layer doped with an n-type dopant or a doped semiconductor layer doped with a p-type dopant. The vertical channel VCH may include sidewalls directly contacting the second dopant region DA 2. The second dopant region DA2 may pass through the sides of the multi-layer memory layer extending along the outer walls of the vertical channel VCH. Thus, the multi-layered memory layer may be divided into the first multi-layered memory pattern ML1 and the second multi-layered memory pattern ML 2. Each of the first and second multi-layered memory patterns ML1 and ML2 may include the same material layers as the multi-layered memory layer described above with reference to fig. 2.
Referring to fig. 7A to 7C, the vertical channel VCH may include a semiconductor layer, and a core region of the vertical channel VCH may be filled with a core insulating layer CO. The core insulating layer CO may have a height lower than the vertical channel VCH. The doped semiconductor pattern CAP may be disposed on the core insulating layer CO. The doped semiconductor pattern CAP may function as a drain junction.
The barrier pattern BP may be formed on the sidewall of the step insulating layer SI. The barrier pattern BP and the step insulating layer SI may be covered by the planarization insulating pattern PD. The structure and material of each of the barrier pattern BP and the step insulating layer SI may be the same as those described above with reference to fig. 1A to 1D. The planarization insulating pattern PD and the step insulating layer SI may be penetrated by the support structure SP extending in the first direction I.
The etch stop layer ES and the upper insulating layer UI may be stacked on the planarization insulating pattern PD. The etch stop layer ES and the upper insulating layer UI may be penetrated by the contact plugs CT, SCT1, SCT2, and WCT.
The contact plugs CT, SCT1, WCT, and SCT2 may include a bit contact plug CT contacting the doped semiconductor pattern CAP, a first select contact plug SCT1 contacting the drain select line DSL, a second select contact plug SCT2 contacting the source select line SSL, and word contact plugs WCT contacting the word lines WL, respectively. The first and second select contact plugs SCT1 and SCT2 and the word contact plug WCT may further pass through the planarization insulating pattern PD and the stepped insulating layer SI.
The bit line BL and the connection wiring LL may be formed on the upper insulating layer UI. The bit line BL may be coupled to the bit contact plug CT, and the connection conductive line LL may be coupled to the first select contact plug SCT1, the second select contact plug SCT2, and the word contact plug WCT, respectively.
According to the structures shown in fig. 7A to 7C, the memory string MCR' may include memory cells coupled in series along the respective vertical channels VCH. Memory cells may be formed at the intersections of the respective vertical channels VCH and word lines WL. In addition, the memory string MCR' may include a drain select transistor coupled in series to the memory cell through a vertical channel VCH. Drain select transistors may be formed at intersections of the respective vertical channels VCH and the drain select lines DSL. In addition, memory string MCR' may include a source select transistor coupled in series to a memory cell through a vertical channel VCH or a lower channel LPC. The source select transistors may be formed at intersections of the respective vertical channels VCH and the source select lines SSL or intersections of the lower channels LPC and the source select lines SSL.
The three-dimensional semiconductor device shown in fig. 7A to 7C may be formed by the manufacturing process shown in fig. 4A to 4H or the manufacturing process shown in fig. 6A to 6F.
According to the present disclosure, when forming the contact plug, the contact plug may overlap the barrier pattern and be less likely to pass through the barrier pattern even when the alignment position of the contact plug is moved in the horizontal direction. In other words, according to the present disclosure, misalignment between the contact plug and the contact portion of the conductive pattern may be prevented by the barrier pattern. Thus, according to the present disclosure, since the barrier pattern may be used to prevent bridging between different conductive patterns, operational reliability of the semiconductor device may be improved.
Fig. 8 is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure.
Referring to fig. 8, a semiconductor device according to an embodiment of the present disclosure may include a substrate SUB, a peripheral circuit structure PC disposed on the substrate SUB, and memory blocks BLK1 through BLKn disposed on the peripheral circuit structure PC.
The substrate SUB may be a single crystal semiconductor layer. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a silicon germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth method. Each of the memory blocks BLK1 through BLKn may include a staircase cascade structure coupled to at least one of the memory strings shown in fig. 5 and 7A through 7C.
The peripheral circuit structure PC may include a row decoder, a column decoder, a page buffer, and a control circuit. The peripheral circuit structure PC may include NMOS and PMOS transistors, resistors, and capacitors electrically coupled to the memory blocks BLK1 through BLKn. The peripheral circuit structure PC may overlap the staircase lamination structure of the memory blocks BLK1 through BLKn.
Fig. 9 is a block diagram showing a configuration of a memory system 1100 according to an embodiment of the present disclosure.
Referring to fig. 9, a memory system 1100 according to an embodiment of the present disclosure may include a memory device 1120 and a memory controller 1110.
Memory device 1120 may be a multi-chip package formed from a plurality of flash memory chips.
The memory controller 1110 may be configured to control the memory device 1120, and includes a Static Random Access Memory (SRAM)1111, a CPU 1112, a host interface 1113, an Error Correction Code (ECC)1114, and a memory interface 1115. The SRAM 1111 can be used as an operation memory of the CPU 1112. The CPU 1112 may perform overall control operations for data exchange of the memory controller 1110. The host interface 1113 may include data exchange protocols for a host connected to the memory system 1100. In addition, ECC1114 can detect and correct errors included in data read from memory device 1120, and memory interface 1115 can perform interfacing with memory device 1120. In addition, the memory controller 1110 may further include a Read Only Memory (ROM) for storing code data for interfacing with a host.
The memory system 1100 described above may be a memory card or a Solid State Disk (SSD) equipped with a memory device 1120 and a memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with an external device (e.g., a host) via one of various interface protocols including Universal Serial Bus (USB), multi-media card (MMC), peripheral component interconnect express (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), and the like.
Fig. 10 is a block diagram illustrating a configuration of a computing system 1200 according to an embodiment of the present disclosure.
Referring to fig. 10, a computing system 1200 according to embodiments of the present disclosure may include a CPU 1220, a Random Access Memory (RAM)1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically coupled to a system bus 1260. In addition, when the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may be further included, and an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further included.
Memory system 1210 may include a memory device 1212 and a memory controller 1211.
The above embodiments are intended to help those of ordinary skill in the art to more clearly understand the present disclosure, and are not intended to limit the scope of the present disclosure. It should be understood that many variations and modifications of the basic concepts described herein will still fall within the spirit and scope of the disclosure as defined in the appended claims and their equivalents.
All terms (including technical terms or scientific terms) used herein have the meaning commonly understood by one of ordinary skill in the art to which this disclosure belongs, as long as they are not defined differently. Terms should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Cross Reference to Related Applications
The present application claims priority of korean patent application No. 10-2018-0085644, filed on the korean intellectual property office at 23/7/2018, the entire disclosure of which is incorporated herein by reference.
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