阅读说明：本技术 嵌入式非易失性存储器器件及其制造方法 (Embedded non-volatile memory device and method of manufacturing the same ) 是由 陈春 J·朴 金恩顺 姜仁国 姜成泽 张国栋 于 2018-07-13 设计创作，主要内容包括：系统和形成这样的系统的方法包括在第一区域中形成存储器栅极(MG)堆叠、在第二区域中的高k电介质上形成牺牲多晶硅栅极,其中,第一区域和第二区域被设置在单个衬底中。然后,可以在半导体衬底的第一区域中邻近MG堆叠形成选择栅极(SG)。牺牲多晶硅栅极可以用金属栅极代替,以在第二区域中形成逻辑场效应晶体管(FET)。第一区域和第二区域中的衬底表面基本共面。(Systems and methods of forming such systems include forming a Memory Gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. A Select Gate (SG) may then be formed in the first region of the semiconductor substrate adjacent to the MG stack. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic Field Effect Transistor (FET) in the second region. The substrate surfaces in the first and second regions are substantially coplanar.)

1. A method, comprising:

forming a Memory Gate (MG) stack in the first region;

forming a sacrificial polysilicon gate on the high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate;

forming a Select Gate (SG) stack adjacent to the MG stack in the first region of the semiconductor substrate,

replacing the sacrificial polysilicon gate with a metal gate to form a logic Field Effect Transistor (FET) in the second region; and

wherein the surface of the substrate in the first and second regions is substantially coplanar.

2. The method of claim 1, wherein forming the MG stack comprises:

forming a charge trapping layer in the first region of the semiconductor substrate;

forming an MG polysilicon layer on the charge trapping layer; and

at least the MG polysilicon layer is patterned to form a Memory Gate (MG).

3. The method of claim 2, wherein forming the SG stack comprises:

forming a gate oxide layer in the first region of the semiconductor substrate;

depositing an SG polycrystalline silicon layer on the grid oxide layer; and

at least patterning the SG polysilicon layer to form a Select Gate (SG) such that the SG stack is disposed adjacent the MG stack.

4. The method of claim 1, further comprising forming at least two dielectric layers between the MG stack and the SG stack.

5. The method of claim 1, further comprising forming a silicide on at least one of the MG or the SG.

6. The method of claim 3, wherein forming the SG further comprises:

planarizing the SG polysilicon layer, wherein the planarizing stops at a thin dielectric layer overlying the MG stack such that the MG stack and SG stack have substantially the same height.

7. The method of claim 6, wherein the thin dielectric layer has a thickness in the approximate range of 20 to 500 angstroms.

8. The method of claim 1, wherein a first surface of the first region and a second surface of the second region of the substrate are coplanar with each other within 200 angstroms.

9. The method of claim 1, wherein the first upper surface of the SG, the second upper surface of the MG, and the third upper surface of the logic FET are coplanar with one another within 300 angstroms.

10. The method of claim 1, prior to replacing the sacrificial polysilicon gate with the metal gate, further comprising:

forming a protective film in the first region covering at least the SG stack and the MG stack.

11. A method of manufacturing a semiconductor device, comprising:

forming a split gate memory cell in a first region of a substrate, further comprising:

depositing a Memory Gate (MG) polysilicon layer overlying the charge trapping layer,

patterning at least the MG polysilicon layer to form MGs,

depositing a Select Gate (SG) polysilicon layer overlying an SG oxide layer and the MGs,

planarizing the SG polysilicon layer such that top surfaces of the MG and SG polysilicon layers are substantially coplanar and parallel to a surface of the substrate, an

Removing portions of the SG oxide layer and the SG polysilicon layer in the first region to form SG adjacent to the MG; and

forming a logic Field Effect Transistor (FET) comprising a metal gate disposed on a high-K dielectric in a second region of the substrate, wherein the logic FET and the split-gate memory cell have substantially the same height.

12. The method of claim 11, further comprising:

depositing a thin dielectric layer overlying the MG polysilicon layer, wherein planarizing the SG polysilicon layer stops at the thin dielectric layer.

13. The method of claim 11, wherein removing portions of the SG polysilicon layer comprises:

removing a first portion of the SG polysilicon layer on one side of the MG; and

patterning a second portion of the SG polysilicon layer on the other side of the MG to form the SG.

14. The method of claim 13, wherein removing the first portion of the SG polysilicon layer comprises performing at least one of a wet etch or a dry etch.

15. The method of claim 11, further comprising forming at least two dielectric layers overlying at least two side surfaces of the MG prior to depositing the Select Gate (SG) polysilicon layer.

16. The method of claim 11, wherein the first upper surface of the SG, the second upper surface of the MG, and the third upper surface of the logic FET are coplanar with one another within 300 angstroms.

17. The method of claim 11, further comprising depositing a cap layer overlying the MG polysilicon layer, wherein depositing the cap layer further comprises depositing one or more of a dielectric film, an amorphous silicon film, or a polysilicon film.

18. A method of manufacturing a semiconductor device, comprising:

depositing a Memory Gate (MG) polysilicon layer overlying the charge trapping layer in a first region of the substrate;

patterning at least the MG polysilicon layer to form MGs,

depositing a Select Gate (SG) polysilicon layer overlying an SG oxide layer and the MGs in the first region,

planarizing the SG polysilicon layer such that top surfaces of the MG and SG polysilicon layers are substantially coplanar;

depositing a high-k dielectric layer on the substrate in the second region and depositing a sacrificial polysilicon gate layer overlying the high-k dielectric layer;

patterning the sacrificial polysilicon gate layer and the high-k dielectric layer;

removing a portion of the SG polycrystalline silicon layer to form SG adjacent to the MG;

depositing an interlayer dielectric (ILD) to encapsulate the MG, the SG, and the logic FET;

planarizing the ILD;

removing the sacrificial polysilicon gate layer; and

depositing a metal gate overlying the high-K dielectric layer to form a logic Field Effect Transistor (FET) in the second region.

19. The method of claim 18, further comprising:

depositing a cap layer overlying the MG polysilicon layer, wherein the cap layer comprises at least one layer of dielectric material, polysilicon, or a combination thereof.

20. The method of claim 18, further comprising:

forming an inter-gate dielectric layer covering at least two sidewalls of the MG, each inter-gate dielectric layer including at least two dielectric layers.

21. The method of claim 18, wherein planarizing the SG polysilicon layer comprises performing a Chemical Mechanical Planarization (CMP) process, a dry etch back process, or a combination thereof.

22. The method of claim 18, further comprising:

metal polishing is performed such that top surfaces of the MG, the SG, and the logic FET are substantially coplanar.

23. The method of claim 18, wherein depositing the MG polysilicon layer comprises performing one of:

depositing a doped polysilicon layer, or

An undoped polysilicon layer is deposited and subsequently doped.

24. The method of claim 18, wherein depositing the SG polysilicon layer comprises performing one of:

depositing a doped polysilicon layer, or

An undoped polysilicon layer is deposited and subsequently doped.

25. The method of claim 18, further comprising, prior to removing the sacrificial polysilicon gate layer:

forming a protective film covering at least the MG and the SG.