Method for manufacturing memory device and memory device
阅读说明：本技术 存储器件的制造方法及该存储器件 (Method for manufacturing memory device and memory device ) 是由 张金霜 邹荣 王奇伟 陈昊瑜 于 2019-10-17 设计创作，主要内容包括：本申请公开了一种存储器件的制造方法及该存储器件,包括：提供一衬底,该衬底包括存储单元区域和外围电路区域；对存储单元区域的有源区进行离子注入；在衬底上沉积隔离层,隔离层的最内层包括氧化硅层,隔离层的最外层包括氮化硅层；对隔离层进行刻蚀,直至衬底平面上的氧化硅层暴露在外；对外围电路区域的源端进行离子注入；在衬底沉积氧化硅层,使衬底上的图形被氧化硅层覆盖；去除存储单元区域的氧化硅层；通过湿刻蚀工艺去除存储单元区域最外层的氮化硅层；对存储区域的漏端进行离子注入。本申请能够在对栅极的侧墙进行减薄的同时不对外围电路的侧墙进行减薄,进而在保证ILD填充良率的基础上,满足外围电路的侧墙厚度以提高击穿电压窗口。(The application discloses a manufacturing method of a memory device and the memory device, comprising: providing a substrate, wherein the substrate comprises a memory cell area and a peripheral circuit area; performing ion implantation on an active region of the memory cell region; depositing an isolation layer on a substrate, wherein the innermost layer of the isolation layer comprises a silicon oxide layer, and the outermost layer of the isolation layer comprises a silicon nitride layer; etching the isolation layer until the silicon oxide layer on the substrate plane is exposed; performing ion implantation on the source end of the peripheral circuit area; depositing a silicon oxide layer on the substrate to enable the pattern on the substrate to be covered by the silicon oxide layer; removing the silicon oxide layer in the memory cell region; removing the silicon nitride layer on the outermost layer of the storage unit region through a wet etching process; and carrying out ion implantation on the drain end of the storage region. According to the method and the device, the side wall of the peripheral circuit is not thinned while the side wall of the grid electrode is thinned, and then on the basis of ensuring the ILD filling yield, the thickness of the side wall of the peripheral circuit is met so as to improve the breakdown voltage window.)
1. A method of manufacturing a memory device, comprising:
providing a substrate, wherein the substrate comprises a memory cell region and a peripheral circuit region, a grid is formed in the memory cell region, the grid sequentially comprises a floating gate, a control oxidation layer and a control gate from bottom to top, and the peripheral circuit region is provided with a control gate;
performing ion implantation on an active region of the memory cell region;
depositing an isolation layer on the substrate, wherein the outermost layer of the isolation layer comprises a silicon nitride layer;
etching the isolation layer until the silicon oxide layer on the substrate plane is exposed;
performing ion implantation on the source end and the drain end of the peripheral circuit region;
depositing a silicon oxide layer on the substrate, so that the pattern on the substrate is covered by the silicon oxide layer;
removing the silicon oxide layer of the memory cell region;
removing the silicon nitride layer on the outermost layer of the storage unit region through a wet etching process;
and carrying out ion implantation on the drain end of the storage region.
2. The method of claim 1, wherein the isolation layer comprises a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer in sequence from inside to outside.
3. The method of claim 2, wherein the removing the silicon nitride layer of the memory cell region by a wet etching process comprises:
and removing the silicon nitride layer of the memory cell region by a phosphoric acid wet etching process.
4. The method of claim 1, wherein depositing a silicon oxide layer on the substrate comprises:
and depositing a silicon oxide layer with the thickness of more than 30 angstroms on the substrate.
5. The method of claim 4, wherein the silicon oxide layer deposited on the substrate has a thickness of less than 200 angstroms.
6. The method of claim 1, wherein the removing the silicon nitride layer at the outermost layer of the memory cell region by a wet etching process comprises:
and masking the peripheral circuit region by a memory cell VT mask plate, and removing the silicon nitride layer of the memory cell region by a wet etching process.
7. The method according to any of claims 1 to 6, further comprising, after the ion implantation into the drain of the storage region:
depositing a complex barrier layer on the substrate;
removing the drain end of the memory cell region and the complex barrier layer on the control gate;
depositing a metal layer on the substrate;
carrying out primary annealing treatment on the substrate to enable the metal layer to react with silicon of the substrate to generate a complex layer;
removing the part of the metal layer which is not reacted with silicon;
and carrying out secondary annealing treatment on the substrate.
8. The method of claim 7, wherein said removing the drain terminal of the memory cell region and the complex barrier layer on the control gate comprises:
and removing the drain end of the memory cell region and the complex barrier layer on the control gate by a dry etching process and a wet etching process.
9. The method of claim 7, wherein said annealing said substrate comprises:
and carrying out primary annealing treatment on the substrate through a rapid annealing process.
10. A memory device, comprising:
a substrate on which a silicon oxide layer is formed;
the grid is formed in the memory cell area of the substrate and sequentially comprises a floating gate, a control oxidation layer and a control gate from bottom to top, a first side wall is formed on the peripheral side of the grid, and the outermost layer of the first side wall comprises a silicon oxide layer;
the control gate is formed in a peripheral circuit region of the substrate, a second side wall is formed on the peripheral side of the control gate, and the outermost layer of the second side wall comprises a silicon nitride layer;
and a complex layer is formed on the top layer of the grid electrode, the drain terminal positioned on one side of the grid electrode, the top layer of the control grid of the peripheral circuit and the source terminal drain terminal of the peripheral circuit.
11. The memory device of claim 10, wherein the first sidewall comprises a silicon oxide layer, a silicon nitride layer 302, and a silicon oxide layer in sequence from inside to outside.
12. The memory device of claim 10 or 11, wherein the second sidewall comprises a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer in sequence from inside to outside.
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a storage device and the storage device.
Background
Market share of non-volatile memory (NVM) devices is increasing, and NVM devices are generally classified into two types: stacked gate memory devices and split gate memory devices.
In order to meet market demands of high density, high performance and low cost, technical nodes are made smaller and smaller, and the size of a corresponding drain is reduced to be lower than 50 nanometers, so that requirements on a side wall process and an Inter Layer Dielectric (ILD) filling process are higher and higher.
In the process step of forming the side wall of the NOR type split-gate memory device below the 65 nanometer node, as the size of the drain end is reduced, only a small gap is left in the middle after the side wall is etched, the subsequent ILD is not well filled, and a hole (Void) is generated to cause a serious yield problem; if the side wall is excessively thinned, the problem of ILD filling in the memory unit region can be solved, but the problem of insufficient breakdown voltage window caused by the thinner side wall of the peripheral circuit can be solved.
Taking an Erasable Programmable Read only memory (ETOX) structure as an example, referring to fig. 1, a top view of the ETOX structure of a nonvolatile memory device is shown, which includes Word Lines (WL) 110 and Bit lines (Bit lines, BL)120 perpendicular to each other, and a Control gate (Control Grid) 130 on one side of the
Fig. 2 is a cross-sectional view of the memory device of the ETOX structure along line AA' in fig. 1, and as shown in fig. 2, one side of a Gate formed by a Floating Gate (FG) 150, a
Fig. 3 to 12 are flow charts of manufacturing of a memory device provided in the related art. Wherein, fig. 3, fig. 5, fig. 7, fig. 9, fig. 11 are cross-sectional views of a memory cell region of the memory device along a line AA' in fig. 1; fig. 4, 6, 8, 10, and 12 are cross-sectional views of a peripheral circuit region of the memory device.
In the steps shown in fig. 3 and 4, the steps of photolithography of the active region, etching of the active region, and ion implantation of the active region are sequentially performed on the substrate; in the steps shown in fig. 5 and 6, an isolation layer is deposited simultaneously on the memory cell region and the peripheral circuit; in the steps shown in fig. 7 and 8, the isolation layers on the memory cell region and the peripheral circuit are simultaneously etched to form a side wall; in the steps shown in fig. 9 and 10, an oxide layer is grown on the sidewall, and the oxide layer is etched; in the steps shown in fig. 11 and 12, the source terminal and the drain terminal of the peripheral circuit are sequentially subjected to photolithography, and the source terminal of the peripheral circuit is subjected to ion implantation.
It can be seen that since the formation and etching of the side walls of the memory cell region and the peripheral circuit are performed simultaneously, the thinning of the side walls can lead to the thinning of the side walls of the peripheral circuit, thereby causing the potential hazard of voltage breakdown. In view of the above, it is desirable to provide a sidewall formation process for a memory device with a 65 nm node or less, which satisfies the sidewall thickness of the peripheral circuit to improve the breakdown voltage window on the basis of ensuring the ILD filling yield of the memory cell region.
Disclosure of Invention
The application provides a manufacturing method of a memory device and the memory device, which can solve the problem of poor ILD filling caused by narrow drain ends of a memory cell region in the manufacturing method of the memory device provided in the related art.
In one aspect, an embodiment of the present application provides a method for manufacturing a memory device, including:
providing a substrate, wherein the substrate comprises a memory cell area and a peripheral circuit area, a grid is formed in the memory cell area, the grid sequentially comprises a floating gate, a control oxidation layer and a control gate from bottom to top, and the peripheral circuit area is provided with a control gate;
performing ion implantation on an active region of the memory cell region;
depositing an isolation layer on the substrate, wherein the outermost layer of the isolation layer comprises a silicon nitride layer;
etching the isolation layer until the silicon oxide layer on the substrate plane is exposed;
performing ion implantation on the source end and the drain end of the peripheral circuit region;
depositing a silicon oxide layer on the substrate, so that the pattern on the substrate is covered by the silicon oxide layer;
removing the silicon oxide layer of the memory cell region;
removing the silicon nitride layer on the outermost layer of the storage unit region through a wet etching process;
and carrying out ion implantation on the drain end of the storage region.
Optionally, the isolation layer sequentially includes a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer from inside to outside.
Optionally, the removing the silicon nitride layer in the memory cell region by a wet etching process includes:
and removing the silicon nitride layer of the memory cell region by a phosphoric acid wet etching process.
Optionally, the depositing a silicon oxide layer on the substrate includes:
and depositing a silicon oxide layer with the thickness of more than 30 angstroms on the substrate.
Optionally, the silicon oxide layer deposited on the substrate has a thickness of less than 200 angstroms.
Optionally, the removing the silicon nitride layer on the outermost layer of the memory cell region by using a wet etching process includes:
and masking the peripheral circuit region by a memory cell VT mask plate, and removing the silicon nitride layer of the memory cell region by a wet etching process.
Optionally, after the ion implantation is performed on the drain end of the storage region, the method further includes:
depositing a complex barrier layer on the substrate;
removing the drain end of the memory cell region and the complex barrier layer on the control gate;
depositing a metal layer on the substrate;
carrying out primary annealing treatment on the substrate to enable the metal layer to react with silicon of the substrate to generate a complex layer;
removing the part of the metal layer which is not reacted with silicon;
and carrying out secondary annealing treatment on the substrate.
Optionally, the removing the drain end of the memory cell region and the complex blocking layer on the control gate includes:
and removing the drain end of the memory cell region and the complex barrier layer on the control gate by a dry etching process and a wet etching process.
Optionally, the performing of the annealing treatment on the substrate for one time includes:
and carrying out primary annealing treatment on the substrate through a rapid annealing process.
In another aspect, the present application provides a memory device comprising:
a substrate on which a silicon oxide layer is formed;
the grid is formed in the memory cell area of the substrate and sequentially comprises a floating gate, a control oxidation layer and a control gate from bottom to top, a first side wall is formed on the peripheral side of the grid, and the outermost layer of the first side wall comprises a silicon oxide layer;
the control gate is formed in a peripheral circuit region of the substrate, a second side wall is formed on the peripheral side of the control gate, and the outermost layer of the second side wall comprises a silicon nitride layer;
and a complex layer is formed on the top layer of the grid electrode, the drain terminal positioned on one side of the grid electrode, the top layer of the control grid of the peripheral circuit and the source terminal drain terminal of the peripheral circuit.
Optionally, the first sidewall sequentially includes a silicon oxide layer, a
Optionally, the second sidewall sequentially includes a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer from inside to outside.
The technical scheme at least comprises the following advantages:
after ion implantation is carried out on an active area of a storage unit area, an isolation layer comprising the outermost layer of silicon nitride is deposited on a substrate, the isolation layer is etched to the innermost silicon oxide layer in the vertical direction, ion implantation is carried out on a source end of a peripheral circuit area, the silicon oxide layer of the storage unit area is removed after the silicon oxide layer is deposited on the substrate, the outermost silicon nitride layer of the storage unit area is removed through a wet etching process, and the outermost silicon oxide layer of the peripheral circuit area is deposited, so that the outermost silicon oxide layer cannot be removed in the wet etching step, so that the side wall of a grid electrode is thinned while the side wall of the peripheral circuit is not thinned, and further on the basis of ensuring the ILD (inter-layer dielectric) filling yield of the storage unit area, the thickness of the side wall of the peripheral circuit is met to improve a breakdown.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a top view of a memory device of an ETOX structure;
FIG. 2 is a cross-sectional view of a memory device of the ETOX structure taken along line AA' of FIG. 1;
fig. 3 to 12 are flow charts of manufacturing of memory devices provided in the related art;
FIG. 13 is a flow chart of a method of fabricating a memory device provided by an exemplary embodiment of the present application;
fig. 14 to 31 are flow charts of manufacturing a memory device according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be configured in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
FIG. 13 is a flow chart of a method of fabricating a memory device provided by an exemplary embodiment of the present application; fig. 14 to 31 are flow charts of manufacturing a memory device according to an exemplary embodiment of the present application, in which fig. 14, 16, 18, 20, 22, 24, 26, 28, and 30 are cross-sectional views of a memory cell region of the memory device along a line AA' in fig. 1; fig. 15, 17, 19, 21, 23, 25, 27, 29, and 31 are cross-sectional views of a peripheral circuit region of a memory device.
Referring to fig. 13, the method for manufacturing a memory device according to the present embodiment includes:
Illustratively, referring to fig. 14, a floating
At
Illustratively, referring to fig. 14 and 15, the
Illustratively, referring to fig. 16 and 17, the isolation layer includes a
At
Illustratively, referring to fig. 18 and 19, the isolation layer may be etched by a dry etch process, the etching step remaining to the
Illustratively, referring to fig. 20 and 21, in this step, the other regions of the
This silicon oxide layer is also referred to as a protective silicon oxide layer. Illustratively, referring to fig. 22 and 23, in this step, a
For example, referring to fig. 24 and 25, the peripheral circuit region may be covered with a
Illustratively, referring to FIGS. 26 and 27, the reaction can be carried out by phosphoric acid (P)3O4) Nitridation of memory cell region by wet etching
Illustratively, referring to fig. 29 and 30, the
In summary, in the embodiment, after the ion implantation is performed on the active region of the memory cell region, the isolation layer including the outermost layer of silicon nitride is deposited on the substrate, the isolation layer is etched to the innermost layer of the silicon oxide layer in the vertical direction, the ion implantation is performed on the source end of the peripheral circuit region, the silicon oxide layer of the memory cell region is removed after the silicon oxide layer is deposited on the substrate, the outermost layer of the silicon nitride layer of the memory cell region is removed through a wet etching process, and the outermost layer of the peripheral circuit is deposited with the silicon oxide layer, so that the outermost layer of the peripheral circuit cannot be removed in the wet etching step, so that the sidewall of the peripheral circuit is not thinned while the sidewall of the gate is thinned, and further, on the basis of ensuring the ILD filling yield of the memory cell region, the sidewall thickness of the peripheral circuit is satisfied to improve the breakdown.
Optionally, in the above embodiment, after
at step 1310, a complex barrier layer is deposited on the substrate.
Optionally, the complex barrier layer comprises a silicon oxide layer.
Step 1311, remove the drain of the memory cell region and the complex barrier layer on the control gate.
Illustratively, the drain end of the memory cell region and the complex barrier layer on the control gate of the peripheral circuit can be removed by a dry etching process and a wet etching process.
Step 1312 deposits a metal layer on the substrate.
Step 1313, annealing the substrate for the first time to react the metal layer with silicon of the substrate to form a complex layer.
Optionally, the substrate may be subjected to a first annealing treatment by a rapid annealing process, so that a part of metal elements in the metal layer reacts with silicon of the substrate to generate a complex layer.
At step 1314, the portions of the metal layer that have not reacted with silicon are removed.
Illustratively, the portions of the metal layer that do not react with silicon may be removed by a dry etching process, and/or a wet etching process, leaving the complex layer.
Step 1315, perform a secondary annealing process on the substrate.
Illustratively, referring to fig. 30 and 31, after the second annealing process, a
Embodiments of the present application also provide a memory device, which may be manufactured by the above manufacturing method, with reference to fig. 30 and 31, and includes:
a
Optionally, the first sidewall sequentially includes a
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious changes and modifications may be made without departing from the spirit and scope of the invention.
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