阅读说明：本技术 三维存储器及其制作方法 (Three-dimensional memory and manufacturing method thereof ) 是由 赵治国 霍宗亮 李春龙 于 2019-11-06 设计创作，主要内容包括：本发明公开了一种三维存储器及其制作方法,所述制作方法包括：提供一半导体衬底,所述半导体衬底形成有堆叠结构；在所述堆叠结构上形成沟道孔,所述沟道孔露出所述半导体衬底；在所述沟道孔内形成沟道孔结构,所述沟道孔结构具有第一沟道层；去除所述第一沟道层,形成间隙；在所述间隙内形成第二沟道层,所述第二沟道层的电子迁移率大于所述第一沟道层的电子迁移率。可见,应用本发明提供的技术方案,可以提高三维存储器中沟道层的电子迁移率,获得更加良好的电学特性。(The invention discloses a three-dimensional memory and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a stacked structure; forming a channel hole on the stacked structure, the channel hole exposing the semiconductor substrate; forming a channel hole structure within the channel hole, the channel hole structure having a first channel layer; removing the first channel layer to form a gap; and forming a second channel layer in the gap, wherein the electron mobility of the second channel layer is larger than that of the first channel layer. Therefore, by applying the technical scheme provided by the invention, the electron mobility of the channel layer in the three-dimensional memory can be improved, and better electrical characteristics can be obtained.)

1. A method for manufacturing a three-dimensional memory, the method comprising:

providing a semiconductor substrate, wherein the semiconductor substrate is provided with a stacked structure;

forming a channel hole on the stacked structure, the channel hole exposing the semiconductor substrate;

forming a channel hole structure within the channel hole, the channel hole structure having a first channel layer;

removing the first channel layer to form a gap;

and forming a second channel layer in the gap, wherein the electron mobility of the second channel layer is larger than that of the first channel layer.

2. The method of manufacturing of claim 1, wherein said providing a semiconductor substrate comprises:

and depositing a film on the semiconductor substrate to form a stacked structure, wherein the stacked structure comprises a plurality of layers of insulating dielectric layers and sacrificial layers which are alternately stacked.

3. The method of claim 2, wherein the insulating dielectric layer is silicon oxide and the sacrificial layer is silicon nitride.

4. The method of manufacturing according to claim 1, wherein the forming a trench hole on the stacked structure comprises:

forming a hard mask layer on the upper surface of the stacking structure, and forming a graphical photoresist layer on the surface of the hard mask layer;

forming a patterned hard mask layer based on the patterned photoresist layer;

and forming a channel hole penetrating through the stacking structure according to the patterned hard mask layer.

5. The method according to claim 1, wherein a hard mask layer covers a surface of the stacked structure; the forming a trench hole structure in the trench hole includes:

forming an epitaxial layer at the bottom of the channel hole;

forming a charge storage function layer on the upper surface of the hard mask layer, the side wall of the channel hole and the surface of the epitaxial layer;

removing part of the functional layer on the surface of the epitaxial layer to expose the epitaxial layer;

forming the first channel layer from the functional layer surface to the bottom of the channel hole;

filling an insulating medium in the trench hole;

and removing the functional layer, the first channel layer and the insulating medium above the hard mask layer.

6. The method of manufacturing according to claim 5, further comprising, after forming the second channel layer:

removing the insulating medium on the top of the channel hole to form a groove;

and filling a conductive medium in the groove to form a plug.

7. The manufacturing method according to claim 5, wherein the method for forming the functional layer includes:

forming a gate oxide layer on the upper surface of the hard mask layer, the side wall of the channel hole and the surface of the epitaxial layer;

forming a charge storage layer on the surface of the gate oxide layer;

and forming a tunnel layer on the surface of the charge storage layer.

8. The method of manufacturing according to claim 1, wherein the first channel layer is polysilicon and the second channel layer is single crystal silicon.

9. A three-dimensional memory, the three-dimensional memory comprising:

a semiconductor substrate formed with a stacked structure;

a channel hole penetrating through the stacked structure, the channel hole exposing the semiconductor substrate;

a channel hole structure located within the channel hole, the channel hole structure having a second channel layer;

the second channel layer is filled in a gap formed after the first channel layer is removed; the second channel layer has an electron mobility greater than that of the first channel layer.

10. The three-dimensional memory according to claim 9, wherein the first channel layer is polysilicon and the second channel layer is single crystal silicon.