阅读说明：本技术 层叠陶瓷电容器 (Multilayer ceramic capacitor ) 是由 池田充 于 2021-04-20 设计创作，主要内容包括：提供一种作为电极整体能降低电阻值的层叠陶瓷电容器。本发明的层叠陶瓷电容器具备层叠体和两个外部电极,层叠体具备：层叠体主体,具有交替地层叠了电介质层和内部电极层的内层部及配置在内层部中的层叠方向上的两侧的外层部；侧方间隔部,配置在层叠体主体中的宽度方向上的两侧；主面,设置在层叠方向上的两侧；侧面,设置在宽度方向上的两侧；及端面,设置在长度方向上的两侧,两个外部电极配置在两个端面的外侧,含基底电极层及导电性树脂层,基底电极层包含导电性金属及玻璃成分,并与层叠体相接,导电性树脂层包含热固化性树脂及金属成分,并与基底电极层相接,内部电极层的与基底电极层相接的端部区域的厚度比端部区域以外的区域的厚度厚。(Provided is a laminated ceramic capacitor capable of reducing the resistance value as an electrode as a whole. The multilayer ceramic capacitor of the present invention includes a multilayer body and two external electrodes, the multilayer body including: a laminate body having an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, and an outer layer portion disposed on both sides of the inner layer portion in a lamination direction; side partition parts arranged on both sides in the width direction of the laminate body; main surfaces provided on both sides in the stacking direction; side surfaces arranged on both sides in the width direction; and end faces provided on both sides in the longitudinal direction, the two external electrodes being disposed outside the two end faces, the end faces including an underlying electrode layer and a conductive resin layer, the underlying electrode layer including a conductive metal and a glass component and being in contact with the laminate, the conductive resin layer including a thermosetting resin and a metal component and being in contact with the underlying electrode layer, the end region of the internal electrode layer in contact with the underlying electrode layer having a thickness greater than a thickness of a region other than the end region.)

1. A laminated ceramic capacitor includes a laminated body and two external electrodes,

the laminate is provided with:

a laminate body having an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately laminated, and two outer layer portions respectively arranged on both sides of the inner layer portion in a lamination direction;

two side spacers arranged on both sides in a width direction intersecting the stacking direction in the stacked body main body;

two main surfaces provided on both sides in the stacking direction, respectively;

two side surfaces respectively provided on both sides in a width direction intersecting the stacking direction; and

two end faces respectively provided on both sides in a longitudinal direction intersecting the stacking direction and the width direction,

the two external electrodes are respectively arranged outside the two end faces in the laminated body, and each of the two external electrodes includes a base electrode layer and a conductive resin layer, the base electrode layer includes a conductive metal and a glass component and is in contact with the laminated body, the conductive resin layer includes a thermosetting resin and a metal component and is in contact with the base electrode layer,

the thickness of an end region of the internal electrode layers in contact with the base electrode layer is greater than the thickness of a region of the internal electrode layers other than the end region.

2. The laminated ceramic capacitor of claim 1,

an interface exists between the laminate body and the side spacer.

3. The laminated ceramic capacitor according to claim 1 or 2,

magnesium segregates to a portion of the side partition portion that is in contact with the internal electrode layer.

4. The laminated ceramic capacitor according to any one of claims 1 to 3,

the side partition portion includes:

an inner side spacer layer that is in contact with the laminate body; and

and an outer side spacer layer in contact with the inner side spacer layer.

5. The laminated ceramic capacitor according to any one of claims 1 to 4,

a line connecting end portions on the side surfaces of the two internal electrode layers adjacent to each other in the stacking direction is convex outward in the WT cross section,

wherein the WT cross section is a cross section in the width direction and the stacking direction passing through the center of the stacked body.

Technical Field

The present invention relates to a laminated ceramic capacitor.

Background

In recent years, a large-capacity and small-sized multilayer ceramic capacitor has been demanded. Such a multilayer ceramic capacitor has an inner layer portion in which dielectric layers that are a strong dielectric material having a relatively high dielectric constant and internal electrodes are alternately stacked. Dielectric layers as outer layer portions are disposed on upper and lower portions of the alternately stacked inner layer portions to form a rectangular parallelepiped laminate body. Side gap portions (side gap portions) are formed on both side surfaces in the width direction of the rectangular parallelepiped laminate body, and external electrodes are formed on both end surfaces in the longitudinal direction.

Conventionally, a multilayer ceramic capacitor in which an external electrode includes a conductive resin in order to relieve stress is known as such a multilayer ceramic capacitor (see patent document 1).

Prior art documents

Patent document

Patent document 1: japanese patent laid-open publication No. 2013 and 73952

However, although the conductive resin has conductivity, the resistance value is large compared to metal. If the resistance value is large, the capacitance of the multilayer ceramic capacitor may not match the design, for example.

Disclosure of Invention

Problems to be solved by the invention

The present invention aims to provide a multilayer ceramic capacitor capable of reducing the resistance value of the whole electrode.

Means for solving the problems

In order to solve the above problem, the present invention provides a multilayer ceramic capacitor including a laminate and two external electrodes, the laminate including: a laminate body having an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately laminated, and two outer layer portions respectively arranged on both sides of the inner layer portion in a lamination direction; two side spacers arranged on both sides in a width direction intersecting the stacking direction in the stacked body main body; two main surfaces provided on both sides in the stacking direction, respectively; two side surfaces respectively provided on both sides in a width direction intersecting the stacking direction; and two end faces provided on both sides in a longitudinal direction intersecting the stacking direction and the width direction, wherein the two external electrodes are disposed outside the two end faces in the laminate, respectively, and each of the two external electrodes includes a base electrode layer and a conductive resin layer, the base electrode layer includes a conductive metal and a glass component and is in contact with the laminate, the conductive resin layer includes a thermosetting resin and a metal component and is in contact with the base electrode layer, and a thickness of an end region in the internal electrode layer in contact with the base electrode layer is larger than a thickness of a region in the internal electrode layer other than the end region.

Effects of the invention

According to the present invention, a multilayer ceramic capacitor in which the resistance value of the entire electrode can be reduced can be provided.

Drawings

Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor according to an embodiment.

Fig. 2 is a sectional view of the laminated ceramic capacitor of fig. 1 taken along line II-II.

Fig. 3 is a cross-sectional view of the laminated ceramic capacitor of fig. 1 taken along the line III-III.

Fig. 4 is a schematic perspective view of the laminate.

Fig. 5 is a schematic perspective view of the laminate main body.

Fig. 6 is a flowchart illustrating a method of manufacturing a laminated ceramic capacitor.

Fig. 7 is a schematic plan view of a raw material sheet.

Fig. 8 is a schematic view showing a state in which raw material sheets are stacked.

Fig. 9 is a schematic perspective view of the mother block.

Description of the reference numerals

1: a laminated ceramic capacitor;

2: a laminate;

3: an external electrode;

3 a: 1 st external electrode;

3 b: a 2 nd external electrode;

10: a laminate body;

11: an inner layer portion;

12: an upper outer layer portion;

13: a lower outer layer part;

14: a dielectric layer;

15: an internal electrode layer;

15 a: 1 st internal electrode layer;

15 b: 2 nd internal electrode layer;

30: a lateral spacer portion;

30 a: the 1 st side spacer;

30 b: a 2 nd lateral spacing part;

31: a base electrode layer;

32: a conductive resin layer;

33: plating a coating layer;

151: a lead-out section;

152: an opposite part;

153: an end region.

Detailed Description

The multilayer ceramic capacitor 1 according to the embodiment of the present invention will be described below. Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment. Fig. 2 is a sectional view of the laminated ceramic capacitor 1 of fig. 1 taken along line II-II. Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 of fig. 1 taken along the line III-III.

The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape, and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The laminate 2 includes an inner layer portion 11, and the inner layer portion 11 includes a plurality of sets of dielectric layers 14 and internal electrode layers 15.

In the following description, as a term indicating the orientation of the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1 is referred to as the longitudinal direction L. The direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked is referred to as a stacking direction T. A direction intersecting both the longitudinal direction L and the stacking direction T is defined as a width direction W. In the embodiment, the width direction is orthogonal to both the longitudinal direction L and the stacking direction T.

Fig. 4 is a schematic perspective view of the laminate 2. The laminate 2 includes a laminate main body 10 and a side spacer 30. Fig. 5 is a schematic perspective view of the laminate body 10.

In the following description, of the six outer surfaces of the laminate 2 shown in fig. 4, a pair of outer surfaces facing each other in the lamination direction T is defined as a 1 st main surface Aa and a 2 nd main surface Ab, a pair of outer surfaces facing each other in the width direction W is defined as a 1 st side surface Ba and a 2 nd side surface Bb, and a pair of outer surfaces facing each other in the longitudinal direction L is defined as a 1 st end surface Ca and a 2 nd end surface Cb.

In addition, when it is not necessary to particularly distinguish between the 1 st main surface Aa and the 2 nd main surface Ab, the description will be given collectively as the main surface a, when it is not necessary to particularly distinguish between the 1 st side surface Ba and the 2 nd side surface Bb, the description will be given collectively as the side surface B, and when it is not necessary to particularly distinguish between the 1 st end surface Ca and the 2 nd end surface Cb, the description will be given collectively as the end surface C.

The laminate 2 is preferably rounded at the corner R1 and the edge line R2. The corner R1 is a portion where the main surface a, the side surface B, and the end surface C intersect. The ridge line portion R2 is a portion where the main surface a and the side surface B, the main surface a and the end surface C, or the side surface B and the end surface C intersect each other, which is two surfaces of the laminate 2.

In addition, the laminate 2 may have irregularities or the like formed on a part or all of the main surface a, the side surface B, and the end surface C. The dimension of the laminate 2 is not particularly limited, but it is preferable that the dimension in the longitudinal direction L is 0.2mm to 10mm, the dimension in the width direction W is 0.1mm to 10mm, and the dimension in the lamination direction T is 0.1mm to 5 mm.

As shown in fig. 5, the laminate body 10 includes an inner layer 11, an upper outer layer 12 disposed on the 1 st main surface Aa side of the inner layer 11, and a lower outer layer 13 disposed on the 2 nd main surface Ab side of the inner layer 11.

The inner layer portion 11 includes a plurality of sets of dielectric layers 14 and internal electrode layers 15 alternately stacked along the stacking direction T.

The thickness of the dielectric layer 14 is 0.5 μm or less. The dielectric layer 14 is made of a ceramic material. As the ceramic material, BaTiO, for example, can be used₃A dielectric ceramic as a main component. As the ceramic material, a ceramic material in which at least one of the subcomponents such as Mn compound, Fe compound, Cr compound, Co compound, Ni compound, and the like is added to the main component may be used. In addition, the dielectric layers 1 constituting the laminate body 10The number of the sheets of 4 is preferably 15 or more and 700 or less inclusive of the upper outer layer portion 12 and the lower outer layer portion 13.

The internal electrode layers 15 include a plurality of 1 st internal electrode layers 15a and a plurality of 2 nd internal electrode layers 15 b. The 1 st internal electrode layer 15a and the 2 nd internal electrode layer 15b are alternately arranged. In addition, when it is not necessary to particularly distinguish between the 1 st internal electrode layer 15a and the 2 nd internal electrode layer 15b, the description will be given collectively as the internal electrode layers 15.

The 1 st internal electrode layer 15a includes a 1 st opposing portion 152a opposing the 2 nd internal electrode layer 15b, a 1 st lead-out portion 151a led out from the 1 st opposing portion 152a to the 1 st end face Ca side, and a 1 st end portion region 153a located at an end portion of the 1 st lead-out portion 151a on the 1 st end face Ca side. The 1 st end region 153a is exposed at the 1 st end face Ca and electrically connected to a 1 st external electrode 3a described later.

In the 1 st internal electrode layer 15a, the thickness of the 1 st end region 153a in the stacking direction T is made thicker than the thickness of the 1 st opposing portion 152a in the stacking direction T and the thickness of the 1 st lead portion 151a in the stacking direction T.

The 2 nd internal electrode layer 15b includes a 2 nd opposing portion 152b opposing the 1 st internal electrode layer 15a, a 2 nd lead portion 151b led out from the 2 nd opposing portion 152b to the 2 nd end face Cb, and a 2 nd end portion region 153b located at an end portion of the 2 nd lead portion 151b on the 2 nd end face Cb side.

The 2 nd end region 153b is electrically connected to the 2 nd external electrode 3b described later. In the 2 nd internal electrode layer 15b, the thickness of the 2 nd end region 153b in the stacking direction T is made thicker than the thickness of the 2 nd opposing portion 152b in the stacking direction T and the thickness of the 2 nd lead portion 151b in the stacking direction T.

Further, according to the internal electrode layers 15 described above, electric charges are accumulated in the 1 st opposing portion 152a of the 1 st internal electrode layer 15a and the 2 nd opposing portion 152b of the 2 nd internal electrode layer 15b, and the characteristics of the capacitor are exhibited.

In addition, when it is not necessary to particularly distinguish between the 1 st and 2 nd facing portions 152a and 152b, the description will be given collectively as the facing portion 152. Note that, when it is not necessary to particularly distinguish between the 1 st drawn part 151a and the 2 nd drawn part 151b, the description will be given collectively as the drawn part 151. When it is not necessary to distinguish between the 1 st end region 153a and the 2 nd end region 153b, the description will be given collectively as the end region 153.

As shown in fig. 3, in the WT cross section, which is a cross section passing through the center of the laminate 2 in the width direction W and the lamination direction T, the position deviation d in the lamination direction T of the end portions in the width direction W of the two 1 st and 2 nd internal electrode layers 15a and 15b adjacent to each other in the up-down direction T is within 0.5 μm. That is, the 1 st internal electrode layer 15a and the 2 nd internal electrode layer 15b adjacent to each other vertically in the stacking direction T have end portions in the width direction W at substantially the same positions in the width direction W, and the positions of the end portions are aligned in the stacking direction T.

On the other hand, similarly, in the WT cross section shown in fig. 3, which is a cross section in the width direction W and the stacking direction T passing through the center of the stacked body 2, a line m indicated by a dotted line in the drawing connecting all the ends in the width direction W of the 1 st internal electrode layer 15a and the 2 nd internal electrode layer 15b adjacent in the stacking direction T is slightly convex outward. In other words, the internal electrode layers 15 in the central portion in the stacking direction T of the 1 st internal electrode layer 15a and the 2 nd internal electrode layer 15b are pressed and elongated. The convex shape may be referred to as a drum shape.

That is, the end portions of the 1 st internal electrode layer 15a and the 2 nd internal electrode layer 15b in the width direction W are located at substantially the same position in the width direction W when two vertically adjacent ones in the stacking direction T are viewed, but are slightly convex outward when viewed as a whole in the stacking direction T. The reason why the convex shape is formed in this manner will be described later.

The internal electrode layers 15 are preferably formed of a metal material typified by Ni, Cu, Ag, Pd, an Ag — Pd alloy, Au, or the like. In the region other than the end region 153, that is, in the lead portion 151 and the counter portion 152, the thickness of the internal electrode layer 15 is preferably, for example, about 0.5 μm or more and 2.0mm or less. The thickness of the end region 153 gradually becomes thicker from the lead portion 151 toward the outer electrode 3 side, and the end region 153 has a substantially right triangle shape, an ellipse shape, or an 1/4 circle shape in the cross-sectional view shown in fig. 2. The difference in thickness between the portion of the end region 153 having the largest thickness and the portion other than the end region 153 is preferably 0.2 μm or less.

The number of internal electrode layers 15 is preferably 15 or more and 200 or less by combining the 1 st internal electrode layer 15a and the 2 nd internal electrode layer 15 b.

The upper outer layer portion 12 and the lower outer layer portion 13 are made of the same material as the dielectric layer 14 of the inner layer portion 11. The thickness of the upper outer layer portion 12 and the lower outer layer portion 13 is preferably 20 μm or more and 60 μm or less, and more preferably 20 μm or more and 40 μm or less.

The side spacer 30 includes a 1 st side spacer 30a provided on the 1 st side surface Ba side of the laminate body 10 and a 2 nd side spacer 30b provided on the 2 nd side surface Bb side of the laminate body 10.

In addition, when it is not necessary to particularly describe the 1 st lateral spacer 30a and the 2 nd lateral spacer 30b separately, the description will be given collectively as the lateral spacers 30

The side spacers 30 cover the end portions of the internal electrode layers 15 exposed on both side surfaces of the laminate body 10 on the width direction W side. The side spacers 30 are made of the same material as the dielectric layer 14, but also contain Mg (magnesium) as a sintering aid. Mg segregates to the side of the side spacers 30 that contacts the internal electrode layer 15 by moving to the internal electrode layer 15 during sintering of the side spacers 30. Further, an interface exists between the laminate body 10 and the side partition portion 30. The thickness of the side spacer 30 is, for example, 20 μm, preferably 10 μm or less.

In the side spacer 30, the particle diameter of the dielectric particles constituting the side spacer 30 decreases from the inner layer toward the outer side. The particle diameter of the particles is preferably 400nm or more and 450nm or less at the outermost side, and 600nm or more at the innermost side, and the particle diameter of the innermost side particles is preferably 1.5 times or more as large as the particle diameter of the outermost side particles. Further, regarding the particle diameter of the particles, the center portion in the lamination direction T of the lateral spacers 30 was divided into a plurality of regions at intervals of 20nm in the width direction from the lateral surface side, the area of the particle diameter was measured in each region, and the area was converted into the circle-equivalent diameter, and the average particle diameter was obtained in each region. The average particle diameter in the region of less than 20nm is defined as the average particle diameter in this region.

In the embodiment, the side spacer portion 30 is formed as one layer, but the side spacer portion 30 is not limited to this, and may have a two-layer structure of an outer side spacer layer located on the outer side and an inner side spacer layer located on the inner electrode layer 15 side.

As described above, in the internal electrode layer 15, the line connecting the end portions on the side surface B side of the internal electrode layer 15 is convex outward in the WT cross section. Therefore, the lateral spacers 30 provided on the outer side are also convex outward in the WT cross section.

The external electrodes 3 include a 1 st external electrode 3a provided on the 1 st end face Ca of the laminate 2 and a 2 nd external electrode 3b provided on the 2 nd end face Cb of the laminate 2. In addition, when it is not necessary to particularly distinguish between the 1 st external electrode 3a and the 2 nd external electrode 3b, the description will be given collectively as the external electrodes 3. The external electrode 3 covers not only the end face C but also a part of the principal face a and the side face B on the side of the end face C.

As described above, the 1 st lead portion 151a of the 1 st internal electrode layer 15a has its end exposed at the 1 st end face Ca and is electrically connected to the 1 st external electrode 3 a. The end of the 2 nd lead portion 151b of the 2 nd internal electrode layer 15b is exposed at the 2 nd end surface Cb, and is electrically connected to the 2 nd external electrode 3 b. Thus, the 1 st external electrode 3a and the 2 nd external electrode 3b are electrically connected in parallel to each other.

The external electrode 3 has a three-layer structure including a base electrode layer 31, a conductive resin layer 32 disposed on the base electrode layer 31, and a plating layer 33 disposed on the conductive resin layer 32.

The bottom electrode layer 31 is formed by, for example, applying and baking a conductive paste containing a conductive metal and glass. As the conductive metal of the underlying electrode layer 31, for example, Cu, Ni, Ag, Pd, Ag — Pd alloy, Au, or the like can be used.

The conductive resin layer 32 is disposed to cover the underlying electrode layer 31. The conductive resin layer 32 has an arbitrary structure including a thermosetting resin and a metal component. As a specific example of the thermosetting resin, for example, various known thermosetting resins such as epoxy resin, phenol resin, polyurethane resin, silicone resin, polyimide resin, and the like can be used. As the metal component, for example, Ag or metal powder in which Ag is coated on the surface of base metal powder can be used.

The plating layer 33 is preferably formed by plating with one metal selected from the group consisting of Cu, Ni, Su, Ag, Pd, Ag — Pd alloy, Au, and the like, or an alloy containing the metal.

Since the conductive resin layer 32 contains a thermosetting resin in this manner, it is more flexible than the underlying electrode layer 31 containing a baked product of, for example, a plating film or a conductive paste. Therefore, even when physical impact or impact due to thermal cycle is applied to the multilayer ceramic capacitor 1, the conductive resin layer 32 functions as a buffer layer, prevents cracks from occurring in the multilayer ceramic capacitor 1, easily absorbs piezoelectric vibration, and has a "ringing (acoustic noise)" suppressing effect.

As described above, the use of the conductive resin layer 32 provides effects of absorbing impact and suppressing "howling". However, the conductive resin layer 32 has a higher electrical resistance than the other layers of the external electrode 3.

Therefore, as shown in fig. 2, 4, and 5, in the multilayer ceramic capacitor 1 according to the embodiment, the thickness in the stacking direction T of the end region 153 of the internal electrode layers 15 on the side of the end face C in contact with the base electrode layer 31 is larger than the thickness in the stacking direction T of the region other than the end region 153 of the internal electrode layers 15. The difference between the thickness of the end region 153 and the thickness of the region other than the end region 153 is 0.2 μm or less.

The thickness of the end region 153 of the internal electrode layer 15 in contact with the base electrode layer 31 is increased, that is, the cross-sectional area of the end region 153 of the internal electrode layer 15 in contact with the base electrode layer 31 is increased. Accordingly, the resistance value of the internal electrode layer 15, and even the resistance value of the entire electrode including the internal electrode layer 15 and the external electrode 3, becomes small, and current flows easily. This can improve the response of the multilayer ceramic capacitor 1.

Fig. 6 is a flowchart illustrating a method of manufacturing the laminated ceramic capacitor 1. Fig. 7 is a schematic plan view of the raw material sheet 103. Fig. 8 is a schematic view showing a laminated state of the raw material sheets 103. Fig. 9 is a schematic perspective view of the mother block 110.

(Master batch production Process S1)

First, a ceramic slurry containing a ceramic powder, a binder, and a solvent is prepared. The ceramic slurry is formed into a sheet shape on a mounting film by using a die coater (die coater), a gravure coater, a micro-gravure coater, or the like, thereby producing a ceramic green sheet 101 for lamination.

Next, a conductive paste is printed on the ceramic green sheet 101 for lamination by screen printing, ink jet printing, gravure printing, or the like so as to have a stripe-like pattern, thereby forming a conductive pattern 102. At this time, for example, the conductive paste is printed on the strip-shaped conductive pattern 102a plurality of times so that the portions of the laminate body 10 that become both ends in the longitudinal direction L become thick when the laminate body 10 is formed by cutting.

Thus, as shown in fig. 7, a raw material sheet 103 is prepared in which a conductive pattern 102 to be an internal electrode layer 15 is printed on the surface of a ceramic green sheet 101 for lamination to be a dielectric layer 14, the conductive pattern bulging in the central portion 102a in the longitudinal direction L.

Next, as shown in fig. 8, a plurality of raw material sheets 103 are stacked. Specifically, the plurality of raw material sheets 103 are stacked such that the strip-shaped conductive patterns 102 are oriented in the same direction, and the strip-shaped conductive patterns 102 are shifted by half a pitch in the width direction between the adjacent raw material sheets 103. Further, the ceramic green sheets 112 for the upper outer layer portion, which become the upper outer layer portion 12, are stacked on one side of the raw material sheets 103 stacked in plural, and the ceramic green sheets 113 for the lower outer layer portion, which become the lower outer layer portion 13, are stacked on the other side.

Next, the ceramic green sheet 112 for the upper outer layer portion, the stacked plurality of raw material sheets 103, and the ceramic green sheet 113 for the lower outer layer portion are thermocompression bonded. Thereby, the mother block 110 shown in fig. 9 is formed.

(Master block dividing step S2)

Next, as shown in fig. 9, the mother block 110 is divided along a cutting line X corresponding to the size of the laminate body 10 and a cutting line Y intersecting the cutting line X. At this time, the cutting line X cuts the raised central portion 102a of the conductive pattern 102. In the embodiment, the cutting line Y is orthogonal to the cutting line X. This produces a plurality of laminate bodies 10 in which the end regions 153 of the internal electrode layers 15 in contact with the base electrode layers 31 are thickened as shown in fig. 5.

(step S3 of sticking ceramic Green sheet for side spacer)

Next, a ceramic slurry in which Mg was added as a sintering aid to the same dielectric powder as the ceramic green sheet 101 for lamination was prepared. Then, a ceramic slurry was applied to the resin film and dried to produce a ceramic green sheet for a side spacer.

Then, the side spacer ceramic green sheets are bonded to the side portion of the laminate body 10 where the internal electrode layers 15 are exposed, thereby forming a layer to be the side spacer 30. At this time, since the side portion of the internal electrode layer 15 of the package laminate body 10 is exposed by pressing the side spacer ceramic green sheets, the end portion in the width direction W of the 1 st internal electrode layer 15a and the end portion in the width direction W of the 2 nd internal electrode layer 15b are pressed by the side spacer ceramic green sheets as described above, and the upper and lower ends in the stacking direction T are slightly retracted inward. As a result, the line indicated by a dotted line in fig. 3 connecting the end portions on the side face B side of the internal electrode layers 15 is slightly convex outward in the WT cross section, which is a cross section in the width direction W and the stacking direction T passing through the center of the stacked body 2.

(side spacer firing step S4)

The laminate body 10 having the layers to be the side spacers 30 formed thereon is degreased under a predetermined condition in a nitrogen atmosphere, and then fired and sintered at a predetermined temperature in a mixed atmosphere of nitrogen, hydrogen, and water vapor to form the laminate 2.

Here, during sintering, Mg in the side spacer portions 30 moves toward the internal electrode layer 15. Thus, Mg in the side spacers 30 segregates to the inner electrode layer side after sintering. Although the dielectric layers 14 and the side spacers 30 are made of substantially the same material, the side spacers 30 are adhered to the laminate body 10 including the dielectric layers 14, and therefore, even after firing, there is an interface between the side spacers 30 and the laminate body 10.

(external electrode Forming Process S5)

Next, the base electrode layer 31, the conductive resin layer 32, and the plating layer 33 are sequentially formed on both end portions of the laminate 2, thereby forming the external electrodes 3.

(firing Process S6)

Then, the laminate 2 having the external electrodes 3 formed on both ends thereof was heated at a predetermined firing temperature in a nitrogen atmosphere for a predetermined time. Thus, the multilayer ceramic capacitor 1 was manufactured.

At this time, the thickness of the end region 153 of the internal electrode layer 15 exposed on the end face C side in the stacking direction T is thicker than the thickness of the region other than the end region 153 of the internal electrode layer 15. Therefore, the cross-sectional area of the connection portion between the internal electrode layer 15 and the base electrode layer 31 becomes large. The multilayer ceramic capacitor 1 has a small resistance value and is easy to flow a current. This can improve the response of the multilayer ceramic capacitor 1.

While the embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and various modifications can be made within the scope of the present invention.