阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 吴咏捷 何彦忠 许秉诚 马礼修 林仲德 于 2021-06-08 设计创作，主要内容包括：一种半导体装置,包含至少一个选择器装置。每个选择器装置包括自底部至顶部包含底部电极、金属氧化物半导体通道层、以及顶部电极,且位于一基板上方的垂直堆叠；接触底部电极、金属氧化物半导体通道层、以及顶部电极的侧壁的栅极介电层；以及形成于栅极介电层之中,且所具有的顶部表面与顶部电极的顶部表面共平面的栅极电极。上述至少一个选择器装置的每个顶部电极或每个底部电极可接触对应的非易失性存储器元件,以提供单选择器-单电阻器存储器单元。(A semiconductor device includes at least one selector device. Each selector device includes a vertical stack comprising, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode, and located over a substrate; a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode; and a gate electrode formed in the gate dielectric layer and having a top surface coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may contact a corresponding non-volatile memory element to provide a single selector-single resistor memory cell.)

1. A semiconductor device, comprising:

at least one selector device, wherein each of the at least one selector device comprises:

a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode, the vertical stack being located above a substrate;

a gate dielectric layer contacting the sidewalls of the bottom electrode, the MOS channel layer, and the top electrode; and

a gate electrode formed in the gate dielectric layer, the gate electrode having a top surface coplanar with a top surface of the top electrode.

Technical Field

The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a vertical field effect transistor as a selector device for a memory cell.

Background

Conventional selector devices, such as diodes or ovonic threshold switches (ovonic switches), have limitations in device density, leakage current level, high threshold voltage, on-off ratio, and manufacturing cost. Therefore, there is a need for a compact, low cost selector device for array applications.

Disclosure of Invention

The disclosed embodiments provide a semiconductor device. The semiconductor device comprises at least one selector device. Each of the at least one selector device comprises: a vertical stack comprising, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode, and located above the substrate 700; a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode; and a gate electrode formed in the gate dielectric layer and having a top surface coplanar with a top surface of the top electrode.

The embodiment of the disclosure provides a memory array. The memory array includes an array of selector devices. Each selector device in the array of selector devices includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode, over a substrate, and laterally contacting a corresponding gate structure, wherein the corresponding gate structure includes a corresponding gate dielectric layer and a corresponding gate electrode. The memory array further includes an array of non-volatile memory elements, wherein each non-volatile memory element in the array of non-volatile memory elements contacts a horizontal surface of a top electrode or a bottom electrode of a corresponding selector device in the array of selector devices.

The embodiment of the disclosure provides a method for forming a semiconductor device. The method for forming the semiconductor device comprises depositing a thin layer stack on a substrate, wherein the thin layer stack comprises a bottom electrode layer, a metal oxide semiconductor channel material layer and a top electrode layer. A plurality of trenches are etch cut through the thin layer stack, wherein a plurality of vertical stacks of corresponding bottom electrodes, corresponding metal oxide semiconductor channel layers, and corresponding top electrodes are formed. A layer of gate dielectric material L and a layer of gate electrode material are deposited in the plurality of trenches and over the plurality of vertical stacks. Portions of the layer of gate dielectric material and the layer of gate electrode material are removed from above a horizontal plane including the top surfaces of the plurality of vertical stacks. The gate dielectric material layer includes a gate dielectric layer 50 in each remaining portion of the plurality of trenches, and the gate electrode material layer includes a gate electrode 52 in each remaining portion of the plurality of trenches. A non-volatile memory element is formed on a top surface of each corresponding top electrode.

Drawings

The disclosure can be better understood from the following description and drawings. It is emphasized that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A is a vertical cross-sectional view of an example structure after forming a dielectric material layer having a metal interconnect structure formed therein and a via cavity extending through the via-level dielectric material layer, in accordance with an embodiment of the present disclosure.

FIG. 1B is a top view of the exemplary structure of FIG. 1A, where a vertical cross-sectional plane A-A' is a plane that is a vertical cross-section of FIG. 1A.

Fig. 2A is a vertical cross-sectional view of an example structure after forming a bottom electrode layer, a layer of metal oxide semiconductor channel material, and a top electrode layer, in accordance with an embodiment of the present disclosure.

Fig. 2B is a top view of the example structure of fig. 2A, where a vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 2A.

Fig. 3A is a vertical cross-sectional view of an example structure after patterning a vertical stack of a bottom electrode layer, a layer of metal oxide semiconductor channel material, and a top electrode layer, in accordance with an embodiment of the present disclosure.

Fig. 3B is a top view of the exemplary structure of fig. 3A, where the vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 3A.

Fig. 4A is a vertical cross-sectional view of an exemplary structure after forming a layer of gate dielectric material and a layer of gate electrode material, in accordance with an embodiment of the present disclosure.

Fig. 4B is a top view of the exemplary structure of fig. 4A, where the vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 4A.

Figure 5A is a vertical cross-sectional view of an exemplary structure after forming a gate dielectric layer and a gate electrode, in accordance with an embodiment of the present disclosure.

Fig. 5B is a top view of the example structure of fig. 5A, where the vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 5A.

Figure 6A is a vertical cross-sectional view of an example structure after forming a layer of non-volatile memory material, in accordance with an embodiment of the present disclosure.

Fig. 6B is a top view of the example structure of fig. 6A, where the vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 6A.

Figure 7A is a vertical cross-sectional view of an example structure after forming an array of non-volatile memory elements, in accordance with an embodiment of the present disclosure.

Fig. 7B is a top view of the example structure of fig. 7A, where the vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 7A.

Figure 8A is a vertical cross-sectional view of an example structure after formation of a memory level dielectric layer, in accordance with an embodiment of the present disclosure.

Fig. 8B is a top view of the example structure of fig. 8A, where the vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 8A.

Fig. 9A is a vertical cross-sectional view of an example structure after formation of dielectric isolation structures, in accordance with an embodiment of the present disclosure.

Fig. 9B is a top view of the example structure of fig. 9A, where the vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 9A.

Fig. 9C is a horizontal cross-sectional view of the exemplary structure of fig. 9A along a horizontal plane C-C ', where a vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 9A.

Fig. 10A is a vertical cross-sectional view of an exemplary structure after tunneling into a memory level dielectric layer and dielectric isolation structures, in accordance with an embodiment of the present disclosure.

Fig. 10B is a top view of the example structure of fig. 10A, where the vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 10A.

FIG. 11A is a vertical cross-sectional view of an exemplary structure after forming bit lines, according to an embodiment of the disclosure.

Fig. 11B is a top view of the example structure of fig. 11A, where the vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 11A.

Figure 12A is a vertical cross-sectional view of an example structure after formation of a contact level dielectric layer and a gate electrode contact via structure, in accordance with an embodiment of the present disclosure.

Fig. 12B is a top view of the example structure of fig. 12A, where the vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 12A.

Fig. 12C is a vertical cross-sectional view of the exemplary structure along the vertical plane C-C of fig. 12B.

Fig. 13A is a vertical cross-sectional view of an alternative configuration of an example structure, shown in accordance with an embodiment of the present disclosure.

Fig. 13B is a top view of an alternative configuration of the example structure of fig. 13A, where the vertical cross-sectional plane a-a' is the plane of the vertical cross-section of fig. 13A.

Fig. 13C is a vertical cross-sectional view of an alternative configuration of the exemplary structure along vertical plane C-C of fig. 13B.

FIG. 14 is a first flowchart illustrating operations for forming an example structure of the present disclosure, according to an embodiment of the present disclosure.

Wherein the reference numerals are as follows:

12 via level dielectric layer

19 bottom electrode level via cavity

700 base plate

720 semiconductor device

760 layer of dielectric material

780 metal interconnection structure

hd1 first horizontal direction

hd2 second horizontal direction

A-A' vertical section plane

20L bottom electrode layer

30L of metal oxide semiconductor channel material layer

40L top electrode layer

20 bottom electrode

30 metal oxide semiconductor channel layer

40 top electrode

51 linear groove

50L gate dielectric material layer

52L layer of gate electrode material

50 gate dielectric layer

52 gate electrode

60L non-volatile memory material layer

60 non-volatile memory element

70 memory level dielectric layer

72 dielectric isolation structure

Plane of C-C

80 bit line

90 contact level dielectric layer

92 gate electrode contact via structure

1410 to 1450 operation

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of the components and arrangements of the present disclosure are set forth below to simplify the description. Of course, these examples are not intended to limit the present disclosure. For example, if the description recites a first feature formed on or over a second feature, it may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which additional features are formed between the first and second features, such that direct contact between the first and second features is not provided. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, the present disclosure may use spatially relative terms, such as "below …," "below," "…," "above," and the like, to facilitate describing the relationship of one element or feature to another element or feature in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be turned to a different orientation (rotated 90 degrees or otherwise) and the spatially relative terms used herein should be interpreted accordingly. Unless explicitly stated otherwise, it shall be assumed that each element having the same reference sign has the same material composition and has a thickness within the same thickness range.

The present disclosure is directed generally to semiconductor devices, and more particularly to semiconductor devices including a vertical field effect transistor (field effect transistor) as a selector device for a memory cell (cell) and methods of forming the same.

Two-dimensional memory arrays in a cross-point array configuration use word lines and bit lines to individually access memory cells. The selection of a single memory cell can be achieved by selecting both word lines and bit lines. Half-select (half-select) occurs on a row of memory elements connected to the selected word line but not to the selected bit line. Similarly, half-select may occur on a column of memory cells connected to the selected bit line but not to the selected word line. Although the half-selected memory elements are not activated (activated) for reading or programming (programming), these memory elements generate a large amount of leakage current, which may render a large two-dimensional cross-point array practically inoperable.

According to embodiments of the present disclosure, selector elements may be introduced into a cross-point memory array to address leakage current issues from half-selected memory cells. In this embodiment, the selector elements may be connected to the memory elements in a series connection. In particular, vertical channel field effect transistors may be used as selector elements. The vertical channel field effect transistors of the various embodiments allow electrical conduction through the vertical channel field effect transistor only when the vertical channel field effect transistor is turned on by application of a gate bias voltage (bias voltage). Using vertical channel field effect transistors as selector elements in a cross-point memory array may enhance signal-to-noise ratio (signal-to-noise ratio) in the cross-point memory array, enhance the operating window of the cross-point memory array, and/or provide a larger cross-point memory array including more memory elements. Various aspects of embodiments of the disclosure are described in detail below.

Fig. 1A is a vertical cross-sectional view of an example structure after forming a dielectric material layer having a metal interconnect structure formed therein and forming a via cavity (cavity) extending through a via-level dielectric material layer, in accordance with an embodiment of the present disclosure. FIG. 1B is a top view of the example structure of FIG. 1A. The vertical cross-sectional plane A-A' is a plane that is a vertical cross-section of FIG. 1A. Referring to fig. 1A and 1B, fig. 1A and 1B illustrate an example structure according to an embodiment of the present disclosure. The exemplary structure includes a substrate 700, and the substrate 700 may be a semiconductor substrate, such as a silicon wafer. In embodiments where the substrate 700 is a semiconductor substrate, a semiconductor device 720, such as a field effect transistor, may be formed on the top surface of the substrate 700. In one embodiment, the semiconductor device 720 may include logic circuitry for controlling operation of a subsequently formed two-dimensional memory array. In an illustrative example, a two-dimensional memory array may include a two-dimensional array of non-volatile (nonvolatile) memory elements, while a field effect transistor selected from semiconductor device 720 may include programming circuitry and sensing circuitry for the array of non-volatile memory elements.

A layer of dielectric material 760 having a metal interconnect structure 780 formed therein may be formed over the field effect transistor. The metal interconnect 780 may be connected to an electrical node (e.g., a field effect transistor) of a semiconductor device 720. A subset of metal interconnect structures 780 may electrically connect corresponding (resistive) nodes of a field effect transistor to corresponding nodes of a two-dimensional memory array to be subsequently formed. In one embodiment, a subset of metal interconnect structures 780 may be electrically connected to electrical nodes of field effect transistors and may later be electrically connected to bottom electrodes or top electrodes of an array of selector devices to be subsequently formed. In one embodiment, the subset of metal interconnect structures 780 located at the topmost level of metal interconnect structures 780 may include word lines, which are then connected to the bottom electrodes of the selector devices to be subsequently formed.

In one embodiment, the via level dielectric layer 12 may be formed over the dielectric material layer 760. The via level dielectric layer 12 may comprise an interlayer dielectric (ILD) material such as undoped silicate glass (undoped silicate glass), doped silicate glass, organosilicate glass, or porous dielectric material. Other suitable materials that may be used as an interlayer dielectric are also included within the scope of the present disclosure. The thickness of the via level dielectric layer 12 may be in the range from 60nm (nanometers) to 600nm, such as in the range from 120nm to 300nm, although lesser and greater thicknesses may also be used. The via level dielectric layer 12 may be formed by a conformal or non-conformal deposition process, such as chemical vapor deposition (cvd) or spin-coating (spin-coating).

A photoresist layer (not shown) may be applied over the via level dielectric layer 12 and may be lithographically patterned to form discrete openings through the via level dielectric layer 12. In one embodiment, the discrete openings through the photoresist layer may be formed as a two-dimensional periodic (periodic) array of discrete openings that may repeat with a first periodicity along the first horizontal direction hd1 and a second periodicity along the second horizontal direction hd 2. The first periodicity may be the same as the pitch of the word lines (a word line may be a subset of metal interconnect structures 780 located at the topmost level of metal interconnect structures 780). The second periodicity may be the same as a pitch of a bit line to be subsequently formed. The first pitch may be in the range from 30nm to 1000nm, for example in the range from 60nm to 500nm, although smaller or larger dimensions may also be used. The second pitch may be in the range from 30nm to 1000nm, such as in the range from 60nm to 500nm, although smaller and larger dimensions may also be used.

An anisotropic (anistropic) etch process may be performed to transfer the pattern of the openings in the photoresist layer through the via-level dielectric layer 12. A via cavity may be formed through the via level dielectric layer 12. These via cavities are referred to herein as bottom electrode level via cavities 19. The top surface of the underlying metal interconnect 780, which may be the top surface of a word line, may be physically exposed at the bottom of the bottom electrode-level via cavity 19. The lateral dimension of each bottom electrode-level via cavity 19 along the first horizontal direction hd1 and/or along the second horizontal direction hd2 may be in the range from 15nm to 500nm, such as in the range from 30nm to 250nm, although smaller and larger dimensions may also be used. Each bottom electrode-level via cavity 19 may have a circular or elliptical horizontal cross-sectional shape, a rectangular horizontal cross-sectional shape, a rounded rectangular horizontal cross-sectional shape, or any conventional non-intersecting closed two-dimensional curvilinear shape (two-dimensional curvilinear). The photoresist layer may then be removed, for example, by ashing (ashing).

Fig. 2A is a vertical cross-sectional view of an example structure after forming a bottom electrode layer, a metal oxide semiconductor (metal oxide semiconductor) channel material layer, and a top electrode layer, in accordance with an embodiment of the present disclosure. Fig. 2B is a top view of the example structure of fig. 2A. The vertical cross-sectional plane A-A' is a plane that is a vertical cross-section of FIG. 2A. Referring to fig. 2A and 2B, the bottom electrode layer 20L, the metal oxide semiconductor channel material layer 30L, and the top electrode layer 40L may be sequentially deposited to form a vertical stack of selector element layers (bottom electrode layer 20L, metal oxide semiconductor channel material layer 30L, top electrode layer 40L). The bottom electrode layer 20L includes a first metal electrode material, which may be a conductive metal nitride material, an elemental metal, or an intermetallic alloy (intermetallic alloy). For example, the bottom electrode layer 20L may comprise TiN, TaN, WN, W, Ti, Co, Mo, Ru, and/or combinations or alloys thereof. Other suitable materials that may be used for the bottom electrode layer 20L are also within the contemplation of this disclosure. The thickness of the bottom electrode layer 20L may be selected such that the entire volume of each bottom electrode-level via cavity 19 is filled with the material of the bottom electrode layer 20L. Alternatively, the horizontally extending portion of the bottom electrode layer 20L covering the top surface of the via-level dielectric layer 12 may be thinned as needed. The thickness of the bottom electrode layer 20L, measured above the horizontal top surface of the via level dielectric layer 12, may be in the range from 10nm to 250nm, such as in the range from 20nm to 120nm, although smaller and larger thicknesses may also be used. The bottom electrode layer 20L may be formed by chemical vapor deposition (cvd), physical vapor deposition (pvd), electroplating (electroplating), or a combination thereof. The bottom electrode layer 20L may include a horizontally extending portion above a horizontal plane containing the top surface of the via-level dielectric layer 12, and a two-dimensional array of via portions formed in the via-level dielectric layer 12.

The metal oxide semiconductor channel material layer 30L includes a metal oxide semiconductor material, such as Indium Gallium Zinc Oxide (IGZO), doped zinc oxide, doped indium oxide, or doped cadmium oxide. Other suitable materials that may be used as the metal oxide semiconductor channel material layer 30L are also within the scope of the present disclosure. The doping level in the metal oxide semiconductor channel material layer 30L may be selected such that leakage current through the metal oxide semiconductor channel material layer 30L may be negligible during operation of the device. For example, metal oxide semiconductorsThe doping level in the body channel material layer 30L may be from 1.0X 10¹⁰/cm³To 2.0X 10¹⁶/cm³Although lower and higher dopant concentrations may also be used.

The use of a metal oxide semiconductor material in place of an elemental semiconductor material or a III-V compound semiconductor material in the layer of metal oxide semiconductor channel material 30L provides the advantage of suppressing leakage currents to a negligible degree, thereby enhancing the effectiveness of the subsequently formed selector device (effect). The metal oxide semiconductor material can provide a thickness of greater than 1.0 × 10⁹The on-off ratio of (c). In other words, for a field effect transistor using a metal oxide semiconductor material as a channel material, the ratio of the on-current to the off-current may be greater than 1.0 × 10⁹. In contrast, a channel composed of an elemental semiconductor material and a III-V compound semiconductor material provides an on-off ratio of about 1.0 × 10⁴. Thus, the use of a metal oxide semiconductor material as a channel material provides the benefit of low leakage current and enhances the effectiveness of the selector device of the present disclosure.

The top electrode layer 40L includes a second metal electrode material, which may be a conductive metal nitride material, an elemental metal, or an intermetallic alloy. Any material that can be used for the bottom electrode layer 20L can be used for the top electrode layer 40L. The thickness of the top electrode layer 40L may be in the range from 10nm to 250nm, such as in the range from 20nm to 120nm, although lesser and greater thicknesses may also be used. The top electrode layer 40L may be formed by chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof.

Fig. 3A is a vertical cross-sectional view of an example structure after patterning a vertical stack of a bottom electrode layer, a layer of metal oxide semiconductor channel material, and a top electrode layer, in accordance with an embodiment of the present disclosure. Fig. 3B is a top view of the example structure of fig. 3A. The vertical cross-sectional plane A-A' is a plane that is a vertical cross-section of FIG. 3A. Referring to fig. 3A and 3B, a photoresist layer (not shown) may be applied over the top electrode layer 40L and may be lithographically patterned to form openings in the photoresist layer. In one embodiment, the pattern of openings in the photoresist layer may be linear openings extending laterally (laterally) along the second horizontal direction hd2 and having a periodic pitch along the first horizontal direction, wherein the periodic pitch is twice the pitch of the array of via portions of the bottom electrode layer 20L along the first horizontal direction hd 1. In other words, a pair of via hole portions of the bottom electrode layer 20L may be disposed between each pair of adjacent linear openings passing through the photoresist layer along the first horizontal direction hd 1.

An anisotropic etch process may be performed to transfer the pattern of linear openings in the photoresist layer through the thin layer stack of the top electrode layer 40L, the metal oxide semiconductor channel material layer 30L, and the bottom electrode layer 20L. A trench may be etched through the thin layer stack of the top electrode layer 40L, the metal oxide semiconductor channel material layer 30L, and the bottom electrode layer 20L. In an embodiment, the grooves may include linear grooves 51 each having a uniform width. For example, linear trenches 51 extending laterally along the second horizontal direction hd2 and laterally spaced from each other along the first horizontal direction hd1 may be formed through the thin layer stack of the top electrode layer 40L, the metal oxide semiconductor channel material layer 30L, and the bottom electrode layer 20L. The photoresist layer may then be removed, for example, by ashing.

Each patterned portion of the bottom electrode layer 20L includes a bottom electrode 20. Each patterned portion of the metal oxide semiconductor channel material layer 30L includes a metal oxide semiconductor channel layer 30. Each patterned portion of the top electrode layer 40L includes a top electrode 40. A vertical stack of bottom electrode 20, metal oxide semiconductor channel layer 30, and top electrode 40 may be formed between each pair of adjacent linear trenches 51. Each linear trench 51 may have a uniform width, which may be in the range from 15nm to 500nm, for example in the range from 30nm to 250nm, although smaller and larger widths may also be used. Each vertical stack of the bottom electrode 20, the mos channel layer 30 and the top electrode 40 may have a uniform width along the first horizontal direction hd1, which may be in the range from 45nm to 1500nm, for example in the range from 90nm to 750nm, although smaller and larger widths may also be used.

Generally, a vertical stack of at least one bottom electrode 20, a metal oxide semiconductor channel layer 30 and a top electrode 40 may be deposited over the substrate 700. In one embodiment, a column of vertical stacks may be deposited over the substrate 700 such that the vertical stacks are disposed along the first horizontal direction hd1 and laterally separated from each other along the second horizontal direction hd2 by linear trenches 51, wherein the linear trenches 51 extend laterally along the second horizontal direction hd 2. In one embodiment, each bottom electrode 20 includes a plate (plate) portion overlying the via-level dielectric layer 12 and includes at least one via portion formed within the via-level dielectric layer 12 and abutting the (adjoin) plate portion. The flat portion of each bottom electrode 20 includes a horizontally extending portion of the corresponding bottom electrode 20 having a uniform thickness.

Fig. 4A is a vertical cross-sectional view of an exemplary structure after forming a layer of gate dielectric material and a layer of gate electrode material, in accordance with an embodiment of the present disclosure. Fig. 4B is a top view of the example structure of fig. 4A. The vertical cross-sectional plane A-A' is a plane that is a vertical cross-section of FIG. 4A. Referring to fig. 4A and 4B, a layer of gate dielectric material 50L may be formed by a conformal deposition process and formed on the physically exposed surface of the vertical stack of the bottom electrode 20, the mos channel layer 30, and the top electrode 40. The gate dielectric material layer 50L includes a gate dielectric material, such as silicon oxide, silicon oxynitride, a dielectric metal oxide, or a stack thereof. Other suitable materials that may be used as the gate dielectric material layer 50L are also within the contemplation of the present disclosure. The gate dielectric material layer 50L may be formed by at least one conformal deposition process, such as at least one chemical vapor deposition process. The thickness of the gate dielectric material layer 50L may be in the range from 1nm to 12m, for example, in the range from 2nm to 6nm, although lesser and greater thicknesses may also be used.

A gate electrode material layer 52L may be formed over the gate dielectric material layer 50L. Gate electrode materialLayer 52L may comprise a doped semiconductor material or a metallic material. Doped semiconductor materials that may be used for the gate electrode material layer 52L include doped polysilicon, silicon germanium alloy, or doped III-V compound semiconductor materials. The doped semiconductor material may comprise dopants with a doping concentration of from 1.0 × 10¹⁹/cm³To 2.0X 10²¹/cm³Although lower and higher doping concentrations may also be used. The dopant may be p-type or n-type. Metallic materials that may be used for the gate electrode material layer 52L include conductive metal nitride materials (e.g., TiN, TaN, and WN), elemental metals (e.g., W, Ta, Ru, Co, or Mo), and intermetallic alloys of at least two metals. Other suitable materials that may be used as the gate electrode material layer 52L are also within the contemplation of the present disclosure. The thickness of the gate electrode material layer 52L may be in the range from 50nm to 300nm, although lesser and greater thicknesses may also be used.

Figure 5A is a vertical cross-sectional view of an exemplary structure after forming a gate dielectric layer and a gate electrode, in accordance with an embodiment of the present disclosure. Fig. 5B is a top view of the example structure of fig. 5A. The vertical cross-sectional plane A-A' is a plane that is a vertical cross-section of FIG. 5A. Referring to fig. 5A and 5B, portions of the gate dielectric material layer 50L and the gate electrode material layer 52L may be removed from above a horizontal plane including top surfaces of the vertical stack of the corresponding bottom electrode 20, the corresponding metal oxide semiconductor channel layer 30, and the corresponding top electrode 40. For example, a Chemical Mechanical Polishing (CMP) process may be performed to remove excess portions of gate dielectric material layer 50L and gate electrode material layer 52L from above a horizontal plane including the top surface of top electrode 40. In one embodiment, the horizontally extending portion of the gate dielectric material layer 50L may be used as a planarization stop layer and may subsequently be selectively removed relative to the material of the top electrode 40.

Each remaining portion of the gate dielectric material layer 50L in the linear trenches 51 includes the gate dielectric layer 50. Each remaining portion of the gate electrode material layer 52L in the linear trench 51 (as shown in fig. 3A and 3B) includes a gate electrode 52. Each stack of gate dielectric layer 50 and gate electrode 52 includes a gate structure (gate dielectric layer 50, gate electrode 52). It should be noted that for clarity of description, the gate structures (gate dielectric layer 50, gate electrode 52) will be referred to as gate structures (50, 52) hereinafter. In one embodiment, each gate structure (50, 52) may laterally contact a corresponding pair of vertical stacks, wherein the corresponding vertical stacks are comprised of a corresponding bottom electrode 20, a corresponding metal oxide semiconductor channel layer 30, and a corresponding top electrode 40. In one embodiment, each gate dielectric layer 50 may contact sidewalls of a pair of bottom electrodes 20, sidewalls of a pair of metal oxide semiconductor channel layers 30, and sidewalls of a pair of top electrodes 40. In one embodiment, the gate electrode 52 may comprise and/or may consist essentially of at least one metallic material. In this embodiment, the gate electrode 52 may be a metal gate electrode. In one embodiment, each gate electrode 52 may be formed within a corresponding gate dielectric layer 50 and may have a horizontal top surface that is coplanar (coplanar) with the top surface of top electrode 40.

In one embodiment, each gate dielectric layer 50 may include a horizontal portion in contact with a bottom surface of the gate electrode 52 and a pair of vertically extending portions adjoining a periphery of the horizontal portion. One of the pair of vertically extending portions may contact sidewalls of the bottom electrode 20, the metal oxide semiconductor channel layer 30, and the top electrode 40 on one side of the gate dielectric layer 50, and the other of the pair of vertically extending portions may contact sidewalls of the bottom electrode 20, the metal oxide semiconductor channel layer 30, and the top electrode 40 on the other side of the gate dielectric layer 50.

Figure 6A is a vertical cross-sectional view of an example structure after forming a layer of non-volatile memory material, in accordance with an embodiment of the present disclosure. Fig. 6B is a top view of the example structure of fig. 6A. The vertical cross-sectional plane A-A' is a plane that is a vertical cross-section of FIG. 6A. Referring to fig. 6A and 6B, a layer of non-volatile memory material 60L may be deposited over the top electrode 40 and the gate electrode 52. Non-volatile storageThe device material layer 60L includes non-volatile memory material, i.e., memory material capable of storing information in a permanent or semi-permanent manner. For example, the non-volatile memory material layer 60L may include a phase change material, a vacancy modulated conductive oxide (mosfet) material, or a ferroelectric memory material. Exemplary phase change materials include chalcogenide glass (chalcogenide glass) materials, such as alloys of gallium, antimony, and tellurium. Other suitable materials that may be used as the non-volatile memory material layer 60L are also within the contemplation of this disclosure. An exemplary vacancy modulating conductive oxide material is vacancy-rich titanium oxide, which is a non-stoichiometric (non-stoichiometric) titanium comprising oxygen vacancies. Exemplary ferroelectric memory materials include hafnium oxide (e.g., hafnium oxide containing at least one dopant selected from the group consisting of Al, Zr, and Si and having a ferroelectric non-centrosymmetric orthorhombic phase), zirconium oxide, hafnium zirconium oxide, bismuth ferrite, barium titanate (e.g., BaTiO)₃(ii) a BT), and lead zirconate titanate (e.g.: pb (Zr, Ti) O₃(ii) a PZT). The non-volatile memory material layer 60L may be deposited by any suitable deposition method, such as by chemical vapor deposition or physical vapor deposition. The thickness of the non-volatile memory material layer 60L may be in the range from 3nm to 100nm, such as in the range from 6nm to 50nm, depending on the type of non-volatile memory material, although lesser and greater thicknesses may also be used. In one embodiment, a sacrificial stop layer (not shown) may be selectively deposited on the non-volatile memory material layer 60L, which may then be used as an etch stop layer or a planarization stop layer for a chemical mechanical polishing process.

Figure 7A is a vertical cross-sectional view of an example structure after forming an array of non-volatile memory elements, in accordance with an embodiment of the present disclosure. Fig. 7B is a top view of the example structure of fig. 7A. The vertical cross-sectional plane A-A' is a plane that is a vertical cross-section of FIG. 7A. Referring to fig. 7A and 7B, a photoresist layer (not shown) may be applied over the non-volatile memory material layer 60L and may be lithographically patterned to form a two-dimensional array of discrete photoresist portions. The patterned photoresist portion may be laterally offset (offset) from the gate electrode 52. In one embodiment, at least one pair of patterned photoresist portions is laterally spaced along the first horizontal direction hd1 and is provided between each pair of adjacent gate electrodes 52. In one embodiment, pairs of patterned photoresist portions may be formed between each pair of adjacent gate electrodes 52 such that the pairs of patterned photoresist portions may be aligned along the second horizontal direction. For example, a 2 × N rectangular array of photoresist portions may be formed over the area of each top electrode 40, where N may be any positive integer.

An anisotropic etch process may be performed to transfer the pattern in the patterned photoresist portion through the layer of non-volatile memory material 60L. The unmasked portions of the non-volatile memory material layer 60L may be removed by an anisotropic etch process. Each remaining portion of the non-volatile memory material layer 60L includes a non-volatile memory element 60. The photoresist layer may then be removed, for example, by ashing.

Each non-volatile memory element 60 may be formed on a top surface of a corresponding top electrode 40. Generally, the non-volatile memory element 60 may be formed by depositing and patterning a non-volatile memory material, wherein the non-volatile memory material may be selected from a phase change material, a vacancy-modulated conductive oxide material, and a ferroelectric memory material. Each top electrode 40 may contact at least one non-volatile memory element 60 and may contact an array of non-volatile memory elements 60.

Figure 8A is a vertical cross-sectional view of an example structure after formation of a memory level dielectric layer, in accordance with an embodiment of the present disclosure. Fig. 8B is a top view of the example structure of fig. 8A. The vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 8A. Referring to fig. 8A and 8B, a memory level dielectric layer 70 may be deposited over the top electrode 40 and the non-volatile memory elements 60. The memory level dielectric layer 70 comprises a dielectric material, such as undoped silicate glass, doped to silicate glass, or organosilicate glass. Other suitable materials that may be used as the memory level dielectric layer 70 are also within the contemplation of this disclosure. The thickness of the memory level dielectric layer 70 may be greater than the thickness of the non-volatile memory element 60 and may be in the range from 50nm to 300nm, although lesser and greater thicknesses may also be used. A memory level dielectric layer 70 laterally surrounds the non-volatile memory elements 60.

Fig. 9A is a vertical cross-sectional view of an example structure after formation of dielectric isolation structures, in accordance with an embodiment of the present disclosure. Fig. 9B is a top view of the example structure of fig. 9A. The vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 9A. Fig. 9C is a horizontal cross-sectional view of the exemplary structure of fig. 9A along a horizontal plane C-C'. The vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 9A. Referring to fig. 9A-9C, a photoresist layer (not shown) may be applied over the memory level dielectric layer 70 and may be lithographically patterned to form discrete openings through the photoresist layer. In one embodiment, the pattern of openings through the photoresist layer may be selected such that each opening through the photoresist layer covers a pair of non-volatile memory elements 60 and a corresponding pair of via portions of the bottom electrode 20. In one embodiment, the pattern of openings through the photoresist layer may be two-dimensional periodic rectangular openings having a pitch along the first horizontal direction hd1 that is the same as the pitch of the gate electrodes 52 along the first horizontal direction hd1, and having a pitch along the second horizontal direction hd2 that is the same as the pitch of the via portions of the bottom electrodes 20 along the second horizontal direction hd 2. In one embodiment, the patterned portion of the photoresist layer may have the shape of a rectangular frame including a two-dimensional periodic array of rectangular openings therethrough.

An anisotropic etch process may be performed to transfer the pattern in the photoresist layer into a vertical stack through the gate structure (50, 52) and the corresponding bottom electrode 20, mos channel layer 30, and top electrode 40. Interdigitated linear trenches may be formed through the gate structures (50, 52) and the vertical stack (bottom electrode 20, metal oxide semiconductor channel layer 30, top electrode 40). It should be noted that for clarity of description, the vertical stack (bottom electrode 20, metal oxide semiconductor channel layer 30, top electrode 40) is referred to as vertical stack (20, 30, 40) hereinafter. In this embodiment, one top electrode 40 contacts the plurality of non-volatile memory elements 60, and after forming the linear trenches, each vertical stack of one bottom electrode 20, one metal oxide semiconductor channel layer 30, and one top electrode 40 is divided into a plurality of vertical stacks of a corresponding bottom electrode 20, a corresponding metal oxide semiconductor channel layer 30, and a corresponding top electrode 40. A vertically stacked two-dimensional rectangular array of corresponding bottom electrodes 20, corresponding metal oxide semiconductor channel layers 30, and corresponding top electrodes 40 may be formed. Each gate structure (50, 52) may be divided by linear trenches into an array of gate structures (50, 52) arranged along the second horizontal direction. The photoresist layer may then be removed, for example, by ashing.

A dielectric fill material, such as undoped silicate glass or doped silicate glass, may be deposited in the intersecting network of linear trenches that laterally separate the vertical stacks of the corresponding bottom electrodes 20, the corresponding metal oxide semiconductor channel layers 30, and the corresponding top electrodes 40. The portions of the deposited dielectric fill material filling the linear trenches collectively form a dielectric isolation structure 72, and the dielectric isolation structure 72 may be a cross-network of dielectric material rails (rails) extending laterally along either the first horizontal direction hd1 or the second horizontal direction hd 2. The portion of the dielectric fill material deposited above the horizontal plane containing the top surface of the memory level dielectric layer 70 may or may not be removed. In one embodiment, the portion of the dielectric fill material deposited above the horizontal plane including the top surface of the memory level dielectric layer 70 may be removed by a recess etch process.

Generally, the dielectric isolation structures 72 extend vertically through the vertically stacked levels of the corresponding bottom electrode 20, the corresponding metal oxide semiconductor channel layer 30, and the corresponding top electrode 40. The dielectric isolation structure 72 may laterally surround each combination of a first vertical stack (20, 30, 40), a gate structure (50, 52), and a second vertical stack (20, 30, 40).

A two-dimensional array of selector devices connected in series with corresponding non-volatile memory elements 60 may be provided. Each selector device comprises a vertical stack (20, 30, 40), a gate dielectric layer 50, and a gate electrode 52, wherein the vertical stack (20, 30, 40) comprises, from bottom to top, a bottom electrode 20, a metal oxide semiconductor channel layer 30, and a top electrode 40, and is located above a substrate 700; the gate dielectric layer 50 contacts the sidewalls of the bottom electrode 20, the metal oxide semiconductor channel layer 30, and the top electrode 40; a gate electrode 52 is formed in the gate dielectric layer 50 and has a top surface that is coplanar with the top surface of the top electrode 40. In one embodiment, each bottom electrode 20 includes a planar portion overlying the via-level dielectric layer 12 and contacting the gate dielectric layer 50 of the corresponding selector device, and includes a via portion formed within the via-level dielectric layer 12 and abutting the planar portion.

In one embodiment, the gate structures (50, 52) may laterally contact a corresponding pair of vertical stacks (20, 30, 40), wherein the vertical stacks (20, 30, 40) are comprised of a corresponding bottom electrode 20, a corresponding metal oxide semiconductor channel layer 30, and a corresponding top electrode 40 in the selector array. A pair of selector devices may share a gate structure (50, 52). For example, the first selector device (20, 30, 40, 50, 52) and the second selector device (20, 30, 40, 50, 52) may comprise two vertical stacks of a corresponding bottom electrode 20, a corresponding metal oxide semiconductor channel layer 30, and a corresponding top electrode 40, and the gate dielectric layer 50 of the first selector device (20, 30, 40, 50, 52) and the gate dielectric layer 50 of the second selector device (20, 30, 40, 50, 52) may comprise a single gate dielectric layer 50 shared between the first selector device (20, 30, 40, 50, 52) and the second selector device (20, 30, 40, 50, 52). Further, the gate electrode 52 of the first selector device (20, 30, 40, 50, 52) and the gate electrode 52 of the second selector device (20, 30, 40, 50, 52) may comprise a single gate electrode 52 shared between the first selector device (20, 30, 40, 50, 52) and the second selector device (20, 30, 40, 50, 52).

In one embodiment, each gate dielectric layer 50 may include a horizontal portion in contact with a bottom surface of the gate electrode 52 and a pair of vertically extending portions adjoining a periphery of the horizontal portion. One of the pairs of vertically extending portions contacts sidewalls of the bottom electrode 20, the metal oxide semiconductor channel layer 30, and the top electrode 40 of the first selector device (20, 30, 40, 50, 52), while the other of the pairs of vertically extending portions contacts sidewalls of the bottom electrode 20, the metal oxide semiconductor channel layer 30, and the top electrode 40 of the second selector device (20, 30, 40, 50, 52). The dielectric isolation structure 72 may contact sidewalls of each bottom electrode 20, each metal oxide semiconductor channel layer 30, and each top electrode 40, wherein the sidewalls do not contact the corresponding gate dielectric layer 50. The dielectric isolation structure 72 may contact sidewalls of the via level dielectric layer 12.

Figure 10A is a vertical cross-sectional view of an exemplary structure after tunneling (stress) of a memory level dielectric layer and dielectric isolation structures, in accordance with an embodiment of the present disclosure. Fig. 10B is a top view of the example structure of fig. 10A. The vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 10A. Referring to fig. 10A and 10B, the memory level dielectric layer 70 and the dielectric isolation structures 72 may be dug vertically. For example, a trench etch process or a Chemical Mechanical Polishing (CMP) process may be used to vertically trench the memory level dielectric layer 70 and the dielectric isolation structures 72. The depth of the dig may be controlled such that the top surface of the non-volatile memory element 60 is physically exposed. If a trench etch process is used to trench the memory level dielectric layer 70 and the dielectric isolation structures 72, the non-volatile memory element 60 may be used for end point detection (end point detection) during the trench etch process. If a Chemical Mechanical Polishing (CMP) process is used to dig into the memory level dielectric layer 70 and the dielectric isolation structures 72, a sacrificial stop layer (not shown) may be used, which may be deposited over the non-volatile memory material layer 60L in the process operations of fig. 6A and 6B and may be removed in a final operation of the CMP process.

FIG. 11A is a vertical cross-sectional view of an exemplary structure after forming bit lines, according to an embodiment of the disclosure. Fig. 11B is a top view of the example structure of fig. 11A. The vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 11A. Referring to fig. 11A and 11B, bit lines 80 extending laterally along the first horizontal direction hd1 may be formed on the top surface of the non-volatile memory elements and above the top surface of the memory level dielectric layer 70. Each bit line 80 may contact a top surface of a corresponding row of non-volatile memory elements 60, wherein the row of non-volatile memory elements 60 is arranged along the first horizontal direction hd 1. Each non-volatile memory element 60 may contact a corresponding bit line 80. In one embodiment, bit lines 80 may be formed by depositing and patterning a metal layer into a linear structure. Alternatively, a damascene (damascone) process may be used to form bit line 80. In this embodiment, a bit line level dielectric layer (not shown) may be formed over the memory level dielectric layer 70, linear trenches may be formed through the bit line level dielectric layer over each column of non-volatile memory elements 60 arranged along the first horizontal direction hd1, and bit lines 80 may be formed on top surfaces of the corresponding columns of non-volatile memory elements 60.

Fig. 12A is a vertical cross-sectional view of an example structure after formation of a contact level dielectric layer and a gate electrode contact via structure, in accordance with an embodiment of the present disclosure. Fig. 12B is a top view of the example structure of fig. 12A. The vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 12A. Fig. 12C is a vertical cross-sectional view of the exemplary structure along the vertical plane C-C of fig. 12B. Referring to fig. 12A-12C, a contact level dielectric layer 90 may be formed over bit line 80 and/or formed around bit line 80. In this embodiment, where bit line 80 is formed using a damascene process, contact level dielectric 90 may be incorporated into and/or identical to the bit line level dielectric. The contact level dielectric 90 has a top surface that may be in or on a horizontal plane that includes the top surface of the bit lines.

Gate electrode contact via structures 92 may be formed through the contact level dielectric layer 90 and the memory level dielectric layer 70 on the top surface of the corresponding gate electrode 52. Each gate electrode 52 may contact a corresponding gate electrode contact via structure 92. For example, a photoresist layer (not shown) may be applied over the contact level dielectric layer 90 and may be lithographically patterned to form a two-dimensional array of openings in the area overlying the gate electrode 52. An anisotropic etch process may be performed to form via cavities extending through the contact-level dielectric layer 90 and the memory-level dielectric layer 70 and down to the top surface of the corresponding gate electrode 52. The photoresist layer may then be removed, for example, by ashing. At least one conductive material may be deposited into the via cavity to form a gate electrode contact via structure 92. Excess portions of the at least one conductive material may be removed from over the top surface of the contact level dielectric 90 by a planarization process, which may use a dig etch process and/or a chemical mechanical polish process.

Fig. 13A is a vertical cross-sectional view of an alternative configuration of an example structure, shown in accordance with an embodiment of the present disclosure. Fig. 13B is a top view of an alternative configuration of the example structure of fig. 13A. The vertical cross-sectional plane a-a' is a plane that is a vertical cross-section of fig. 13A. Fig. 13C is a vertical cross-sectional view of an alternative configuration of the exemplary structure along vertical plane C-C of fig. 13B. Referring to fig. 13A-13C, fig. 13A-13C illustrate an alternative configuration of an example structure that can be derived from the example structure of fig. 12A-12C by forming a memory level dielectric layer 70 having a two-dimensional array of non-volatile memory elements 60 formed therein over a layer of dielectric material 760 having a metal interconnect structure 780 formed therein. Subsequently, the pattern of the bottom electrode-level via cavities 19 may be modified to perform the process operations of fig. 1A-6B such that a via portion of each bottom electrode 20 is formed on the top surface of the corresponding non-volatile memory element 60. Thereafter, a connection-level dielectric layer 76 may be formed over the vertically stacked two-dimensional array of corresponding bottom electrodes 20, corresponding metal-oxide-semiconductor channel layers 30, and corresponding top electrodes 40. The top electrode contact via structure 48 may be formed through a connection level dielectric layer 76 on a top surface of a corresponding one of the top electrodes. The process operations of fig. 11A and 11B may then be modified and performed such that each bit line 80 is formed on a corresponding row of top electrode contact via structures 48. The process operations of fig. 12A and 12B may then be performed to form a gate electrode contact via structure 92 that contacts a corresponding gate electrode 52.

Referring to fig. 1A-13C and in accordance with various embodiments of the present disclosure, the present disclosure provides a device structure (or semiconductor device) including at least one selector device (20, 30, 40, 50, 52). Each of the at least one selector device (20, 30, 40, 50, 52) comprises: a vertical stack comprising, from bottom to top, a bottom electrode 20, a metal oxide semiconductor channel layer 30, and a top electrode 40, and located above a substrate 700; a gate dielectric layer 50 contacting sidewalls of the bottom electrode 20, the metal oxide semiconductor channel layer 30, and the top electrode 40; and a gate electrode 52 formed in the gate dielectric layer 50 and having a top surface coplanar with the top surface of the top electrode 40.

In one embodiment, gate dielectric layer 50 includes a horizontal portion in contact with a bottom surface of gate electrode 52, and includes a pair of vertically extending portions adjacent to a periphery of the horizontal portion. One of a pair of vertically extending portions contacts the sidewalls of the bottom electrode 20, the metal oxide semiconductor channel layer 30, and the top electrode 40.

In one embodiment, each top electrode 40 (shown in fig. 12A-12C) or each bottom electrode (shown in fig. 13A-13C) of the at least one selector device (20, 30, 40, 50, 52) contacts a corresponding non-volatile memory element 60. In one embodiment, the corresponding non-volatile memory element 60 comprises a material selected from the group consisting of a phase change material, a vacancy-modulated conductive oxide material, and a ferroelectric memory material. In one embodiment, each non-volatile memory element 60 contacts a corresponding bit line 80, wherein the bit lines 80 extend laterally along a horizontal direction, as shown in fig. 12A-12C. In one embodiment, each gate electrode 52 contacts a corresponding gate electrode contact via structure 92.

In one embodiment, the at least one selector device includes a first selector device (20, 30, 40, 50, 52) and a second selector device (20, 30, 40, 50, 52), the first selector device (20, 30, 40, 50, 52) and the second selector device (20, 30, 40, 50, 52) including two vertical stacks of a corresponding bottom electrode 20, a corresponding metal oxide semiconductor channel layer 30, and a corresponding top electrode 40. The gate dielectric layer 50 of the first selector device (20, 30, 40, 50, 52) and the gate dielectric layer 50 of the second selector device (20, 30, 40, 50, 52) may comprise a single gate dielectric layer 50 shared between the first selector device (20, 30, 40, 50, 52) and the second selector device (20, 30, 40, 50, 52). The gate electrode 52 of the first selector device (20, 30, 40, 50, 52) and the gate electrode 52 of the second selector device (20, 30, 40, 50, 52) may comprise a single gate electrode 52 shared between the first selector device (20, 30, 40, 50, 52) and the second selector device (20, 30, 40, 50, 52).

In one embodiment, the device structure includes a via level dielectric layer 12 located below a gate dielectric layer 50; and each bottom electrode 20 includes a planar portion overlying the via-level dielectric layer 12 and contacting the gate dielectric layer 50 of the corresponding selector device (20, 30, 40, 50, 52), and includes a via portion formed in the via-level dielectric layer 12 and abutting the planar portion. In one embodiment, the device structure includes a dielectric isolation structure 72 that contacts additional sidewalls of the bottom electrode 20, the metal oxide semiconductor channel layer 30, and the top electrode 40, and contacts sidewalls of the via level dielectric layer 12.

In one embodiment, the above apparatus structure comprises: a field effect transistor on top of the substrate 700; and a metal interconnect structure 780 formed in the dielectric material layer 760. A subset of metal interconnect structures 780 are electrically connected to electrical nodes of the field effect transistors and to the bottom electrode 20 or the top electrode 40 of the at least one selector device. In this embodiment, a subset of the metal interconnect structures 780 are electrically connected to the top electrode 40 of the at least one selector device (20, 30, 40, 50, 52), and a subset of the metal interconnect structures 780 may be electrically connected to the bit line 80, but not to the bottom electrode 20.

According to another aspect of the present disclosure, a memory array is provided that includes an array of selector devices (20, 30, 40, 50, 52). Each selector device (20, 30, 40, 50, 52) of the array of selector devices (20, 30, 40, 50, 52) comprises a vertical stack comprising, from bottom to top, a bottom electrode 20, a metal oxide semiconductor channel layer 30, and a top electrode 40, and located above the substrate 700, and laterally contacting a corresponding gate structure (50, 52), wherein the gate structure (50, 52) comprises a corresponding gate dielectric layer 50 and a corresponding gate electrode 52. Each selector device (20, 30, 40, 50, 52) in the array of selector devices (20, 30, 40, 50, 52) contacts a non-volatile memory element 60. Each non-volatile memory element 60 in the array of non-volatile memory elements 60 contacts a horizontal surface of the top electrode 40 or the bottom electrode 20 of a corresponding selector device (20, 30, 40, 50, 52) in the array of selector devices (20, 30, 40, 50, 52).

In one embodiment, each gate structure (50, 52) laterally contacts a corresponding pair of vertical stacks (20, 30, 40) in the array of selector devices (20, 30, 40, 50, 52). In one embodiment, the dielectric isolation structure 72 may extend vertically through the level of the vertical stack (20, 30, 40) and laterally surround each combination of the first vertical stack (20, 30, 40), the gate structure (50, 52), and the second vertical stack (20, 30, 40).

In one embodiment, the memory array includes bit lines 80, the bit lines 80 contacting corresponding columns of non-volatile memory elements 60, wherein the corresponding columns of non-volatile memory elements 60 are selected from the array of non-volatile memory elements 60. In one embodiment, the memory device includes a plurality of field effect transistors on top of the substrate 700 and including programming circuitry and sensing circuitry for the array of non-volatile memory elements 60, and a metal interconnect structure 780 formed in the layer of dielectric material 760 and electrically connected to an electrical node of the plurality of field effect transistors and to the bottom electrode 20 or the top electrode 40 of the array of selector devices (20, 30, 40, 50, 52).

Referring to FIG. 14, FIG. 14 shows a first flowchart of process operations for forming the disclosed device structure. Referring to operation 1410 and fig. 1A-2B, a thin layer stack including a bottom electrode layer 20L, a metal oxide semiconductor channel material layer 30L, and a top electrode layer 40L may be deposited over the substrate 700. Referring to operation 1420 and fig. 3A and 3B, a trench (e.g., linear trench 51) may be etched through the thin layer stack. A vertical stack (20, 30, 40) of a corresponding bottom electrode 20, a corresponding metal oxide semiconductor channel layer 30, and a corresponding top electrode 40 may be formed. Referring to operation 1430 and fig. 4A and 4B, a layer of gate dielectric material 50L and a layer of gate electrode material 52L may be deposited in the trench and over the vertical stack (20, 30, 40). Referring to operation 1440 and fig. 5A and 5B, portions of gate dielectric material layer 50L and gate electrode material layer 52L may be removed from above a horizontal plane including the top surface of the vertical stack (20, 30, 40). Each remaining portion of gate dielectric material layer 50L in the trench includes gate dielectric layer 50, and each remaining portion of gate electrode material layer 52L in the trench includes gate electrode 52. Referring to operation 1450 and fig. 6A-7B, a non-volatile memory element 60 may be formed on a top surface of each top electrode 40. Subsequently, the process operations of fig. 8A-12C may be selectively performed to provide electrical wiring (wiring) to the device structure. Alternatively, the array of non-volatile memory elements 60 may be formed first, and the array of selector devices (20, 30, 40, 50, 52) may be formed over the array of non-volatile memory elements 60.

In one embodiment, the non-volatile memory element is formed by depositing and patterning a material selected from the group consisting of phase change materials, vacancy-modulated conductive oxide materials, and ferroelectric memory materials. In one embodiment, the method of forming the device structure of the present disclosure further comprises forming a memory-level dielectric layer laterally surrounding the non-volatile memory elements; and forming a plurality of bit lines extending laterally along a horizontal direction on a top surface of a corresponding subset of the non-volatile memory elements over a top surface of the memory level dielectric layer.

In one embodiment, the method of forming the device structure of the present disclosure further comprises forming a plurality of gate electrode contact via structures through the memory level dielectric layer on the top surface of the corresponding gate electrode. In one embodiment, the method of forming the device structure of the present disclosure further comprises forming a plurality of field effect transistors on top of the substrate; and forming a plurality of dielectric material layers over the plurality of field effect transistors, the plurality of dielectric material layers having a plurality of metal interconnect structures formed therein, wherein a subset of the plurality of metal interconnect structures are electrically connected to a plurality of electrical nodes of the plurality of field effect transistors and to a corresponding bottom electrode or a corresponding top electrode.

Various embodiments of the present disclosure may be used to provide a cross-point array of unit device structures, each including a series connection of non-volatile memory elements 60 and selector devices (20, 30, 40, 50, 52). Each selector device (20, 30, 40, 50, 52) includes a vertical field effect transistor using a metal oxide semiconductor channel that can provide a high switching current ratio and can effectively suppress leakage current through unselected non-volatile memory elements 60. Thus, high signal-to-noise ratios and integration of large numbers of memory elements can be achieved by the disclosed devices.

The foregoing outlines features of various embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. It should also be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure.