阅读说明：本技术 半导体器件及其形成方法 (Semiconductor device and method of forming the same ) 是由 林孟汉 吴伟成 于 2019-05-27 设计创作，主要内容包括：本发明提供一种方法,在所述方法中,制成与嵌入式存储器阵列的闪存单元基本相同的监测器单元。监测器单元与存储器阵列的单元同时形成,并因此在某些关键方面,二者可进行完全匹配。形成孔,孔延伸穿过控制栅极和介入电介质到达监测器单元的浮置栅极。为预防后续CMP工艺中的硅化物污染,在浮置栅极上形成硅化物接触件之前,在控制栅极的暴露部分上形成硅化物保护层(SPL),比如,光刻胶保护氧化物。SPL与现有制造工艺同时形成,以避免额外的工艺步骤。本发明的实施例还涉及半导体器件及其形成方法。(The present invention provides a method in which a monitor cell is made substantially identical to a flash cell of an embedded memory array. The monitor cells are formed simultaneously with the cells of the memory array and thus, in certain critical aspects, the two can be perfectly matched. A hole is formed extending through the control gate and the intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination in subsequent CMP processes, a Silicide Protection Layer (SPL), such as a photoresist protection oxide, is formed on the exposed portion of the control gate prior to forming a silicide contact on the floating gate. The SPL is formed simultaneously with the existing manufacturing process to avoid additional process steps. Embodiments of the invention also relate to semiconductor devices and methods of forming the same.)

1. A method of forming a semiconductor device, comprising:

defining a plurality of chips on a wafer of semiconductor material;

forming a respective one of a plurality of microprocessor devices on each of the chips defined on the semiconductor material wafer, each of the microprocessor devices including an embedded memory;

forming a monitor unit on the wafer of semiconductor material, comprising:

forming a floating gate, a control gate and a corresponding dielectric layer;

forming a hole extending through a control gate of the monitor cell and exposing a portion of a floating gate of the monitor cell;

forming a silicide protection layer on a portion of a control gate of the monitor cell, the portion of the control gate being exposed by forming the hole; and

after the forming of the silicide protection layer, forming a silicide contact terminal on a portion of a floating gate of the monitor cell, the portion of the floating gate being exposed by forming the hole.

2. The method of claim 1, wherein forming the silicide protection layer comprises forming a silicide protection layer while performing processing steps associated with forming the plurality of microprocessor devices.

3. The method of claim 1, comprising: after forming the silicide contact terminals, chemical mechanical polishing of the semiconductor material wafer is performed and a portion of the control gates of the monitor cells are exposed.

4. The method of claim 3, comprising, after performing chemical mechanical polishing of the wafer of semiconductor material:

depositing an interlevel dielectric layer on the semiconductor material wafer;

forming a metal layer on the interlayer dielectric layer; and

forming an electrical connector between the electrical trace of the metal layer and the silicide contact terminal.

5. The method of claim 1, wherein forming a monitor unit on the wafer of semiconductor material comprises forming a monitor unit on a portion of the wafer of semiconductor material that is not defined as part of one of the plurality of chips.

6. The method of claim 1, wherein forming monitor units on the wafer of semiconductor material comprises forming monitor units on each of the chips defined on the wafer of semiconductor material.

7. The method of claim 1, wherein forming the floating gate, control gate, and corresponding dielectric layer of the monitor cell comprises:

forming a same first tunneling dielectric layer of the monitor cell and a memory cell of each embedded memory;

forming the same floating gate of the monitor cell and a memory cell of each embedded memory; and

the same control gate of the monitor cell and the memory cell of each embedded memory are formed.

8. The method of claim 1, wherein forming the floating gate, control gate, and corresponding dielectric layer of the monitor cell comprises:

the same second tunneling dielectric layer of the monitor cell and the memory cell of each embedded memory are formed between the respective floating gate and the corresponding erase gate.

9. A method of forming a semiconductor device, comprising:

forming a plurality of identical memory cells on a wafer of semiconductor material;

forming a monitor cell including exposing a portion of a floating gate of one of the plurality of memory cells by forming a hole in a portion of the one of the plurality of memory cells;

forming a silicide contact terminal on the exposed portion of the floating gate; and

when a material is exposed by forming the hole and the exposed material is susceptible to forming a silicide, a silicide prevention layer is formed on the exposed material in addition to the exposed portion of the floating gate before forming a silicide contact terminal on the exposed portion of the floating gate.

10. A semiconductor device, comprising:

a wafer of semiconductor material;

a plurality of chips defined on the semiconductor material wafer;

a memory array formed on each of the plurality of chips; and

a monitor unit formed on the semiconductor material wafer and having:

a floating gate identical to a floating gate of a memory cell of the memory array formed on each of the plurality of chips,

a first tunneling dielectric layer that is the same as a corresponding tunneling dielectric layer of memory cells of the memory array formed on each of the plurality of chips,

a silicide contact terminal formed on the floating gate,

an electrical connector extending through an aperture formed in a control gate of the monitor unit, an

A silicide protection layer in contact with the control gate within the hole.

Technical Field

Embodiments of the invention relate to semiconductor devices and methods of forming the same.

Background

Flash memory has certain advantages and benefits over other types of solid state non-volatile memory structures. For example, many of these advantages and benefits are associated with improved read, write and/or erase speeds, power consumption, compactness, cost, and the like. Flash memory is commonly used in high density data storage devices and portable USB data storage devices configured for use in cameras, cell phones, voice recorders-commonly referred to as thumb drives or flash drives, etc. Typically, in such applications, the flash memory is fabricated on a dedicated microchip and then coupled in a single package with another chip or chips containing the appropriate processor circuitry, or in a separate package configured to be electrically coupled.

Processors with embedded flash memory are a recent development. In such devices, the flash array is fabricated on a single chip along with logic and control circuitry. Such arrangements are typically used in microcontroller units (MCUs), i.e. small computer devices integrated on a single chip, the latter typically being designed to repeatedly perform a limited number of specific tasks. MCUs are often used in smart cards, wireless communication devices, automotive control units, etc. Integration of memory with associated processing circuitry may increase processing speed while reducing package size, power consumption, and cost.

Disclosure of Invention

An embodiment of the present invention provides a method of forming a semiconductor device, including: defining a plurality of chips on a wafer of semiconductor material; forming a respective one of a plurality of microprocessor devices on each of the chips defined on the semiconductor material wafer, each of the microprocessor devices including an embedded memory; forming a monitor unit on the wafer of semiconductor material, comprising: forming a floating gate, a control gate and a corresponding dielectric layer; forming a hole extending through a control gate of the monitor cell and exposing a portion of a floating gate of the monitor cell; forming a silicide protection layer on a portion of a control gate of the monitor cell, the portion of the control gate being exposed by forming the hole; and forming a silicide contact terminal on a portion of a floating gate of the monitor cell, the portion of the floating gate being exposed by forming the hole, after the forming of the silicide protection layer.

Another embodiment of the present invention provides a method of forming a semiconductor device, including: forming a plurality of identical memory cells on a wafer of semiconductor material; forming a monitor cell including exposing a portion of a floating gate of one of the plurality of memory cells by forming a hole in a portion of the one of the plurality of memory cells; forming a silicide contact terminal on the exposed portion of the floating gate; and forming a silicide prevention layer on the exposed material in addition to the exposed portion of the floating gate before forming a silicide contact terminal on the exposed portion of the floating gate when the material is exposed by forming the hole and the exposed material is susceptible to forming a silicide.

Still another embodiment of the present invention provides a semiconductor device including: a wafer of semiconductor material; a plurality of chips defined on the semiconductor material wafer; a memory array formed on each of the plurality of chips; and a monitor unit formed on the semiconductor material wafer and having: a floating gate that is identical to a floating gate of a memory cell of the memory array formed on each of the plurality of chips, a first tunneling dielectric layer that is identical to a corresponding tunneling dielectric layer of a memory cell of the memory array formed on each of the plurality of chips, a silicide contact terminal formed on the floating gate, an electrical connector extending through a hole formed in a control gate of the monitor cell, and a silicide protection layer in contact with the control gate within the hole.

Drawings

Embodiments of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a schematic cross-sectional side view of a portion of a semiconductor device (e.g., a microcontroller unit) during fabrication according to one embodiment.

Fig. 2A is a schematic plan view of a semiconductor wafer 106 having a plurality of devices of fig. 1 formed thereon.

Fig. 2B is an enlarged view of a portion 2B of the wafer 106 of fig. 2A, showing additional details, according to one embodiment.

Fig. 3 is a schematic side sectional view of a monitor unit according to an embodiment.

Fig. 4A-4C are schematic side cross-sectional views of a semiconductor material wafer at respective stages of a fabrication process, showing a portion of one of a plurality of devices, such as the device described above with reference to fig. 1 and similar to the device described above with reference to fig. 3.

Fig. 5A-5D are schematic side cross-sectional views of a wafer at a respective stage of a manufacturing process according to one embodiment, wherein fig. 5A shows the wafer at a stage of manufacture subsequent to processing in the stage shown in fig. 4A, and the stages shown in fig. 5B and 5C correspond to the stages shown in fig. 4B and 4C, respectively. Fig. 5D shows the monitor unit of fig. 5A-5C at a stage corresponding to the stage of manufacture shown in fig. 1.

Fig. 6 shows a schematic side view of a monitor unit as an alternative structure to that of fig. 2A to 4C, the structure being made using an alternative process to that described with reference to fig. 4A to 4C and corresponding to the stage of manufacture shown in fig. 4B.

Fig. 7 is a schematic side view of a monitor unit according to one embodiment as an alternative structure to the monitor unit in fig. 5A-5D, and in particular corresponding to the stage of manufacture shown in fig. 5B.

Fig. 8 is a flow chart illustrating a method of manufacturing consistent with the process described with reference to fig. 5A-5D and 7, according to an embodiment.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different functions of the inventive subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatial relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as shown. Spatial relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.

In the drawings, some elements are designated with reference numerals plus letters, such as "704 a, 704 b". In this case, letter designations are used which, in the corresponding description, may be used to refer to or distinguish between particular elements of the many other similar or identical elements. If the specification omits letters from the references and refers to these elements by numbers only, it is to be understood that a general reference to any or all of the elements identified by the reference numeral may be made unless other distinguishing language is used.

A microcontroller unit (MCU) typically includes a number of discrete devices such as a Central Processing Unit (CPU) core, a Static Random Access Memory (SRAM) array (or module), a flash memory module, a system integration module, a timer, an analog-to-digital converter (ADC), a communication and networking module, a power management module, and the like. Each of these devices in turn comprises a number of passive and active electronic components, such as resistors, capacitors, transistors and diodes. A large number of these components, in particular active components, are based on various types of Field Effect Transistors (FETs). In a FET, the conductivity in the channel region extending between the source and drain terminals is controlled by the electric field in the channel region, which is generated by the voltage difference between the control gate and the body of the device.

Fig. 1 is a schematic side cross-sectional view of a portion of a device 100 (e.g., MCU) during fabrication, according to one embodiment. The device 100 includes a flash memory array 102 and a processor 104 formed on a semiconductor wafer 106. The processor 104 includes a transistor 108 as part of a logic circuit, while the memory array 102 includes a pair of flash memory cells 110.

Transistor 108 includes a channel region 114 extending between a drain region 116 and a source region 118. The control gate 120 is isolated from the channel region 114 by a gate dielectric 122, and a silicide contact terminal 124 is formed over the drain and source regions 116, 118.

The flash memory cell 110 includes a respective channel region 114 extending under a respective floating gate 126 and select gate 128, a respective drain 116 and these share a common source region 119. Each flash memory cell 110 includes a control gate 121, a floating gate 126 between the control gate and the channel region 114, and a select gate 128 adjacent to the control gate and the floating gate. A gate dielectric 122 separates the channel region 114 from the respective floating and select gates 126, 128. The pair of flash memory cells share a common erase gate 130 that is separated from the source region 119 by a dielectric oxide region 132. Each floating gate 126 is separated from the erase gate 130 by a tunnel oxide layer 134. The isolation trenches 136 and polysilicon dummy walls 137 separate regions of the device 100 having different types or levels of conductivity. Additional silicide contact terminals 135 are formed on the upper surfaces of the strips (not shown in fig. 1) of select gates 128, erase gates 130, and control gates 121.

An interlayer dielectric (ILD)138 layer extends over the wafer 106, and a via 140 extends from an upper surface of the ILD to the silicide contact terminal 124. The electrical traces 142 formed in the first metal layer 144 are coupled to the respective silicide contact terminals 124 by metal connectors 146 formed in the vias 140.

Although connections are not shown for each component, it should be understood that in actual practice, connections are provided for the control gates 120, 121, the common source region 119, the select gate 128, the common source region 119, etc. to electrically contact each component with the appropriate circuitry. In some cases, the connection is made through a metal layer, similar to those shown. In other cases, the connections are formed on or over the substrate 106. Only the floating gate 126 is fully isolated from direct electrical contact with other components and circuitry of the device 100.

Various material layers 148 are shown in general outline, which are not configured to function as conductors or semiconductors in device 100. These layers may include dielectric layers, photoresist overlays, passivation layers, etch stop layers, spacers, and the like.

As described above, the logic transistor 108 operates by applying an electric field across the channel region 114, thereby changing the conductivity of the channel region. The electric field is generated by applying a voltage potential between the control gate 120 and the semiconductor body 106. The FET may be configured to increase or decrease conductivity when an electric field of a selected polarity is present. Typically, the transistors in the logic circuit are designed to operate as switches, turning on or off and controlling in response to an electric field having a selected strength.

In memory cell 110, during a write operation, electrons may be forced to tunnel through gate dielectric 122 to floating gate 126, where they may hold a well indefinitely, by applying a write voltage to control gate 121 while creating a current in channel region 114. If a sufficient number of electrons are trapped on the floating gate 126, the electrons may block the electric field generated by the control gate 121, thereby preventing the control gate from acting to change conductivity in the channel region 114. Thus, the presence of electrons can be detected by applying a voltage potential across the drain and source regions 116, 119 while applying a read voltage to the control gate 121 to generate an electric field and test the current in the channel region 114. Typically, a binary value of 1 is the default setting of the flash memory cell at the time of manufacture and prior to programming, while a binary value of zero is indicated if the channel current is not affected by the read voltage at control gate 121. A binary zero value on a flash memory cell can be erased-i.e., returned to a zero value-by applying a sufficiently strong erase voltage to erase gate 130. This allows electrons trapped on the floating gates 126 of both memory cells 110 to tunnel through the tunnel oxide layer 134 to the erase gate 130. In actual operation, there will be more memory cells adjacent to erase gate 130 that extend along rows perpendicular to the view of FIG. 1. During an erase operation, each of these memory cells will be erased simultaneously-i.e., in flash memory-hence the name flash memory.

The term tunneling is used herein to refer to any process by which electrons move to or from a floating gate through a dielectric layer, including, for example, fowler-nordheim tunneling, quantum tunneling, hot electron injection, and the like.

As technology advances, devices are becoming smaller and more compact, reducing power and voltage requirements, and increasing speed. However, problems that arise with the reduction in size are: previously negligible variations in the thickness or quality of the gate dielectric 122 or tunnel oxide 134 can significantly affect the operating parameters of the cell.

This is especially true at technology nodes below 65nm, 40nm and 28 nm. As a result, extensive testing of newly manufactured devices is necessary to determine the appropriate voltage levels for read, write and erase operations. This is a time consuming operation because the floating gate 126 is completely isolated, making it impossible to simply apply a voltage and measure the effect. Instead, repeated read, write, and erase operations must be performed at different voltage and time settings in order to generate enough data to infer the appropriate values for the chips of a given wafer.

One solution has been proposed as described with reference to fig. 2A, 2B and 3. Fig. 2A is a schematic plan view of a semiconductor wafer 106 having a plurality of devices 100 of fig. 1 formed thereon. Fig. 2B is an enlarged view of a portion 2B of the wafer 106 of fig. 2A, showing additional details, according to one embodiment. The devices 100 are separated by scribe lines 150 along which the wafer 106 will be diced to create individual microchips. The scribe lines 150 comprise saw cuts that will be used to separate the wafer 106 into dies or chips 100, defining chips on the wafer. The material removed by the saw and the material surrounding the device 100 will be discarded as waste after the separation process. However, it is common practice to form additional devices and circuitry 152 in scribe lines 15, as shown in fig. 2B. These devices are commonly referred to as Process Control Monitor (PCM) test keys and are used to monitor various functions and processes during manufacture to ensure proper operability of the chip 100. These devices can be used to monitor, for example, threshold voltage, saturation current, off current, breakdown voltage, back-end processing, capacitance, and resistance, among others. It has been proposed to form one or more monitor cells in the PCM test key 152, as described below. Fig. 3 is a schematic side sectional view of a monitor unit 160 according to an embodiment of the proposed solution. For example, the monitor unit 160 is formed on the wafer 106 in one or more test keys 152. The elements of monitor cell 160 are formed concurrently with the formation of similar elements of memory cell 110 of device 100 of fig. 1, and the monitor cell is identical to the memory cell in most respects. During the formation of memory cell 110, substantially identical structures, including, for example, channel region 114, source and drain regions 116, 119, gate dielectric 122, tunnel oxide 134, floating gate 126a, control gate 121a, etc., are simultaneously formed in monitor cell 160 using the same processes. However, after the control gate 121a is formed, a hole 162 is etched through the control gate and intervening dielectric layer 148a to expose a portion of the surface of the floating gate 126 a.

The term "simultaneously" is used herein to refer to a plurality of processing tasks being performed simultaneously, and by the same processing steps. For example, if the gate dielectric layer 122 for each of the plurality of memory cells 110 is formed by depositing a single dielectric layer over the portion of the wafer 106 where those memory cells are placed, and then patterned to define that single gate dielectric layer 122, the gate dielectric layers may be described as having been formed simultaneously. Likewise, if the gate dielectric layer 122a is formed of the same single dielectric layer as the gate dielectric layer 122 of the memory cell 110 and patterned by the same process, then the gate dielectric layer of the monitor unit 160 can be described as being formed at the same time as the gate dielectric layer of the memory cell.

With continued reference to fig. 3, a metal silicide contact 124a is formed on the surface of the floating gate 126a, and when the via 140 is later formed in the memory array 102 and the processor 104, an additional via 140a and connector 146a are formed in the monitor cell 160 above the floating gate 126a, bringing the floating gate 126a into contact with the electrical trace 142 of the first metal layer 144. According to one embodiment, the floating gate 126a is in electrical contact with a contact pad formed in one of the metal layers, where the contact pad is accessed for testing prior to completion of the wafer. According to another embodiment, the floating gate 126a is ultimately in electrical contact with a contact pad at the uppermost surface of the wafer 200 through electrical connections in various additional metal layers. This enables access to the floating gate 126a for various appropriate tests before the wafer is separated into individual chips. Alternatively, the monitor unit 160 is separate from the wafer 106, as part of a small additional microchip with limited circuitry, which may be tested while the rest of the device 100 is further processed and packaged. According to other embodiments, the monitor cell 160 is formed on each semiconductor die, for example, by modifying one memory cell 110 of the cell array for this purpose.

According to one embodiment, the steps of forming silicide contacts 124a, vias 140a, and connectors 146a are performed simultaneously with forming silicide contacts 124, vias 140, and connectors 146 of memory cells 110. Also, even though memory cell 110 does not include structures similar to hole 162, there are many processes for forming other components of device 100, including multiple etching processes, in addition to those used to form memory array 102. According to one embodiment, the holes 162 are formed while the processes for fabricating the other components of the device 100 are performed.

At a later stage in the manufacturing process, a test is performed in which varying values and combined voltages are applied to the source and drain regions 116, 119 and the floating and erase gates 126a, 130 to create conditions for the write and erase processes. By doing so, the floating gate 126a may be excited and the electron current density may be directly measured to determine whether the insulating oxide meets device specifications and used to establish the appropriate read, write and erase voltages.

Since monitor cell 160 is formed at the same time as memory array 102 of device 100, in some embodiments, most of the elements of the monitor cell (including tunnel dielectrics 122, 134) are substantially the same as the corresponding elements of memory cell 110 and, of course, also share common features other than the non-operation of control gate 121 a. Furthermore, the only expense is the initial modification of the appropriate mask and tool without adding additional production costs. On the other hand, a simplified test procedure will reduce the cost per wafer production.

In fig. 3, a single monitor cell 160 is shown and described, which is substantially identical in most respects to the memory cells 110 of the flash memory array 102 of the device 100. However, according to other embodiments, for example, the plurality of monitor units 160 are fabricated as a plurality of individual units, a single array of units, or as a plurality of test keys 152 or an array of units, or spaced apart units or arrays around the perimeter of the wafer 160. In addition, according to various embodiments, cells of different sizes and/or shapes are made. Multiple monitor units, differently sized monitor units, and/or different shapes may provide additional data regarding unit or dielectric quality or performance, etc. Finally, according to some embodiments, one or more monitor units 160 are included on each device 100, enabling testing to be performed after dicing of the wafer 160.

While the above process is considered a very economical alternative to the relatively expensive process, the present inventors have recognized a problem associated with the proposed process that may result in a significant increase in chip rejection and a reduction in performance, and may offset any potential cost savings. This problem is explained below with reference to fig. 4A to 4C.

Fig. 4A-4C are schematic side cross-sectional views of the wafer 106 at respective stages of the fabrication process, illustrating a portion of one of a plurality of devices 100, such as the device described above with reference to fig. 1, that will ultimately be separated from the wafer 106 as respective chips. Also shown is a monitor unit 160 formed in the PCM test keys 152 of the wafer 106, as described above with reference to fig. 2B and 3. The views and corresponding descriptions shown in fig. 4A-4C are isolated steps in the manufacturing process and are not intended to provide general information about the manufacturing process, but are merely illustrative of the nature and cause of problems caused by the inclusion of monitor units 160 on wafer 106.

As shown in the stage of fig. 4A, most of the structure of the memory unit 110 and the monitor unit 160 has been completed: the floating gate 126 is completed with the gate dielectric and tunnel oxide layers 122, 134. In the memory cell 110, the control, select, and erase gates 121, 128, 130 are substantially completed with a hard mask cap 170 on top. On the processor side, a dielectric layer 172 is deposited, which will be patterned to form the gate dielectric of the logic transistor 108. The dummy polysilicon gate material 174 and hard mask layer 176 that have deposited and patterned the logic transistor control gates-the dummy polysilicon material will be replaced at a later stage. To this end, the monitor unit 160 is substantially identical to the flash memory cells 110 of the memory array 102. However, as shown in FIG. 4A, a hole 162 is formed in the monitor cell 160 during an element etch process in the formation of the processor 104, the hole extending through the control gate 121a and the intervening dielectric layer 148a to expose a portion of the upper surface of the floating gate 126.

Continuing at the stage shown in fig. 4B, spacers 178 are formed and dielectric layer 172 is patterned to form gate dielectric 122 of logic transistor 108, and control gate 120 of the logic transistor is substantially completed. Memory cell 110 and the drain region 116 of the logic transistor are implanted, as well as the source region 118 of the logic transistor. Nickel is deposited and nickel suicide contacts 124 are formed on exposed surfaces of the memory cells 110 and the drain regions 116 of the logic transistors 108 and the source regions 118 of the logic transistors 108. In the same process, silicide contacts 124a are formed on the exposed portions of the floating gates 126a of the monitor cells 160 within the holes 162. It is noted that silicide deposits 124b are also formed on the surfaces of the control gate 121a, which are exposed by the etching process used to access the floating gate 126 a. However, these remain isolated from the silicide contacts 124a and the floating gates 126a by the dielectric 148 a.

Turning now to fig. 4C, a Contact Etch Stop Layer (CESL)180 is formed over the features and an interlayer dielectric (ILD)182 is deposited over the wafer 106. A chemical/mechanical polishing (CMP) process is then performed, removing the hard mask caps 170, 176 and exposing the surfaces of the control, select, and erase gates 120, 121, 128, 130, and bringing all features to a common height on the wafer 106. This creates a surface suitable for subsequent processing steps. The dummy gate material 174 is removed and replaced with metal to form the control gate 120 of the logic transistor 108. A mask is deposited and patterned and silicide contacts 135 are formed on the exposed upper surfaces of the select and erase gates 128, 130 of the control gate 121, the dummy polysilicon walls 137 and the strips (not shown in fig. 4C).

It can be seen that in fig. 4C, when a CMP process is performed, the process removes a small portion of the control gate 121. The inventors have first recognized that the exposed portion of the control gate 121a of the monitor cell 160 may form the silicide deposit 124b when the hole 162 is formed, and second recognized that when the CMP process reaches and removes a portion of the control gate 121a, the portion of the silicide deposit 124b formed thereon must also be removed. This can lead to silicide contamination of the surface of the wafer 106, with some unexpected consequences. For example, the polishing process may carry tiny silicide particles and distribute them over the polished surface of the wafer 106. These silicide particles are conductive and thus can affect the conductivity or resistivity of the material with which they are in contact, or create parasitic capacitance. Additionally, as the manufacturing process proceeds, the silicide may chemically react with other materials and chemicals, producing other undesirable products and byproducts. Detection of silicide contamination is difficult and expensive and impractical for the production process. However, in many cases, if contaminating silicide particles are not detected before the wafer moves to the next step in the process, the defects caused by the contamination will result in the ultimate rejection of the contaminated chips. This can become very expensive if a large proportion of the chips on the wafer are found to be contaminated.

The likelihood of silicide contamination may be reduced or eliminated according to embodiments of the present disclosure. As with the steps of making the monitor cell 160, embodiments for reducing or eliminating the risk of silicide contamination according to the present invention can be implemented using standard manufacturing processes without the need for additional process steps.

Fig. 5A-5D are schematic side cross-sectional views of a wafer 200 at respective stages of a fabrication process, according to one embodiment. The wafer 200 includes a plurality of devices 100 that are substantially identical to the devices 100 described above with reference to fig. 1-4C and are made by the same manufacturing process. The wafer 200 also includes a monitor cell 210 formed in the PCM test keys 152 of the wafer 106 according to embodiments of the present disclosure.

Fig. 5A shows wafer 200 at a stage of manufacture subsequent to processing in the stage shown in fig. 4A, while the stages shown in fig. 5B and 5C correspond approximately to the stages shown in fig. 4B and 4C, respectively. Fig. 5D shows the monitor unit 210 at a stage corresponding to the stage of manufacture shown in fig. 1. In addition to the processing completed by the stage shown in fig. 4A, in fig. 5A, spacers 178 are also formed and dielectric layer 172 is patterned to form gate dielectric 122 of logic cell 108 and to implant source and drain regions 116, 118. As shown in fig. 5A, there is still a Silicide Prevention Layer (SPL) 212. In this example, the SPL 212 is a portion of a photoresist protective oxide (RPO) layer that is deposited and patterned concurrently with the formation of other RPO layers as part of the fabrication process of the device 100, and is modified to cover the monitor cell 210 and patterned to provide a window 214 through which a portion of the floating gate 126a may be exposed.

As shown in fig. 5B, after deposition of SPL 212, nickel is deposited and silicide contacts 124 are formed substantially as previously described, including forming silicide contacts 124a in windows 214 of SPL 212, according to the described embodiment of the invention. In contrast to the monitor cell 160 previously described with respect to fig. 4A-4C, the SPL 212 seals the exposed surface of the control gate 121a and blocks any silicide formation on the control gate without interfering with the formation of the silicide contact 124A on the floating gate 126 a. The exemplary process then proceeds to the stage shown in fig. 5C, where CESL 180 is formed on the features and ILD 182 is deposited on wafer 200. A chemical/mechanical polishing (CMP) process is performed as described above, but since silicide deposition has been prevented from being formed on the control gate 121a as described above, silicide is not exposed by the CMP process and silicide contamination is reduced or prevented.

Figure 5D shows a portion of wafer 200 housing monitor unit 210 at a stage of manufacture corresponding to that shown in figure 1. At the stage shown, ILD 138 is deposited (i.e., in combination with ILD 182 described above in the process), vias 140 are formed, and first metal layer 144 is deposited and patterned to form electrical traces 142 and connectors 146.

Referring to the monitor 160 or the aperture 162 of the cell 210, for example, as shown in fig. 4A and 5A, it can be seen that the walls of the aperture are angled relative to the plane defined by the wafer substrate 106. Depending on the type of etch used to form the holes, the walls may be sloped, as shown in previous figures, or may be at a shallower angle or closer to perpendicular relative to the substrate. Fig. 6 shows a schematic side view of a monitor unit 220 as an alternative structure to the monitor unit 160 of fig. 1-4C, which is made using an alternative process to that described with reference to fig. 4A-4C. In particular, the view of FIG. 6 corresponds to the stage of fabrication shown in FIG. 4B and illustrates structural differences from the alternative process.

In an alternative process for making the monitor cell 220 in fig. 6, the monitor cell 220 includes a hole 222 extending through the control gate 121a and the underlying dielectric 148a to the floating gate 126 a. The process for forming the holes 222 results in sidewalls that are substantially perpendicular to the plane defined by the wafer substrate 106. As a result, in a subsequent process step of forming spacers 178, spacers 178a are formed inside hole 222 to cover the exposed vertical faces of control gate 121 a. However, the same process that forms spacers 178 etches back hard mask 170a covering the remainder of control gate 121a, exposing a small portion of the upper surface of control gate 121 a. Thus, when forming silicide contacts 124, silicide deposits 124c are formed on small exposed portions of the upper surface of control gate 121a, presenting the same potential for silicide contamination as previously described with reference to monitor cell 160.

Fig. 7 is a schematic side view of a monitor unit 230 according to one embodiment, as an alternative to the monitor unit 200 of fig. 5A-5C. The monitor unit 230 includes apertures 222 that are made using the same alternative process as the apertures 222 that form the monitor unit 220, as described with reference to fig. 6. The view of fig. 7 corresponds to the stage of manufacture shown in fig. 5B and illustrates the formation of spacers 178a substantially as described with reference to monitor cell 220 of fig. 6. In the embodiment of fig. 7, SPL 212 is deposited on monitor unit 230 to seal the exposed portion of control gate 121a and patterned to define window 214, substantially as described with reference to fig. 5A. After the formation and patterning of the SPL 212, silicide contacts 124a are formed on the exposed surfaces of the floating gates 126a within the windows 214. The fabrication process continues as described above with respect to fig. 5C, with the benefit of reducing or preventing silicide contamination.

Fig. 8 is a flow diagram illustrating a method 300 of manufacturing consistent with the process described above with reference to fig. 5A-5D and 7, according to an embodiment. It should be understood that although the process steps of method 300 are shown in a sequence, they are not necessarily performed in the order shown, and in fact, many of the steps may be or may be performed concurrently. For example, in step 302, a plurality of chips are defined on a semiconductor material substrate. In fact, the specifically defined chips may not be discernable on the wafer prior to defining the scribe lines, which may occur during or after many other processes are performed. Accordingly, the order of operations is not limited to the order shown, except as provided in the language or description.

Proceeding to steps 304 and 306, a microprocessor is formed for each chip and an embedded memory is formed for each microprocessor. In step 308-318, a monitor cell is also formed. In step 310, the floating gates, control gates, and corresponding dielectric layers of the monitor cells are formed concurrently with the formation of the floating gates, control gates, and corresponding dielectric layers of the memory cells of each embedded memory array.

In step 312-318, electrical connections are made to the floating gates of the monitor cells. In step 314, holes are formed to extend through the control gates of the monitor cells to the floating gates. Then in step 316, an SPL is formed on the portion of the control gate of the monitor cell exposed by forming a hole, wherein a window is formed in the SPL above the floating gate. Finally, in step 318, silicide contact terminals are formed on the floating gates of the monitor cells in the window of the SPL.

The embodiments shown and described herein provide improvements to the monitor cells formed to provide a means for testing the quality and specific characteristics of the dielectric layer separating the floating gate of each memory cell from the surrounding structures, particularly the channel region and erase gate in use. The improvement comprises forming a Silicide Prevention Layer (SPL) within a hole formed to provide electrical access to a floating gate of the monitor cell. In particular, SPL is beneficial if materials susceptible to forming silicide are exposed during formation of the holes and may be subsequently subjected to a CMP process in which such silicide contaminates the surface of the semiconductor wafer resulting in expensive defect formation. According to embodiments of the present disclosure, the SPL is formed simultaneously with the fabrication process used to form other devices on the wafer. Using SPLs according to the described embodiments of the invention can reduce and/or prevent potentially expensive semiconductor wafer contamination during production.

In the above-described embodiments, the monitor unit is formed in the scribe line of the wafer while the memory array is formed on each of the plurality of microchips of the wafer. According to another embodiment, the monitor units are formed on individual microchips so that testing can be performed before or after dicing the wafer into individual chips. According to yet another embodiment, a memory cell of a memory array is modified by forming a connector with a floating gate to create a monitor cell within the memory array.

The structures shown and described above are provided as examples only; there are many different configurations of memory cells employing floating gates, including flash memory, EPROM, EEPROM, etc., as well as other floating gate MOSFET devices, many of which can benefit from the principles of this disclosure, including forming corresponding monitor cells and providing protection against silicide contamination.

In the illustrated embodiment of the invention, the memory cells are configured such that electrons are transferred through the first dielectric layer (122) onto the floating gate of each memory cell and are removed through the second dielectric layer (134). In other embodiments, electrons enter and exit the floating gate through the same dielectric layer.

In some structures, forming the hole to access the floating gate may expose a different gate, element, or structure of material that may form silicide, thus creating a risk of silicide contamination. The formation of SPLs according to the disclosed embodiments, including according to the described embodiments, may find use in these other structures.

The term floating gate refers to a permanently electrically isolated transistor gate structure, i.e., it has no direct electrical connection to circuitry and is configured to interact with the control gate and the channel region. However, where the term floating gate is used, referring to an element of the monitor unit in the present specification and claims, it is also applicable to a gate structure configured to be electrically connected to a circuit, but which is fabricated simultaneously with the floating gate of at least one transistor structure formed on the same semiconductor wafer.

Ordinal numbers such as first, second, third, etc. are used in the claims in accordance with conventional claim practice, i.e., to clearly distinguish between claimed elements or features thereof. Ordinals can be assigned arbitrarily, or simply in the order in which the elements are introduced. The use of such numbers does not indicate any other relationship, such as order of operation, relative position of elements, etc. Furthermore, ordinal numbers used to refer to elements in the claims should not be assumed to relate to numbers in the specification used to refer to elements of the disclosed embodiments as read by the claims, nor should they be assumed to relate to elements or features that are similar to the numerical representations used in the independent claims.

According to one embodiment, a plurality of chips are defined on a semiconductor material wafer, such as by forming scribe lines on the semiconductor material wafer. A microprocessor device includes embedded flash memory formed on each of the microchips. Monitor cells are formed on the wafer, wherein many elements of the monitor cells are formed simultaneously with corresponding elements of memory cells of the memory array, including floating gates, control gates, and corresponding dielectric layers. Forming a hole in the monitor cell to extend through the control gate to expose a portion of the floating gate. A silicide protection layer is then formed on the portion of the control gate exposed by the process of forming the hole. After forming the silicide protection layer, forming a silicide contact terminal on a portion of the floating gate exposed by the forming of the hole while the silicide protection layer prevents silicide from being formed on the control gate.

In accordance with another embodiment, a method is provided that includes forming a plurality of memory cells on a wafer of semiconductor material. This includes forming a first dielectric layer for each of the plurality of memory cells adjacent a channel region, forming a floating gate on a side of the first dielectric layer opposite the channel region, and forming a control gate adjacent the floating gate and isolated therefrom by a second dielectric layer.

The method also includes monitoring cells on the semiconductor material wafer including forming a first dielectric layer of the monitoring cells concurrently with the forming of the first dielectric layer of each of the plurality of memory cells, forming a floating gate of the monitoring cells concurrently with the forming of the floating gates of the plurality of memory cells, and forming a control gate of the monitoring cells concurrently with the forming of the control gates of the plurality of memory cells. A hole is then formed that extends through the control gate and the intervening dielectric layer of the monitor cell to expose a portion of the floating gate of the monitor cell. A silicide protection layer is then formed to cover any portion of the control gate exposed by the process of forming the hole. After forming the silicide protection layer, a silicide contact terminal is formed on the exposed portion of the floating gate.

In accordance with yet another embodiment, a method is provided wherein a plurality of substantially identical memory cells are formed on a semiconductor wafer. A monitor unit is also formed by exposing a portion of the floating gate of one of the plurality of memory cells by forming a hole in the one of the plurality of memory cells that extends to the floating gate. Finally, a silicide contact terminal is formed on the exposed portion of the floating gate. When another material is exposed by the forming of the hole and the exposed material is susceptible to forming a silicide, then a silicide prevention layer is formed on the exposed material except on the exposed portion of the floating gate before forming a silicide contact terminal on the exposed portion of the floating gate.

According to some embodiments, there is provided a method of forming a semiconductor device, comprising: defining a plurality of chips on a wafer of semiconductor material; forming a respective one of a plurality of microprocessor devices on each of the chips defined on the semiconductor material wafer, each of the microprocessor devices including an embedded memory; forming a monitor unit on the wafer of semiconductor material, comprising: forming a floating gate, a control gate and a corresponding dielectric layer; forming a hole extending through a control gate of the monitor cell and exposing a portion of a floating gate of the monitor cell; forming a silicide protection layer on a portion of a control gate of the monitor cell, the portion of the control gate being exposed by forming the hole; and forming a silicide contact terminal on a portion of a floating gate of the monitor cell, the portion of the floating gate being exposed by forming the hole, after the forming of the silicide protection layer.

In the above method, wherein forming the silicide protection layer comprises forming the silicide protection layer while performing processing steps associated with forming the plurality of microprocessor devices.

In the above method, comprising: after forming the silicide contact terminals, chemical mechanical polishing of the semiconductor material wafer is performed and a portion of the control gates of the monitor cells are exposed.

In the above method, comprising, after performing chemical mechanical polishing of the semiconductor material wafer: depositing an interlevel dielectric layer on the semiconductor material wafer; forming a metal layer on the interlayer dielectric layer; and forming an electrical connector between the electrical trace of the metal layer and the silicide contact terminal.

In the above method, wherein forming a monitor unit on the wafer of semiconductor material comprises forming a monitor unit on a portion of the wafer of semiconductor material that is not defined as part of one of the plurality of chips.

In the above method, wherein forming a monitor unit on the semiconductor material wafer comprises forming a monitor unit on each of the chips, each of the chips being defined on the semiconductor material wafer.

In the above method, wherein forming the floating gate, the control gate and the corresponding dielectric layer of the monitor cell comprises: forming a same first tunneling dielectric layer of the monitor cell and a memory cell of each embedded memory; forming the same floating gate of the monitor cell and a memory cell of each embedded memory; and a memory unit forming the same control gate of the monitor unit and each embedded memory.

In the above method, wherein forming the floating gate, the control gate and the corresponding dielectric layer of the monitor cell comprises: the same second tunneling dielectric layer of the monitor cell and the memory cell of each embedded memory are formed between the respective floating gate and the corresponding erase gate.

In the above method, wherein said forming a silicide protection layer comprises forming a silicide protection layer while performing processing steps associated with forming a plurality of microprocessor devices on said wafer of semiconductor material.

In the above method, wherein forming the silicide protection layer comprises forming a photoresist protection oxide layer.

In the above method, wherein forming a monitor unit on the wafer of semiconductor material comprises forming a monitor unit on a portion of the wafer of semiconductor material that is external to any defined plurality of chips.

In the above method, wherein forming monitor cells on the wafer of semiconductor material comprises forming monitor cells on scribe lines of the wafer of semiconductor material.

According to another embodiment, there is provided a method of forming a semiconductor device, including: forming a plurality of identical memory cells on a wafer of semiconductor material; forming a monitor cell including exposing a portion of a floating gate of one of the plurality of memory cells by forming a hole in a portion of the one of the plurality of memory cells; forming a silicide contact terminal on the exposed portion of the floating gate; and forming a silicide prevention layer on the exposed material in addition to the exposed portion of the floating gate before forming a silicide contact terminal on the exposed portion of the floating gate when the material is exposed by forming the hole and the exposed material is susceptible to forming a silicide.

In the above method, wherein forming the monitor cell comprises forming one of the plurality of memory cells in a scribe line of the wafer of semiconductor material.

In the above method, wherein: forming a hole in a portion of one of the plurality of memory cells includes forming a hole in a control gate of one of the plurality of memory cells; and forming a silicide-prevention layer on the exposed material includes forming a silicide-prevention layer on a portion of the control gate exposed by the formation of the hole in the control gate of one of the plurality of memory cells.

According to still another embodiment, there is provided a semiconductor device including: a wafer of semiconductor material; a plurality of chips defined on the semiconductor material wafer; a memory array formed on each of the plurality of chips; and a monitor unit formed on the semiconductor material wafer and having: a floating gate that is identical to a floating gate of a memory cell of the memory array formed on each of the plurality of chips, a first tunneling dielectric layer that is identical to a corresponding tunneling dielectric layer of a memory cell of the memory array formed on each of the plurality of chips, a silicide contact terminal formed on the floating gate, an electrical connector extending through a hole formed in a control gate of the monitor cell, and a silicide protection layer in contact with the control gate within the hole.

In the above semiconductor device, wherein the silicide protection layer is a photoresist protection oxide.

In the above semiconductor device, a microelectronic device defined on each of the chips and an embedded memory including the memory array are included.

In the above semiconductor device, wherein the monitor unit is formed on a scribe line between a pair of chips.

In the above semiconductor device, wherein the monitor unit is one of a plurality of monitor units formed on the semiconductor material wafer.

Although the method and process steps recited in the claims may be presented in an order corresponding to the order of steps disclosed and described in the specification, the order in which the steps are presented in the specification or claims is not limited to the order in which the steps may be performed unless specifically indicated.

The abstract of the invention provides a brief summary of some principles of the invention according to one embodiment, and is not intended as a complete or definitive description of any embodiment thereof, nor should it be relied upon to define terms used in the specification or claims. The abstract does not limit the scope of the claims.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.