Semiconductor device including distributed write drive arrangement and method of operating the same
阅读说明:本技术 包括分布式写入驱动布置的半导体器件及其操作方法 (Semiconductor device including distributed write drive arrangement and method of operating the same ) 是由 藤原英弘 廖宏仁 王俐文 张琮永 陈炎辉 于 2019-07-15 设计创作,主要内容包括:根据本申请的实施例,一种半导体存储器器件包括:本地写入位(LWB)线;本地写入位_bar(LWB_bar)线;全局写入位(GWB)线;全局写入位_bar(GWBL_bar)线;区段列,每区段包括位单元;位单元的每个包括锁存电路和将对应的LWB和LWB_bar线连接到锁存电路的第一通路栅极和第二通路栅极;以及分布式写入驱动布置。分布式写入驱动布置包括:全局写入驱动器,包括在GWB线和LWB线之间连接的第一反相器、以及在GWB_bar线和LWB_bar线之间连接的第二反相器;以及包括在每个区段的内部处的本地写入驱动器,每个本地写入驱动器包括在GWB线和LWB线之间连接的第三反相器;以及在GWB_bar线和LWB_bar线之间连接的第四反相器。本申请的实施例提供了半导体存储器器件和在分布式基础上在SRAM宏中写入-驱动列的方法。(According to an embodiment of the present application, a semiconductor memory device includes: a Local Write Bit (LWB) line; a local write bit _ bar (LWB _ bar) line; a Global Write Bit (GWB) line; a global write bit _ bar (GWBL _ bar) line; a sector column, each sector comprising a bit cell; each of the bit cells includes a latch circuit and first and second pass gates connecting corresponding LWB and LWB _ bar lines to the latch circuit; and a distributed write drive arrangement. The distributed write drive arrangement includes: a global write driver including a first inverter connected between a GWB line and an LWB line, and a second inverter connected between a GWB _ bar line and an LWB _ bar line; and a local write driver included at an interior of each sector, each local write driver including a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB _ bar line and the LWB _ bar line. Embodiments of the present application provide a semiconductor memory device and a method of writing-driving columns in an SRAM macro on a distributed basis.)
1. A semiconductor memory device, comprising:
a Local Write Bit (LWB) line;
a local write bit _ bar (LWB _ bar) line;
a Global Write Bit (GWB) line;
a global write bit _ bar (GWBL _ bar) line;
a column of sectors, each sector comprising a bit cell;
each of the bit cells includes a latch circuit and first and second pass gates connecting the corresponding LWB and LWB _ bar lines to the latch circuit; and
the distributed write driver arrangement includes a global write driver and a local write driver:
the global write driver includes:
a first inverter connected between the GWB line and the LWB line; and
a second inverter connected between the GWB _ bar line and the LWB _ bar line; and
the local write drivers contained in each sector, each local write driver located inside the corresponding sector, each local write driver comprising:
a third inverter connected between the GWB line and the LWB line; and
a fourth inverter connected between the GWB _ bar line and the LWB _ bar line.
2. The semiconductor memory device of claim 1, wherein:
the first inverter is connected between the GWB line and the LWB line by a connection between corresponding first and second nodes;
the second inverter is connected between the GWB _ bar lines by a connection between the corresponding third and fourth nodes; and
the global write driver further comprises:
a first equalizer circuit connected between the LWB line and the LWB _ bar line and configured to be controlled by signals on the corresponding first and third nodes.
3. The semiconductor memory device of claim 2, wherein:
the first equalizer circuit of the global write driver includes:
a first transistor and a second transistor connected in series between the LWB line and the LWB _ bar line; and
the first node and the third node are connected to corresponding gate electrodes of the first transistor and the second transistor.
4. The semiconductor memory device of claim 2, wherein:
the first equalizer circuit of the global write driver includes:
a transistor connected in series between the LWB line and the LWB _ bar line; and
a logic circuit connected between a gate electrode of the transistor and each of the first node and the second node.
5. The semiconductor memory device of claim 2, wherein:
the logic circuit is configured to apply a logical OR function to signals on the corresponding first and third nodes.
6. The semiconductor memory device of claim 2, wherein:
the first equalizer circuit of the global write driver is configured to turn off reactions to signals on the corresponding first and third nodes having different logic states.
7. The semiconductor memory device of claim 2, wherein:
the third inverter is connected between the GWB line and the LWB line by being connected between corresponding fifth and sixth nodes;
the fourth inverter is connected between the GWB _ bar line and the LWB line by being connected between corresponding seventh and eighth nodes; and
the local write driver further comprises:
a second equalizer circuit connected between the LWB line and the LWB _ bar line and configured to be controlled by signals on the corresponding fifth and seventh nodes.
8. The semiconductor memory device of claim 7, wherein:
the second equalizer circuit of each local write driver includes:
a first transistor and a second transistor connected in series between the LWB line and the LWB _ bar line; and
signals on the fifth node and the seventh node are connected to corresponding gate electrodes of the first transistor and the second transistor.
9. A semiconductor memory device, comprising:
a column of sectors, each sector comprising a bit cell;
a Local Write Bit (LWB) line;
a local write bit _ bar (LWB _ bar) line;
a Global Write Bit (GWB) line;
a global write bit _ bar (GWBL _ bar) line;
each of the bit cells comprises:
a latch circuit; and
connecting the corresponding LWB line and LWB _ bar line to a first pass gate and a second pass gate of the latch circuit; and
the distributed write drive arrangement includes:
a global write driver connected between the GWB line and the LWB line and between the GWB _ bar line and the LWB _ bar line;
local write drivers included in each sector, each local write driver connected between the GWB line and the LWB line and between the GWB _ bar line and the LWB _ bar line; and
wherein:
each local write driver is located in the first device layer; and
the global write driver is located in a second device layer above the first device layer.
10. A method of writing-driving columns in an SRAM macro on a distributed basis, the columns including a Global Write Bit (GWB) line, a global write bit _ bar (GWBL _ bar) line, a Local Write Bit (LWB) line, a local write bit _ bar (LWB _ bar) line, a bit cell, and at least one local write driver,
each of the bit cells includes a latch circuit and first and second pass gates connecting the corresponding LWB and LWB _ bar lines,
the global write driver includes a first inverter connected between the GWB line and the LWB line and a second inverter connected between the GWB _ bar line and the LWB _ bar line, and
the local write driver includes a third inverter connected between the GWB line and the LWB line and a fourth inverter connected between the GWB _ bar line and the LWB _ bar line, and
the local write driver is located inside the column;
the method comprises the following steps:
driving the GWB line with a first signal having a first logic value;
driving the GWB _ bar line with a second signal having the first logical value or a second logical value opposite the first logical value;
inverting the first signal with each of the first inverter in the global write driver and the third inverter in the local write driver to form a first _ bar signal having the second logic value;
inverting the second signal with each of the second inverter in the global write driver and the fourth inverter in the local write driver to form a second _ bar signal having an opposite logic value than the second signal;
driving the LWB line with the first _ bar signal to provide the first _ bar signal to the first pass-gate of each of the bit cells; and
driving an LWB _ bar line with the second _ bar signal to provide the second _ bar signal to the second pass-gate of each of the bit cells.
Technical Field
Embodiments of the present application relate to the field of semiconductors, and more particularly, to a semiconductor device including a distributed write drive arrangement and a method of operating the same.
Background
In a typical memory system, memory cells are arranged in an array. Each memory cell (also referred to as a cell) stores data representing one bit. Each cell is located at an intersection of a row and a column. Thus, a particular cell is accessed by selecting the row and column that intersect at the particular cell. Each cell in a column is connected to a bit line. Input/output (I/O) circuitry reads data from or writes data to a selected one of the bitcells in the column using the bitline.
Typically, there are many cells in a column. Due to the variation in physical distance between the I/O circuitry and the cells, the bit lines represent different resistive and/or capacitive loads for each cell in the column.
Disclosure of Invention
According to an embodiment of the present application, there is provided a semiconductor memory device including: a Local Write Bit (LWB) line; a local write bit _ bar (LWB _ bar) line; a Global Write Bit (GWB) line; a global write bit _ bar (GWBL _ bar) line; a column of sectors, each sector comprising a bit cell; each of the bit cells includes a latch circuit and first and second pass gates connecting the corresponding LWB and LWB _ bar lines to the latch circuit; and the distributed write driver arrangement includes a global write driver and a local write driver: the global write driver includes: a first inverter connected between the GWB line and the LWB line; and a second inverter connected between the GWB _ bar line and the LWB _ bar line; and the local write drivers contained in each sector, each local write driver located inside the corresponding sector, each local write driver comprising: a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB _ bar line and the LWB _ bar line.
According to an embodiment of the present application, there is provided a semiconductor memory device including: a column of sectors, each sector comprising a bit cell; a Local Write Bit (LWB) line; a local write bit _ bar (LWB _ bar) line; a Global Write Bit (GWB) line; a global write bit _ bar (GWBL _ bar) line; each of the bit cells comprises: a latch circuit; and connecting the corresponding LWB line and LWB _ bar line to a first pass gate and a second pass gate of the latch circuit; and the distributed write drive arrangement comprises: a global write driver connected between the GWB line and the LWB line and between the GWB _ bar line and the LWB _ bar line; local write drivers included in each sector, each local write driver connected between the GWB line and the LWB line and between the GWB _ bar line and the LWB _ bar line; and wherein: each local write driver is located in the first device layer; and the global write driver is located in a second device layer above the first device layer.
In accordance with an embodiment of the present application, there is provided a method of writing-driving columns in an SRAM macro on a distributed basis, the columns including a Global Write Bit (GWB) line, a global write bit _ bar (GWBL _ bar) line, a Local Write Bit (LWB) line, a local write bit _ bar (LWB _ bar) line, bit cells, and at least one local write driver, each of the bit cells including a latch circuit and first and second pass gates connecting the corresponding LWB and LWB _ bar lines, the global write driver including a first inverter connected between the GWB and LWB lines and a second inverter connected between the GWB and LWB _ bar lines, and the local write driver including a third inverter connected between the GWB and LWB lines and a fourth inverter connected between the GWB and LWB _ bar lines, and the local write driver is located inside the column; the method comprises the following steps: driving the GWB line with a first signal having a first logic value; driving the GWB _ bar line with a second signal having the first logical value or a second logical value opposite the first logical value; inverting the first signal with each of the first inverter in the global write driver and the third inverter in the local write driver to form a first _ bar signal having the second logic value; inverting the second signal with each of the second inverter in the global write driver and the fourth inverter in the local write driver to form a second _ bar signal having an opposite logic value than the second signal; driving the LWB line with the first _ bar signal to provide the first _ bar signal to the first pass-gate of each of the bit cells; and driving an LWB _ bar line with the second _ bar signal to provide the second _ bar signal to the second pass-gate of each of the bit cells.
Drawings
One or more embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which elements having the same reference numerals refer to similar elements throughout the description. Unless otherwise disclosed, the drawings are not drawn to scale.
Fig. 1 is a block diagram of a semiconductor device according to some embodiments.
Fig. 2 is a block diagram of an array and column drive regions including a distributed write drive arrangement in accordance with at least one embodiment of the present disclosure.
Fig. 3 is a circuit diagram of an array and column drive regions including a distributed write drive arrangement in accordance with at least one embodiment of the present disclosure.
Fig. 4A-4C are corresponding circuit diagrams of an array and column drive regions including a distributed write drive arrangement in accordance with at least one embodiment of the present disclosure.
Fig. 5A-5C are corresponding circuit diagrams of an array and column drive regions each comprising a distributed write drive arrangement, according to corresponding embodiments of the present disclosure.
Fig. 6 is a cross section of an array and
FIG. 7 is a flow diagram of a
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, etc. are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms, such as "below," "lower," "over," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative positional terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In some embodiments, a distributed write drive arrangement is provided for SRAM bit cells that include separate write and read ports. More specifically, this distributed write drive arrangement includes: a global write driver; and, in each bitcell sector, a driver is written locally. The global write driver includes: a first inverter connected between a Global Write Bit (GWB) line and a Local Write Bit (LWB) line; and a second inverter connected between the global write bit _ bar (GWB _ bar) line and the local write bit _ bar (LWB _ bar) line. Each local write driver includes: a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB _ bar line and the LWB _ bar line. In some embodiments, a distributed write drive arrangement including each local write driver in a corresponding sector of a bit cell has the advantage of mitigating issues of resistive and/or capacitive loading of the LWB and LWB _ bar lines. In some embodiments, each local write driver is in a first device layer and the global write driver is in a second device layer above the first device layer, which gives the advantage that the global write driver is easier to configure for high speed and large footprint than if the global write driver were in the first device layer.
Fig. 1 is a block diagram of a
In fig. 1, a
Fig. 2 is a block diagram of an array and column drive region 200 including a distributed write drive arrangement in accordance with at least one embodiment of the present disclosure. Region 200 of fig. 2 is an example of
In FIG. 2, the area 200 is organized into columns, where columns 207(j) through 207(j + n) are shown in FIG. 2, where j and n are integers and j ≧ 0, n ≧ 1, and j denotes a column number. Region 200 includes section 202A and section 202B, global drive (g-drv) block 204; and a control block 206.
Section 202A includes: a block 210A; segment-drive (s-drv) block 218A; and block 214A. Section 202B includes: a block 210B; an s-drv block 218B; and block 214B.
Block 210A is organized as a two-dimensional array of rows and columns that includes bitcell 212A (i, j) to bitcell 212A (i + m, j + n), where i and m are integers, i ≧ 0, m ≧ 1, and i denotes a row number. Bitcells, such as bitcell 212A (i, j), are shown in more detail in fig. 3 (discussed below). For example, bitcell 212A (i, j) to bitcell 212A (i + m, j) is in column 207 (j). Block 214A is organized as a two-dimensional array including bit cell 216A (i, j) to bit cell 216A (i + m, j + n). Block 210B is organized as a two-dimensional array including bit cell 212B (i, j) to bit cell 212B (i + m, j + n). Block 214B is organized as a two-dimensional array including bit cell 216B (i, j) to bit cell 216B (i + m, j + n).
The S-drv block 218A includes local write drivers 220A (j) to local write drivers 220A (j + n) referred to as sector-column (S-col) drivers 220A (j) to S-col drivers 220A (j + n). An S-col drive, such as S-col drive 220A (j), is shown in more detail in FIG. 3 (discussed below). For example, s-col driver 220A (j) is in column 207 (j). S-drv block 218B includes local write drivers 220B (j) to local write drivers 220B (j + n), referred to as S-col drivers 220B (j) to S-col drivers 220B (j + n).
The global drive (g-drv) block 204 includes global write drivers 224(j) through global write drivers 224(j + n) referred to as global-column (g-col) drivers 224(j) through g-col drivers 224(j + n). A G-col driver, such as G-col driver 224(j), is shown in more detail in FIG. 3 (discussed below). For example, g-col driver 224(j) is in column 207 (j).
In FIG. 2, the region 200 is considered to have a distributed write drive arrangement because the region 200 includes a global drive (g-drv) block 204 and s-drv blocks 218A through 218B (the latter included in sections 202A through 202B, respectively).
The control block 206 includes column drive (c-drv) control units 226(j) to 226(j + n) of the c-drv control unit. A control unit, such as c-drv control unit 226(j), is shown in more detail in FIG. 3 (discussed below). For example, c-drv control unit 226(j) is in column 207 (j). The C-drv control units 226(j) through 226(j + n) provide corresponding write-control signals (see fig. 3 discussed below).
The area 200 further includes: global Write Bit (GWB) lines 230(j) to GWB lines 230(j + n); a corresponding global write bit _ bar (GWB _ bar) line (not shown, but see fig. 3 discussed below); local Write Bit (LWB) lines 234(j) to LWB lines 234(j + n); and a corresponding local write bit _ bar (LWB _ bar) line (not shown, but see fig. 3 discussed below).
In region 200 of FIG. 2, GWB line 230(j) is connected to each of s-col driver 220A (j), s-col driver 220B (j), and g-col driver 224 (j). GWB line 230(j + n) is connected to each of s-col driver 220A (j + n), s-col driver 220B (j + n), and g-col driver 224(j + n), etc. LWB line 234(j) is connected to each of bitcell 212A (i, j) through bitcell 212A (i + m, j), s-col driver 220A (j), bitcell 216A (i, j) through bitcell 216A (i + m, j), bitcell 212B (i, j) through bitcell 212B (i + m, j), s-col driver 220B (j), bitcell 216B (i, j) through bitcell 216B (i + m, j), and g-col driver 224 (j). LWB line 234(j + n) is connected to each of bitcells 212A (i, j + n) through 212A (i + m, j + n), s-col driver 220A (j + n), bitcells 216A (i, j + n) through 216A (i + m, j + n), bitcells 212B (i, j + n) through 212B (i + m, j + n), s-col driver 220B (j + n), bitcells 216B (i, j + n) through 216B (i + m, j + n), and g-col driver 224(j + n), among others.
For simplicity of illustration, the area 200 of FIG. 2 is shown with two sections 202A-202B. In some embodiments, additional sections are included in region 200. Likewise, for simplicity of illustration, each of the sections 202A-202B has been shown with one s-drv block, i.e., the corresponding s-drv block 218A-218B, such that the intra-segment ratio of the cell block (bcell) to the s-drv block (bsdrv) is bcell: bsdrv ═ 2: 1. other ratios are within the scope of the present disclosure. In some embodiments, the intra-segment ratio, bcell: bsdrv has the exception of bcell: bsdrv ═ 2: values other than 1.
Fig. 3 is a circuit diagram 300 including an array of distributed write drive arrangements and column drive regions in accordance with at least one embodiment of the present disclosure.
The circuit diagram 300 is an example implementation of the array and column drive region 200 of fig. 2. Thus, circuit diagram 300 is an example of
While the circuit diagram 300 of figure 3 is in some respects more detailed than the block diagram of region 200 of figure 2, for example, because the circuit diagram depicts transistors, inverters, NOR gates, GWB _ bar line 322 (j); LWB _ bar line 336(j), etc., the circuit diagram also represents a simplification of the block diagram of
In FIG. 3, bitcells 312A (i, j) and 316A (i + m, j) are dual port, 8 transistor (8T) SRAM bitcells, with one port representing a write port and one port representing a read port. Other bitcell configurations are within the scope of the present disclosure. In some embodiments,
In circuit diagram 300,
With particular regard to latch 311, transistor P01 and transistor N01 are connected in series between a first reference voltage and a second reference voltage. In some embodiments, the first reference voltage is VDD. In some embodiments, the second reference voltage is VSS. The source and drain electrodes of transistor P01 are connected to VDD and node 303A, respectively. The drain and source electrodes of transistor N01 are connected to nodes 303A and VSS, respectively. Transistor P02 and transistor N02 are connected in series between VDD and VSS. The source and drain electrodes of transistor P02 are connected to VDD and node _
In circuit diagram 300,
In the
In fig. 3, the g-col driver 324(j) includes:
In fig. 3, the s-col driver 320a (j) includes:
In FIG. 3, c-drv control unit 426(i) includes NOR
In the context of an array and column drive region in an SRAM device according to another approach, and more particularly in the context of a column thereof, it is noted that the other approach does not use a distributed drive arrangement but rather a merged drive arrangement. Thus, another approach does not include a local write driver in each corresponding sector of the bit cell, nor a GWB line, nor a GWB _ bar line, and has a merged driver (not shown) in place of the g-col driver 324(j) and the c-drv control unit 326 (j). The problem of resistive and/or capacitive loading of the LWB and LWB _ bar lines significantly compromises the operation of the arrangement according to another method.
For example, according to another method, during a write process where a column is selected and a sector is selected, the LWB line is precharged to a logic high value (value H). After precharging, the merged driver drives the LWB line with a value of H or a logic low value (value of L). According to another approach consider a write scenario in which the node of the latch (of the bit cell) initially stores the value H, so that the NMOS transistor connected to the node is turned off, since node _ bar stores the corresponding value L, the node of the latch (of the bit cell) is selected to be connected to the LWB line, and the merged driver attempts to drive/write the LWB line with the value L. In a write scenario according to another method, the NMOS transistor will turn on and will attempt to pull down the LWB line from the precharge value H to the value L. The resistive and/or capacitive loading of the LWB line significantly compromises the ability of the corresponding NMOS transistor to pull down the WRB line from the precharge value H to the value L in the latch of another approach.
In some embodiments, the distributed write drive arrangement of region 200 has the benefit of mitigating the problem of resistive and/or capacitive loading of LWB lines 334(j) and LWB _ bar lines 336 (j). In particular,
The circuit diagram 300 of FIG. 3 also includes a Local Read Bit (LRB) line 337(j), a section read (s-read) circuit 368(j), a global read (g-read) circuit 370(j), and a Global Read Bit (GRB) line 339 (j). Similarly, in the
With respect to c-read circuit 313, transistor N05 and transistor N06 are connected in series between Local Read Bit (LRB) line 337(j) and VSS. A first source/drain electrode and a second source/drain electrode of transistor N05 are connected to LRB line 337(j) and
In some embodiments, during a read process in which column 307(j) is selected and
Likewise, in
With respect to C-read circuit 313, a first source/drain electrode and a second source/drain electrode of transistor N11 are connected to LRB line 337(j) and node 305C. A first source/drain electrode and a second source/drain electrode of transistor N12 are connected to node 305C and VSS. Transistor N11 selectively connects LRB line 337(j) to node 305C under control of a signal on line BWRD (i + m). Transistor N12 selectively connects node 305C to VSS under the control of the logic value (L or H) stored at
Fig. 4A-4C are corresponding circuit diagrams 400A-400C including an array of distributed write drive arrangements and column drive regions, according to at least one embodiment of the present disclosure. More specifically, each of the circuit diagrams 400A-400C shows the same circuitry, albeit in a different control phase for the columns 407(j) of the array and column drive regions.
Each of the circuit diagrams 400A-400C is an example implementation of the array and column drive region 200 of fig. 2. Thus, each of the circuit diagrams 400A to 400C is an example of the
In some aspects, each of circuit diagram 400A-400C is a more detailed version of circuit diagram 300. For example, each of the circuit diagrams 400A-400C shows: an
Fig. 4A assumes a scenario in which column 407(j) is not selected. Fig. 4B assumes a scenario in which column 407(j) is selected and column 407(j) is precharged prior to a write operation. Fig. 4C assumes a scenario in which column 407(j) is selected and data is being written to column 407(j) after column 407(j) has been precharged.
With respect to fig. 4A (which again assumes a scenario in which column 407(j) is not selected), since the inclusion of NOR
With respect to g-col driver 424(j), when the output of
Likewise, with respect to g-col driver 424(j), when the output of each of
With respect to the s-col driver 420(j), when the output of
Likewise, with respect to g-col driver 420(j), when the input of
The discussion now turns to fig. 4B (which again assumes a scenario in which column 407(j) is selected and the column 407(j) is precharged prior to a write operation). In fig. 4B, the signal on line CS _ BAR is set to the value L. When the signal on line CS _ BAR is set to a value of L, the output of each of NOR
In fig. 4B, with respect to g-col driver 424(j), when the output of
The discussion now turns to fig. 4C (again assuming a scenario in which column 407(j) is selected, and in which data is written to column 407(j) after column 407(j) is precharged). It should be recalled that a bit cell, e.g., 412A (i, j) (but see 312A (i, j) in more detail), stores a pair of opposite logical values (L & H or H & L) at a corresponding pair of nodes, e.g., node 303A and
FIG. 4C is similar to FIG. 4B except that in FIG. 4C, the value on line WD is different from the value on line WD _ bar, resulting in the output of the C-drv control unit 426(i) at
More specifically, with respect to the C-drv control unit 426(i) in FIG. 4C, the signal on line CS _ BAR is set to the value L. When the signal on line CS _ BAR is set to a value of L, the output of each of NOR
With respect to the g-col driver 424(j) in FIG. 4C, when the output of
Likewise, with respect to g-col driver 424(j), when the output of
With respect to the s-col driver 420(j), when the output of
The
The circuit configuration may be described, for example, in terms of relative degrees of optimization of various parameter combinations represented by the circuit configuration. For example, the speed is a parameter indicating the operation speed of the corresponding circuit. In some embodiments, the relative degree of optimization of the speed is referred to as lower, medium, and higher, such that the corresponding circuit is configured to exhibit low, medium, or high speed, where lower < medium < higher. As another example, the coverage area is a parameter representing the area consumed/occupied by the corresponding circuit. In some embodiments, the relative degree of optimization of the coverage areas is referred to as small, medium, and large, such that the corresponding circuitry is configured to present a small coverage area, a medium coverage area, or a large coverage area, where small < medium < large.
In some embodiments, the particular relative optimization of speed and coverage area is referred to as a type.
In some embodiments, the maximum speed is a parameter representing a maximum operating speed (Max speed) of the corresponding circuit. In some embodiments, the footprint is a parameter that represents the area consumed by the corresponding circuit. In some embodiments, and as summarized in the following table (table 1),
Type (B)
Max speed
Coverage area
Type-1
Medium and high grade
Of moderate degree
Type-2
Is lower than
Is smaller
Type-3
Is higher than
Is larger
TABLE 1
In fig. 3 and 4A-4C, each of the s-col driver 320a (j), g-col driver 324(j), s-col driver 420a (j), and g-col driver 424(j) is shown to have the same internal configuration. More specifically, each of the s-
Fig. 5A-5C are corresponding circuit diagrams 500A-500C each including an array of distributed write drive arrangements and column drive regions, according to corresponding embodiments of the present disclosure.
Each of circuit diagrams 500A-500C is an example implementation of the array and column drive region 200 of fig. 2. Thus, each of the circuit diagrams 500A to 500C is an example of the
Each of the corresponding circuit diagrams 500A-500C of fig. 5A-5C is an example variation of the circuit diagrams 400A-400C of fig. 4A-4C. It should be recalled that each of the circuit diagrams 400A-400C shows the same circuit in a different control phase for the column 407(j) of the array and column drive regions. For the sake of brevity, the discussion of the
In FIG. 5A, the s-
In circuit diagram 500A, the s-
Likewise, in circuit diagram 500A, g-col driver 524 (j)' includes
Equalizer 527 operates the same as
Fig. 5B is similar in some respects to fig. 4A-4C and in some respects to fig. 5A. In fig. 5B, the s-col driver 520a (j) is the same as the s-col driver 420a (j) in fig. 4A-4C. Likewise, in FIG. 5B, the g-col drive 524(j) "'is the same as the g-col drive 524 (j)"' in FIG. 5A.
Fig. 5C is similar in some respects to fig. 4A-4C and in some respects to fig. 5A. In FIG. 5C, the s-
As for the types summarized in table 1, the combinations of the types shown in fig. 3, fig. 4A to 4C, and fig. 5A to 5C are summarized in the following table (table 2).
TABLE 2
In some embodiments, the specific relative optimizations for speed and coverage area are summarized in the following table (table 3).
TABLE 3
With respect to table 3, in fig. 3 and 4A-4C, each of the s-col driver 320a (j), g-col driver 324(j), s-col driver 420a (j), and g-col driver 424(j) is configured to substantially the same maximum speed, and each of the s-col driver 320a (j), g-col driver 324(j), s-col driver 420a (j), and g-col driver 424(j) is configured with substantially the same coverage area. In fig. 5A, the s-col driver 520a (j) 'is configured for a lower maximum speed than the g-col driver 524 (j)', and the s-col driver 520a (j) 'is configured to have a smaller coverage area than the g-col driver 524 (j)'. In fig. 5B, the s-col driver 520a (j) is configured for a lower maximum speed than the g-col driver 524(j) ", and the s-col driver 520a (j)" is configured to have a smaller coverage area than the g-col driver 524(j) "'. In fig. 5C, the s-col driver 520a (j) 'is configured for a lower maximum speed than the g-col driver 524 (j)', and the s-col driver 520a (j) 'is configured to have a smaller coverage area than the g-col driver 524 (j)'.
Fig. 6 is a cross section of an array and
Fig. 6 includes
Examples of the device included in the device layer (p)671 include: section 202A and section 202B of FIG. 2, which include corresponding s-col drivers 220A (j) through s-col driver 220(j + n) and s-col drivers 220B (j) through s-col driver 220B (j + n);
Examples of devices included in the device layer (p +1)673 include: g-col drivers 224(j) through 224(j + n) and c-drv control units 226(j) through 226(j +1) of FIG. 2; the g-col driver 324(j) and c-drv control unit 326(j) of FIG. 3; the g-col driver 424(j) and C-drv control unit 426(j) of FIGS. 4A-4C; the g-col drive 524 (j)' of FIGS. 5A-5B; g-col driver 524(j) of FIG. 5C; and C-drv control unit 526(j) of fig. 5A through 5C.
The device layer (p)671 includes
The sub-layer 675 includes a semiconductor structure (not shown), such as an active region or the like.
The sub-layer 687 includes semiconductor structures (not shown), such as active regions and the like. The
In the array and
In some embodiments, device layer (p +1)673 includes type-2 configurations of type-1 and/or type-3 but not circuitry, while layer (p)671 includes type-3 configurations of type-1 and/or type-2 but not circuitry. In some embodiments, device layer (p +1)673 includes a type-1 configuration and/or a type-2 configuration of type-3 configurations but not circuitry, while layer (p)671 includes a type-1 circuitry and/or a type-3 configuration of type-2 configurations but not circuitry. In some embodiments, device layer (p +1)673 includes a type-1 configuration but does not include a type-2 configuration and/or a type-3 configuration of circuitry, while layer (p)671 includes a type-1 configuration but does not include a type-2 configuration and/or a type-3 configuration of circuitry. Other configurations are within the scope of the present disclosure.
FIG. 7 is a flow diagram of a
According to some embodiments, the
With respect to
In fig. 7,
At
At
At
At
At
At
In some embodiments, block 714 includes: when the first signal and the second signal have different logic values, each of the first equalizer circuit and the second equalizer circuit is turned off, an example of which is shown in fig. 4C.
In some embodiments, block 714 includes: providing a first signal to gates of the first transistor and the third transistor; and supplies the second signal to the gates of the second transistor and the fourth transistor. Examples of the first to fourth transistors are the corresponding transistors P11 to P14 of fig. 4A to 4C, the gates of which are connected to the corresponding
In some embodiments, block 714 includes: logically combining the first signal and the second signal to form a third signal; and provides a third signal to the gate of the first transistor. One example of a transistor is the transistor P51 in fig. 5A. An example of logically combining the first and second signals to form the third signal is providing the signals on
In one embodiment, a semiconductor memory device includes: a Local Write Bit (LWB) line; a local write bit _ bar (LWB _ bar) line; a Global Write Bit (GWB) line; a global write bit _ bar (GWBL _ bar) line; and a sector column. Each sector includes bit cells, each bit cell including a latch circuit and first and second pass gates connecting corresponding LWB and LWB _ bar lines to the latch circuit. The device also includes a distributed write drive arrangement. The distributed write drive arrangement includes: a global write driver and a local write driver. The global write driver includes: a first inverter connected between the GWB line and the LWB line; and a second inverter connected between the GWB _ bar line and the LWB _ bar line. Local write drivers are included in each zone, each local write driver being located inside the corresponding zone, each local write driver including: a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB _ bar line and the LWB _ bar line. In some embodiments, the first inverter is connected between the GWB line and the LWB line by connecting between corresponding first and second nodes; a second inverter is connected between the GWB _ bar lines by being connected between corresponding third and fourth nodes; and the global write driver further comprises: a first equalizer circuit is connected between the LWB line and the LWB _ bar line and is configured to be controlled by signals on corresponding first and third nodes. In some embodiments, the first equalizer circuit of the global write driver includes: a first transistor and a second transistor connected in series between the LWB line and the LWB _ bar line; and the signals on the first and third nodes are connected to the corresponding gate electrodes of the first and second transistors. In some embodiments, the first equalizer circuit of the global write driver includes: a transistor connected in series between the LWB line and the LWB _ bar line; and a logic circuit connected between the gate electrode of the transistor and each of the first node and the second node. In some embodiments, the logic circuit is configured to apply a logic OR function to the signals on the corresponding first and third nodes. In some embodiments, the first equalizer circuit of the global write driver is configured to turn off when the signals on the corresponding first and third nodes have different logic states. In some embodiments, the third inverter is connected between the GWB line and the LWB line by being connected between the corresponding fifth node and sixth node; a fourth inverter is connected between the GWB _ bar line and the LWB line by being connected between corresponding seventh and eighth nodes; and the local write driver further comprises: a second equalizer circuit connected between the LWB line and the LWB _ bar line and configured to be controlled by signals on corresponding fifth and seventh nodes. In some embodiments, the second equalizer circuit of each local write driver includes: a first transistor and a second transistor connected in series between the LWB line and the LWB _ bar line; and the signals on the fifth node and the seventh node are connected to the corresponding gate electrodes of the first transistor and the second transistor. In some embodiments, the second equalizer circuit of each local write driver includes: a transistor connected in series between the LWB line and the LWB _ bar line; and a logic circuit connected between the gate electrode of the second transistor and each of the fifth node and the seventh node. In some embodiments, the logic circuit is configured to apply a logical OR function to the signals on the corresponding fifth and seventh nodes. In some embodiments, the second equalizer circuit of each local write driver is configured to turn off when the signals on the corresponding fifth and seventh nodes have different logic states. In some embodiments, the maximum speed is a parameter representing a maximum operating speed of the corresponding circuit; the coverage area is a parameter representing the area consumed by the corresponding circuit; and configuring the local write driver and the global write driver to correspondingly exhibit one of the following descriptions: the local write driver is configured to have substantially the same maximum speed as compared to the global write driver, and the local write driver is configured to have substantially the same footprint as compared to the global write driver; alternatively, the local write driver is configured to have a lower maximum speed than the global write driver, and the local write driver is configured to have a smaller footprint than the global write driver.
In another embodiment, a semiconductor memory device includes: a column of sectors, each sector comprising a bit cell; a Local Write Bit (LWB) line; a local write bit _ bar (LWB _ bar) line; a Global Write Bit (GWB) line; a global write bit _ bar (GWBL _ bar) line; each of the bit cells includes: a latch circuit; the first and second pass gates connect the corresponding LWB and LWB _ bar lines to the latch circuit; and the distributed write drive arrangement comprises: a global write driver and a local write driver. A global write driver is connected between the GWB line and the LWB line and between the GWB _ bar line and the LWB _ bar line. Local write drivers are included in each sector, each local write driver connected between a GWB line and an LWB line and between a GWB _ bar line and an LWB _ bar line; and wherein: each local write driver is in the first device layer; and the global write driver is located in a second device layer above the first device layer. In some embodiments, each local write driver is located at an internal location in the corresponding zone; the bit cell is located in the first device layer; the LWB and LWB _ bar lines are located in a first metallization layer, the first metallization layer located between the first device layer and the second device layer; a first device layer; and the GWB line and the GWBL _ bar line are located in a second metallization layer, the second metallization layer being located between the first metallization layer and the second device layer. In some embodiments, the maximum speed is a parameter representing a maximum operating speed of the corresponding circuit; the coverage area is a parameter representing the area consumed by the corresponding circuit; and configuring the local write driver and the global write driver to correspondingly exhibit one of the following descriptions: the local write driver is configured to have substantially the same maximum speed as compared to the global write driver, and the local write driver is configured to have substantially the same footprint as compared to the global write driver; alternatively, the local write driver is configured to have a lower maximum speed than the global write driver, and the local write driver is configured to have a smaller footprint than the global write driver.
In another embodiment, a method of write-driving a column in an SRAM macro on a distributed basis, the column includes a Global Write Bit (GWB) line, a global write bit _ bar (GWBL _ bar) line, a Local Write Bit (LWB) line, a local write bit _ bar (LWB _ bar) line, bit cells and at least one local write driver, each bit cell including a latch circuit and first and second pass gates connecting corresponding LWB and LWB _ bar lines, a global write driver including a first inverter connected between the GWB and LWB lines and a second inverter connected between the GWB and LWB _ bar lines, and a local write driver including a third inverter connected between the GWB line and the LWB line and a fourth inverter connected between the GWB _ bar line and the LWB _ bar line, and the local write driver is located at an inner portion of the column; the method comprises the following steps: driving a GWB line with a first signal having a first logic value; driving the GWB _ bar line with a second signal having the first logic value or a second logic value opposite to the first logic value; inverting the first signal with each of the first inverter in the global write driver and the third inverter in the local write driver to form a first _ bar signal having a second logic value; inverting the second signal with each of the second inverter in the global write driver and the fourth inverter in the local write driver to form a second _ bar signal having an opposite logic value to the second signal; driving the LWB lines with a first _ bar signal to provide a first _ bar signal to a first pass gate of each of the bit cells; and driving the LWB _ bar line with a second _ bar signal to provide the second _ bar signal to the second pass-gate of each of the bit cells. In some embodiments, the global write driver includes a first equalizer circuit connected between the LWB line and the LWB _ bar line; the local write driver includes a second equalizer circuit connected between the LWB line and the LWB _ bar line; and the method further comprises: controlling a first equalizer circuit with a first signal and a second signal; and controlling a second equalizer circuit with the first signal and the second signal. In some embodiments, controlling the first equalizer circuit comprises: turning off the first equalizer circuit when the first signal and the second signal have different logic values; and controlling the second equalizer circuit comprises: the second equalizer circuit is turned off when the first signal and the second signal have different logic values. In some embodiments, the first equalizer circuit includes a first transistor and a second transistor connected in series between the LWB line and the LWB _ bar line; the local write driver further includes a third transistor and a fourth transistor connected in series between the LWB line and the LWB _ bar line; and controlling the first equalizer circuit includes: providing a first signal to a gate of a first transistor; supplying a second signal to a gate of the second transistor; and controlling the second equalizer circuit comprises: providing a first signal to a gate of a first transistor; and providing a second signal to a gate of the fourth transistor. In some embodiments, the first equalizer circuit includes a transistor connected in series between the LWB line and the LWB _ bar line; and controlling the first equalizer circuit comprises: logically combining the first signal and the second signal to form a third signal; and providing a third signal to the gate of the transistor.
According to an embodiment of the present application, there is provided a semiconductor memory device including: a Local Write Bit (LWB) line; a local write bit _ bar (LWB _ bar) line; a Global Write Bit (GWB) line; a global write bit _ bar (GWBL _ bar) line; a column of sectors, each sector comprising a bit cell; each of the bit cells includes a latch circuit and first and second pass gates connecting the corresponding LWB and LWB _ bar lines to the latch circuit; and the distributed write driver arrangement includes a global write driver and a local write driver: the global write driver includes: a first inverter connected between the GWB line and the LWB line; and a second inverter connected between the GWB _ bar line and the LWB _ bar line; and the local write drivers contained in each sector, each local write driver located inside the corresponding sector, each local write driver comprising: a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB _ bar line and the LWB _ bar line.
According to an embodiment of the present application, the first inverter is connected between the GWB line and the LWB line by connecting between corresponding first and second nodes; the second inverter is connected between the GWB _ bar lines by a connection between the corresponding third and fourth nodes; and the global write driver further comprises: a first equalizer circuit connected between the LWB line and the LWB _ bar line and configured to be controlled by signals on the corresponding first and third nodes.
According to an embodiment of the present application, the first equalizer circuit of the global write driver includes: a first transistor and a second transistor connected in series between the LWB line and the LWB _ bar line; and the first node and the third node are connected to corresponding gate electrodes of the first transistor and the second transistor.
According to an embodiment of the present application, the first equalizer circuit of the global write driver includes: a transistor connected in series between the LWB line and the LWB _ bar line; and a logic circuit connected between a gate electrode of the transistor and each of the first node and the second node.
According to an embodiment of the application, the logic circuit is configured to apply a logical OR function to the signals on the corresponding first and third nodes.
According to an embodiment of the application, the first equalizer circuit of the global write driver is configured to turn off reactions to signals on the corresponding first and third nodes having different logic states.
According to an embodiment of the present application, the third inverter is connected between the GWB line and the LWB line by connecting between corresponding fifth and sixth nodes; the fourth inverter is connected between the GWB _ bar line and the LWB line by being connected between corresponding seventh and eighth nodes; and the local write driver further comprises: a second equalizer circuit connected between the LWB line and the LWB _ bar line and configured to be controlled by signals on the corresponding fifth and seventh nodes.
According to an embodiment of the present application, the second equalizer circuit of each local write driver includes: a first transistor and a second transistor connected in series between the LWB line and the LWB _ bar line; and the signals on the fifth node and the seventh node are connected to the corresponding gate electrodes of the first transistor and the second transistor.
According to an embodiment of the present application, the second equalizer circuit of each local write driver includes: a transistor connected in series between the LWB line and the LWB _ bar line; and a logic circuit connected between the gate electrode of the second transistor and each of the fifth node and the seventh node.
According to an embodiment of the application, the logic circuit is configured to apply a logical OR function to the signals on the corresponding fifth and seventh nodes.
According to an embodiment of the application, the second equalizer circuit of each local write driver is configured to turn off when the signals on the corresponding fifth and seventh nodes have different logic states.
According to an embodiment of the present application, the maximum speed is a parameter representing a maximum operating speed of the corresponding circuit; the coverage area is a parameter representing the area correspondingly consumed; and the local write driver and the global write driver are configured to correspondingly exhibit one of the following descriptions: the local write driver is configured to have substantially the same maximum speed as compared to the global write driver and the local write driver is configured to have substantially the same coverage area as compared to the global write driver; or the local write driver is configured to have a lower maximum speed than the global write driver and the local write driver is configured to have a smaller footprint than the global write driver.
According to an embodiment of the present application, there is provided a semiconductor memory device including: a column of sectors, each sector comprising a bit cell; a Local Write Bit (LWB) line; a local write bit _ bar (LWB _ bar) line; a Global Write Bit (GWB) line; a global write bit _ bar (GWBL _ bar) line; each of the bit cells comprises: a latch circuit; and connecting the corresponding LWB line and LWB _ bar line to a first pass gate and a second pass gate of the latch circuit; and the distributed write drive arrangement comprises: a global write driver connected between the GWB line and the LWB line and between the GWB _ bar line and the LWB _ bar line; local write drivers included in each sector, each local write driver connected between the GWB line and the LWB line and between the GWB _ bar line and the LWB _ bar line; and wherein: each local write driver is located in the first device layer; and the global write driver is located in a second device layer above the first device layer.
According to an embodiment of the application, each local write driver is located at an internal location in the corresponding zone; the bit cell is located in the first device layer; the LWB line and the LWB _ bar line are located in a first metallization layer located between the first device layer and the second device layer; the first device layer; and the GWB line and the GWBL _ bar line are located in a second metallization layer, the second metallization layer located between the first metallization layer and the second device layer.
According to an embodiment of the present application, the maximum speed is a parameter representing a maximum operating speed of the corresponding circuit; the coverage area is a parameter representing the area correspondingly consumed; and the local write driver and the global write driver are configured to correspondingly exhibit one of the following descriptions: the local write driver is configured to have substantially the same maximum speed as compared to the global write driver and the local write driver is configured to have substantially the same coverage area as compared to the global write driver; or the local write driver is configured to have a lower maximum speed than the global write driver and the local write driver is configured to have a smaller footprint than the global write driver.
In accordance with an embodiment of the present application, there is provided a method of writing-driving columns in an SRAM macro on a distributed basis, the columns including a Global Write Bit (GWB) line, a global write bit _ bar (GWBL _ bar) line, a Local Write Bit (LWB) line, a local write bit _ bar (LWB _ bar) line, bit cells, and at least one local write driver, each of the bit cells including a latch circuit and first and second pass gates connecting the corresponding LWB and LWB _ bar lines, the global write driver including a first inverter connected between the GWB and LWB lines and a second inverter connected between the GWB and LWB _ bar lines, and the local write driver including a third inverter connected between the GWB and LWB lines and a fourth inverter connected between the GWB and LWB _ bar lines, and the local write driver is located inside the column; the method comprises the following steps: driving the GWB line with a first signal having a first logic value; driving the GWB _ bar line with a second signal having the first logical value or a second logical value opposite the first logical value; inverting the first signal with each of the first inverter in the global write driver and the third inverter in the local write driver to form a first _ bar signal having the second logic value; inverting the second signal with each of the second inverter in the global write driver and the fourth inverter in the local write driver to form a second _ bar signal having an opposite logic value than the second signal; driving the LWB line with the first _ bar signal to provide the first _ bar signal to the first pass-gate of each of the bit cells; and driving an LWB _ bar line with the second _ bar signal to provide the second _ bar signal to the second pass-gate of each of the bit cells.
According to an embodiment of the present application, the global write driver includes a first equalizer circuit connected between the LWB line and the LWB _ bar line; the local write driver includes a second equalizer circuit connected between the LWB line and the LWB _ bar line; and the method further comprises: controlling the first equalizer circuit with the first signal and the second signal; and controlling the second equalizer circuit with the first signal and the second signal.
According to an embodiment of the application, controlling the first equalizer circuit includes: turning off the first equalizer circuit when the first signal and the second signal have different logic values; and controlling the second equalizer circuit comprises: turning off the second equalizer circuit when the first signal and the second signal have different logic values.
According to an embodiment of the present application, the first equalizer circuit includes a first transistor and a second transistor connected in series between the LWB line and the LWB _ bar line; the local write driver includes a third transistor and a fourth transistor connected in series between the LWB line and the LWB _ bar line; and controlling the first equalizer circuit comprises: providing the first signal to a gate of the first transistor; and providing the second signal to a gate of the second transistor; and controlling the second equalizer circuit comprises: providing the first signal to a gate of the first transistor; and providing the second signal to a gate of the fourth transistor.
According to an embodiment of the present application, the first equalizer circuit includes a transistor connected in series between the LWB line and the LWB _ bar line; and controlling the first equalizer circuit comprises: logically combining the first signal and the second signal to form a third signal; and providing the third signal to a gate of the transistor.
It will be seen that one or more of the disclosed embodiments achieves one or more of the advantages set forth above, as would be apparent to one of ordinary skill in the art. Numerous variations, equivalent alterations, and numerous other embodiments as broadly disclosed herein will occur to those of ordinary skill in the art upon reading the foregoing description. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.