阅读说明：本技术 动态随机存取存储器 (Dynamic random access memory ) 是由 藤冈伸也 池田仁史 于 2018-07-18 设计创作，主要内容包括：本发明提供一种动态随机存取存储器(DRAM)。所述DRAM包括一温度传感器、一动态存储器阵列、一控制电路、多个电力供应电路以及一电力控制电路。温度传感器感测DRAM的操作温度。控制电路耦接至动态存储器阵列,以及存取与管理动态存储器阵列。电力供应电路供电给动态存储器阵列与控制电路。电力控制电路控制所述多个电力供应电路的供电输出。当DRAM进入自刷新模式时,电力控制电路依照DRAM的操作温度而选择性地切换于低功率控制状态与通常功率控制状态之间。(The present invention provides Dynamic Random Access Memories (DRAMs) including a temperature sensor, a dynamic memory array, a control circuit, a plurality of power supply circuits, and a power control circuit.)

1, dynamic random access memory, comprising:

a temperature sensor sensing an operating temperature of the dynamic random access memory;

a dynamic memory array;

control circuitry coupled to the dynamic memory array and accessing and managing the dynamic memory array;

a plurality of power supply circuits that supply power to the dynamic memory array and the control circuit; and

a power control circuit that controls power supply outputs of the plurality of power supply circuits,

wherein when the dynamic random access memory enters a self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state in accordance with the operating temperature of the dynamic random access memory.

2. The dynamic random access memory of claim 1, wherein with the dynamic random access memory in the self-refresh mode, the power control circuit operates in the normal power control state when the operating temperature of the dynamic random access memory is above a threshold temperature, and the power control circuit operates in the low power control state when the operating temperature of the dynamic random access memory is below the threshold temperature.

3. The dram of claim 1, wherein when the power control circuit is operating in the low power control state, the power control circuit determines whether to leave the low power control state and enter the normal power control state according to the operating temperature of the dram.

4. The dram of claim 1, wherein when the power control circuit is operating in the normal power control state, the power control circuit determines whether to leave the normal power control state and enter the low power control state according to the operating temperature of the dram.

5. The dynamic random access memory according to claim 1, wherein the plurality of power supply circuits are divided into a plurality of groups, the plurality of groups including group ,

when the power control circuit operates in the low-power control state, and during an internal self-refresh command issuance period, the power control circuit controls the power supply output of the power supply circuits of the th group to switch from a floating state to an active state, and

when the power control circuit operates in the low power control state, and after the period during which the internal self-refresh command is issued ends, the power control circuit controls the power supply output of the power supply circuit of group to switch from the active state back to the floating state.

6. The dynamic random access memory of claim 5, wherein when the power control circuit operates in the normal power control state, the power control circuit controls a power supply output of the power supply circuit of the group to remain in the active state.

7. The dynamic random access memory according to claim 5, wherein the plurality of clusters includes a second cluster,

when the power control circuit operates in the low-power control state, the power control circuit controls a supply output of the power supply circuits of the second group to be switched from the active state to the floating state, an

When the power control circuit operates in the normal power control state, the power control circuit controls a supply output of the power supply circuits of the second group to switch from the floating state back to the active state.

8. The dynamic random access memory according to claim 7, wherein the plurality of clusters includes a third cluster,

when the power control circuit operates in the low power control state, the power control circuit controls the supply output of the power supply circuits of the third group to be clamped at a ground voltage, and

when the power control circuit operates in the normal power control state, the power control circuit controls a power supply output of the power supply circuits of the third group to return to the active state.

9. The dynamic random access memory according to claim 8, wherein the plurality of clusters includes a fourth cluster,

when the power control circuit operates in the low-power control state, the power control circuit controls a supply output of the power supply circuits of the fourth group to remain in the active state, an

When the power control circuit operates in the normal power control state, the power control circuit controls a power supply output of the power supply circuits of the fourth group to remain in the active state.

10. The dynamic random access memory according to claim 1, wherein the control circuit comprises:

an input-output circuit to provide an access interface to an external device, wherein the plurality of power supply circuits includes an input-output power supply circuit to supply power to the input-output circuit, a supply output of the input-output power supply circuit remains in a floating state when the power control circuit operates in the low-power control state, and the supply output of the input-output power supply circuit switches from the floating state back to an active state when the power control circuit operates in the normal power control state; and

peripheral circuitry coupled between the input-output circuitry and the dynamic memory array, wherein the peripheral circuitry manages the power control circuitry by issuing at least internal commands, the at least internal commands including an internal self-refresh command, a self-refresh entry command, or a self-refresh exit command, the plurality of power supply circuitry further including peripheral power supply circuitry to power the peripheral circuitry, the power supply output of the peripheral power supply circuitry remaining in the active state when the power control circuitry is operating in the low-power control state and the normal power control state.

The dynamic random access memory of the kind 11, , wherein the dynamic random access memory includes:

a dynamic memory array;

control circuitry coupled to the dynamic memory array and accessing and managing the dynamic memory array;

a plurality of power supply circuits for supplying power to the DRAM array and the control circuit, wherein the plurality of power supply circuits are divided into a plurality of groups, the plurality of groups include group

A power control circuit that controls power supply outputs of the plurality of power supply circuits,

wherein the power control circuit selectively switches between a low power control state and a normal power control state when the dynamic random access memory enters a self-refresh mode,

wherein when the power control circuit operates in the low power control state and during an internal self-refresh command issuance period, the power control circuit controls a power supply output of the power supply circuits of the th group to switch from a floating state to an active state, and

wherein when the power control circuit operates in the low power control state and after the internal self-refresh command issuance period ends, the power control circuit controls the power supply output of the power supply circuits of group to switch from the active state back to the floating state.

12. The dynamic random access memory of claim 11, wherein the control circuit comprises:

an input-output circuit to provide an access interface to an external device, wherein the plurality of power supply circuits includes an input-output power supply circuit to supply power to the input-output circuit, a supply output of the input-output power supply circuit remains in the floating state when the power control circuit operates in the low-power control state, and the supply output of the input-output power supply circuit switches from the floating state back to the active state when the power control circuit operates in the normal power control state; and

peripheral circuitry coupled between the input-output circuitry and the dynamic memory array, wherein the peripheral circuitry manages the power control circuitry by issuing at least internal commands, the at least internal commands including an internal self-refresh command, a self-refresh entry command, or a self-refresh exit command, the plurality of power supply circuitry further including peripheral power supply circuitry to power the peripheral circuitry, the power supply output of the peripheral power supply circuitry remaining in the active state when the power control circuitry is operating in the low-power control state and the normal power control state.

13. The dynamic random access memory of claim 11, wherein the plurality of power supply circuits includes an th storage cell power supply circuit, a second storage cell power supply circuit, a third storage cell power supply circuit, a th sense amplifier power supply circuit, a second sense amplifier power supply circuit, and a third sense amplifier power supply circuit for powering the dynamic memory array,

the th storage cell power supply circuit and the third sense amplifier power supply circuit belong to the th group;

when the power control circuit operates in the low power control state, the th sense amplifier power supply circuit switches its supply output to the floating state, the second and third storage cell power supply circuits clamp their supply outputs to ground, the second sense amplifier power supply circuit remains in the active state, and

when the power control circuit operates in the normal power control state, power supply outputs of the th sense amplifier power supply circuit, the second storage unit power supply circuit, and the third storage unit power supply circuit revert to the active state.

14. The dram of claim 11, further comprising:

a temperature sensor sensing an operating temperature of the dynamic random access memory,

when an external device requests the dynamic random access memory to enter the self-refresh mode, the control circuit determines whether to enter the self-refresh mode according to the operating temperature of the dynamic random access memory.

15. The dram of claim 14, wherein the control circuit determines whether to leave the self-refresh mode according to the operating temperature of the dram when the dram is operating in the self-refresh mode.

Technical Field

The present invention relates to kinds of memories, and more particularly to kinds of Dynamic Random Access Memories (DRAMs).

Background

Recently, products of the Narrow-Band Internet of Things (NB-IoT), such as wearable devices, mobile devices, etc., require low power memory with about megabit memory capacity therefore, low power dynamic random access memory, such as pseudo static random access memory (pSRAM), is widely used in NB-IoT by .

Disclosure of Invention

It is an object of the present invention to provide DRAM devices for further reducing power of the DRAM device in self-refresh (self-refresh) mode.

The embodiment of the invention provides dynamic random access memories, which comprises a temperature sensor, a dynamic memory array, a control circuit, a plurality of power supply circuits and a power control circuit, wherein the temperature sensor senses the operating temperature of the dynamic random access memory, the control circuit is coupled to the dynamic memory array, and accesses and manages the dynamic memory array, the power supply circuit supplies power to the dynamic memory array and the control circuit, the power control circuit controls the power supply output of the plurality of power supply circuits, and when the dynamic random access memory enters a self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the dynamic random access memory.

Embodiments of the present invention provide types of dynamic random access memory including a dynamic memory array, control circuitry, a plurality of power supply circuits, and power control circuitry coupled to the dynamic memory array, and accessing and managing the dynamic memory array.

As indicated at , the DRAM of embodiments of the present invention may manage power to the DRAM in the self-refresh mode in steps to reduce current consumed by the DRAM in the self-refresh mode.

In particular, for a semiconductor memory having a self-refresh mode enabled by an external command issued by a memory controller within a microcontroller or system on chip, after entering the self-refresh mode, a power control circuit may detect an operating temperature of the semiconductor memory via a temperature sensor, the temperature sensor may further manage power of the semiconductor memory based on the operating temperature.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a block diagram illustrating an electronic system with a DRAM as its main memory according to an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating the operation mode of the pSRAM of FIG. 1 in accordance with embodiment of the present invention.

FIG. 3 is a block diagram illustrating the circuit of the pSRAM of FIG. 1 in accordance with an embodiment of the present invention.

FIG. 4 is a flow chart illustrating a method of operation of the pSRAM in accordance with an embodiment of the present invention.

Fig. 5A is a power diagram illustrating a power supply circuit belonging to group according to an embodiment of the present invention .

Fig. 5B is a waveform diagram illustrating the voltage VHLF of fig. 3 in a low power control state according to an embodiment of the invention.

Fig. 6 is a power diagram illustrating an embodiment of of a power supply circuit belonging to the second group.

Fig. 7 is a power diagram illustrating a power supply circuit belonging to the third group according to an embodiment of the present invention .

Description of the reference numerals

100: electronic system

110: pseudo static random access memory (pSRAM)

111: control circuit

111 a: input/output circuit

111 b: peripheral circuit

111 c: receiving circuit

112: dynamic memory array

113: temperature sensor

114: power control circuit

115 a: input/output power supply circuit

115 b: peripheral power supply circuit

115c, 115d, 115 e: sense amplifier power supply circuit

115f, 115g, 115 h: power supply circuit for storage unit

120: external device

AREF: internal self-refresh command

CMD, DQ: pin

Cont1, Cont2, Cont 3: control signal

ELPEN: self-refresh entry command

ELPEXIT: self-refresh exit command

VBB, VBLH, VHLF, VINT, VIO, VNWL, VOD, VPP: voltage of

VDD: system voltage

VSS: ground voltage

S410 to S480: step (ii) of

Detailed Description

For example, if is described as being coupled (or connected) to a second device, it should be understood that device may be directly connected to the second device or device may be indirectly connected to the second device through other devices or some connection means.

Although the pseudo-static random access memory is used as an example of implementations of the dram, it should be noted that the following embodiments are described with reference to the pseudo-static random access memory, but the following description of the embodiments can also be applied to other types of drams with a self-refresh mode.

FIG. 1 is a circuit block diagram illustrating an embodiment of an electronic system 100 having a Dynamic Random Access Memory (DRAM) as its main memory, wherein the embodiment shown in FIG. 1 is examples of the DRAM 110. the description of the embodiment shown in FIG. 1 can also be applied to other types of DRAMs.pSRAM 110 is connected to an external device 120 via a pin CMD and a pin DQ. the external device 120 can be an MCU, an SoC or other operational circuits/elements according to design requirements.A memory controller (not shown) in the external device 120 can issue external commands (such as access commands, management commands, etc.) to pSRAM 110. for example, the external device 120 can issue external commands to pSRAM110 according to system transactions (system transactions). pSRAM110 performs corresponding operations according to each external command.

Fig. 2 is a diagram illustrating an operation mode of the pSRAM110 shown in fig. 1 according to an embodiment of the present invention, after power on (poweron), the pSRAM110 enters a standby mode (standby mode), in which the pSRAM110 may receive an external command from the external device 120 and execute a corresponding operation mode according to the external command, for example, when the pSRAM110 receives a read command from the external device 120, the pSRAM110 may enter a read mode (readmode) from the standby mode, after completing the read command, the pSRAM110 may return to the standby mode from the read mode, when the pSRAM110 receives a write command from the external device 120, the pSRAM110 may enter a write mode (write mode) from the standby mode, after completing the write command, the pSRAM110 may return to the standby mode from the write mode, when the pSRAM110 receives a depth command from the external device 120, the pSRAM110 may enter a depth power down mode (sleep mode) from the standby mode.

Based on the management of the dynamic memory array within the pSRAM110, control circuitry within the pSRAM110 issues a self-refresh enter (self-refresh entry) command ELPEN and a self-refresh exit (self-refresh) command ELPEXIT at appropriate times. When a control circuit within the pSRAM110 issues a self-refresh enter command ELPEN, the pSRAM110 may enter a self-refresh mode from a standby mode. When a control circuit within the pSRAM110 issues the self-refresh exit command ELPEXIT, the pSRAM110 may return to the standby mode from the self-refresh mode.

Alternatively, the external device 120 may require the pSRAM110 to enter a self-refresh mode based on the management of the dynamic memory array within the pSRAM 110. Upon receiving an entry request from the external device 120, the pSRAM110 may internally generate a self-refresh entry command ELPEN. The self-refresh enter command ELPEN may cause associated circuitry within pSRAM110 to enter a self-refresh mode. When the pSRAM110 receives an exit request from the external device 120, the pSRAM110 may internally generate a self-refresh exit command ELPEXIT, and then the pSRAM110 returns to the standby mode.

FIG. 3 is a block diagram illustrating the circuit of the pSRAM110 of FIG. 1 according to an embodiment of the present invention, wherein the pSRAM110 of FIG. 3 comprises a control circuit 111, a dynamic memory array 112, a temperature sensor 113, a power control circuit 114, and a plurality of power supply circuits 114, wherein the power control circuit 114 can control the power outputs of the plurality of power supply circuits that can power the dynamic memory array 112 and the control circuit 111, and wherein the plurality of power supply circuits comprises an input-output power supply circuit 115a, a peripheral power supply circuit 115b, a sense amplifier power supply circuit 115c, a sense amplifier power supply circuit 115d, a sense amplifier power supply circuit 115e, a storage unit power supply circuit 115f, a storage unit power supply circuit 115g, and a storage unit power supply circuit 115h in the embodiment of FIG. 3.

Control circuit 111 is coupled to dynamic memory array 112. control circuit 111 can access and manage dynamic memory array 112. dynamic memory array 112 can include a memory cell array, sense amplifiers, an X decoder, and a Y decoder. temperature sensor 113 senses the operating temperature of pSRAM 110. in the embodiment, dynamic memory array 112 can be a conventional dynamic memory array and will not be described herein.

When the external device 120 requests the pSRAM110 to enter the self-refresh mode, the control circuit 111 may determine whether to operate the pSRAM110 in the normal power control state or the low power control state according to the operating temperature of the pSRAM 110. for example, if the operating temperature of the pSRAM110 is above a threshold temperature (threshold temperature), the control circuit 111 first operates the pSRAM110 in the normal power control state.

After the pSRAM110 enters the self-refresh mode, and before the external device 120 requests the pSRAM110 to leave the self-refresh mode, the control circuit 111 can selectively switch the pSRAM110 between the normal power control state and the low power control state according to the operating temperature of the pSRAM 110. For example, after the pSRAM110 enters the self-refresh mode, when the pSRAM110 is operating in the normal power control state, if the operating temperature of the pSRAM110 is sensed to be lower than the threshold temperature, the control circuit 111 will switch the pSRAM110 to the low power control state; similarly, when the pSRAM110 is operating in the low power control state, the control circuit 111 switches the pSRAM110 to the normal power control state if the operating temperature of the pSRAM110 is sensed to be higher than the threshold temperature.

When the external device 120 requests the pSRAM110 to leave the self-refresh mode, the control circuit 111 controls the pSRAM110 to operate in the normal power state and then returns the pSRAM110 to the standby mode. Specifically, when the external device 120 requests the pSRAM110 to exit the self-refresh mode, if the pSRAM110 is operating in the normal power state, the pSRAM110 immediately returns to the standby mode. However, if the pSRAM110 is operated in the low power control state, the control circuit 111 will control the pSRAM110 to switch to the normal power control state first, and then make the pSRAM110 return to the standby mode.

The pSRAM110 receives an external command from the external device 120. In the embodiment shown in fig. 3, the control circuit 111 includes an input/output circuit 111a, a peripheral circuit 111b, and a receiving circuit 111 c. The peripheral circuit 111b is coupled between the input/output circuit 111a and the dynamic memory array 112, and is coupled between the receiving circuit 111c and the dynamic memory array 112. The input-output power supply circuit 115a may supply power to the input-output circuit 111 a. The system voltage VDD may power the receiving circuit 111 c. In the low power control state, the system voltage VDD may continuously power (activate) the receiving circuit 111 c. Therefore, the receiving circuit 111c can function as a receiver in the low power mode. When the power control circuit 114 operates in the low power control state, the power supply output of the input-output power supply circuit 115a is kept in a floating state (stops supplying the voltage VIO). When the power control circuit 114 operates in the normal power control state, the power supply output of the input-output power supply circuit 115a switches from the floating state back to the active state (resumes supplying the voltage VIO to the input-output circuit 111 a). The peripheral power supply circuit 115b supplies power to the peripheral circuit 111 b. When the power control circuit 114 operates in the low power control state and the normal power control state, the power supply output of the peripheral power supply circuit 115b is kept in the active state (continuously supplying the voltage VINT to the peripheral circuit 111 b).

The input output circuit 111a may provide an access interface to the external device 120. the input output circuit 111a may buffer external commands from the external device 120 and transmit the external commands to the peripheral circuit 111 b. in the peripheral circuit 111b, such external commands are decoded and cause the pSRAM110 to enter a corresponding mode (as shown in fig. 2). the peripheral circuit 111b manages the power control circuit 114 and other circuits by issuing at least internal commands the at least internal commands include an internal self-refresh command AREF, a self-refresh enter command ELPEN, or a self-refresh exit command elpexit. when an external command requires entry into a self-refresh mode, the peripheral circuit 111b may correspondingly control the power control circuit 114 to manage power to the pSRAM110 in the self-refresh mode for steps.

Fig. 4 is a flow chart illustrating an operation method of the pSRAM110 according to an embodiment of the present invention , in the standby mode, after the pSRAM110 receives an instruction to enter the self-refresh mode from the external device 120, the power control circuit 114 may check an operating temperature of the pSRAM110 through the temperature sensor 113 and determine a power control state according to the operating temperature of the pSRAM110, when the pSRAM110 enters the self-refresh mode (step S410), the power control circuit 114 may selectively switch between a low power control state (step S430) and a normal power control state (step S440) according to the operating temperature of the pSRAM 110.

For example, when step S420 determines that the operating temperature of the pSRAM110 is lower than the threshold temperature with the pSRAM110 in the self-refresh mode, the power control circuit 114 operates in the low power control state (step S430). In the case where the power control circuit 114 operates in the low power control state, the power control circuit 114 may continuously check the operating temperature of the pSRAM110 (step S420), and decide whether to leave the low power control state and enter the normal power control state according to the operating temperature of the pSRAM110 (step S440). When it is judged in step S420 that the operating temperature of the pSRAM110 is higher than the threshold temperature, the power control circuit 114 operates in the normal power control state (step S440).

In the case where the power control circuit 114 operates in the normal power control state, the power control circuit 114 may continuously check the operating temperature of the pSRAM110 (step S420), and decide whether to leave the normal power control state (step S440) and enter the low power control state (step S430) according to the operating temperature of the pSRAM 110. When it is judged at step S420 that the operating temperature of the pSRAM110 is lower than the threshold temperature, the power control circuit 114 operates in the low power control state (step S430).

That is, regardless of whether the pSRAM110 is operating in the low power control state (step S430) or the normal power control state (step S440), the pSRAM110 continuously checks the operating temperature of the pSRAM110 using the temperature sensor 113, and determines whether the pSRAM110 should switch to operate in the normal power control state (step S440) or the low power control state (step S430).

In the normal power control state (step S440) and the low power control state (step S430), the control circuit 111 may wait for an exit command received from the external device 120 (steps S450 and S460). When the external device 120 requests the pSRAM110 to leave the self-refresh mode, the pSRAM110 first checks the power control state. When the pSRAM110 is in the normal power control state (step S440), if the pSRAM110 receives an exit command from the external device 120 (step S460 "yes"), the pSRAM110 directly exits the self-refresh mode and returns to the standby mode (step S470). In the low power control state (step S430), when the pSRAM110 receives an exit command from the external device 120 (yes in step S450), the power control circuit 114 leaves the low power control state (step S430) and enters the normal power control state (step S480), and after entering the normal power control state, the pSRAM110 automatically exits the self-refresh mode and returns to the standby mode (step S470).

For example, in the embodiment shown in FIG. 3, the sense amplifier power supply circuit 115e supplying the voltage VHLF and the memory cell power supply circuit 115f supplying the voltage VPP belong to group , the input/output power supply circuit 115a supplying the voltage VIO and the sense amplifier power supply circuit 115c supplying the voltage VOD belong to group two, the memory cell power supply circuit 115g supplying the voltage VNWL and the memory cell power supply circuit 115h supplying the voltage VBB belong to group three, the peripheral power supply circuit 115b supplying the voltage VINT and the sense amplifier power supply circuit 115d supplying the voltage VBLH belong to group four, the power control circuit 114 controls the power supply circuits belonging to group by the control signal Cont1, controls the power supply circuits belonging to group two by the control signal Cont2, and controls the power supply circuits belonging to group three by the control signal Cont3, the power supply circuit branch table 1 illustrates the general power control strategy of the power supply circuits operated in the following power control states and control states.

Table 1: control meter for power supply circuit

In this table 1, voltage VPP and voltage VNWL are used to control memory cells in dynamic memory array 112. Voltage VPP is used to turn on the memory cell and voltage VNWL is used to turn off the memory cell. Voltage VOD, voltage VBLH and voltage VHLF are used to manage and control the sense amplifiers in dynamic memory array 112. The voltage VOD and the voltage VBLH are used to guarantee a high logic level of data. The voltage VHLF can clamp the bit line level to VBLH/2 in the standby state, which means that the bit line voltage needs to be set to 1/2 of VBLH when the pSRAM110 is in the standby mode. In other words, VHLF is VBLH/2. The voltage VINT is used to manage the peripheral circuits 111b, and the voltage VIO is used to manage the input-output circuits 111 a. The voltage VBB is used to provide a back bias level (back bias level) for the memory cells in the dynamic memory array 112. The levels of these voltages shown in FIG. 3 and Table 1 may be determined according to design requirements. For example, but not limited to, VPP 2.85V, VOD 1.8V, VINT 1.1V, VIO 1.1V, VBLH 1.1V, VHLF 0.55V, VNWL 0.15V, VBB 0.5V. VDD is 1.8V, VSS is 0V.

According to the description related to fig. 4, the power control circuit 114 can be selectively switched between the low power control state and the normal power control state based on the detection result of the operating temperature of the temperature sensor 113. In the normal power control state, the power control circuit 114 may activate (active) the input-output power supply circuit 115a, the sense amplifier power supply circuit 115c, the sense amplifier power supply circuit 115e, the storage unit power supply circuit 115f, the storage unit power supply circuit 115g, and the storage unit power supply circuit 115 h. In the active state, the input-output power supply circuit 115a supplies the voltage VIO (at the same time, the level of the voltage VIO is the same as the voltage VINT), the peripheral power supply circuit 115b supplies the voltage VINT, the sense amplifier power supply circuit 115c supplies the voltage VOD, the sense amplifier power supply circuit 115d supplies the voltage VBLH, the sense amplifier power supply circuit 115e supplies the voltage VHLF, the memory cell power supply circuit 115f supplies the voltage VPP, the memory cell power supply circuit 115g supplies the voltage VNWL, and the memory cell power supply circuit 115h supplies the voltage VBB.

FIG. 5A is a power diagram illustrating the power supply circuits belonging to group according to an embodiment of the invention , wherein the horizontal axis represents time and the vertical axis represents power in FIG. 5A. when the power control circuit 114 operates in the normal power control state, the power control circuit 114 controls the power supply output of the power supply circuit belonging to group to remain in the active state. according to the related description of FIG. 4, the power control circuit 114 can switch the power supply circuit belonging to group from the normal power control state (active state) to the low power control state. in the low power control state, the power supply output of the power supply circuit belonging to group can operate in the floating state or active state according to the internal self-refresh command AREF. therefore, the power control circuit 114 can further manage the power of the power supply circuits belonging to group in the self-refresh mode to reduce the power of the power supply circuits (as shown in FIG. 5A).

Fig. 5B illustrates a waveform of the voltage VHLF of the sense amplifier power supply circuit 115e of fig. 3 in a low power control state according to an embodiment of the invention, the other power supply circuits (e.g., the memory cell power supply circuit 115f) belonging to the th group may refer to the related description of the sense amplifier power supply circuit 115e, and therefore are not repeated, in fig. 5B, the horizontal axis represents time and the vertical axis represents voltage level, in the low power control state, the power supply output of the sense amplifier power supply circuit 115e is usually maintained in a floating state (except for PAREF during which the internal self-refresh command is issued), the time length of the PAREF during which the internal self-refresh command is issued may be determined according to design requirements, for example, in the implementation example shown in fig. 5B, the period from 1.5 microseconds (μ s) before the internal self-refresh command AREF to 0.5 μ s after the internal self-refresh command AREF is defined as the internal self-refresh command issue period, the power supply control circuit may be configured to perform a power supply operation from the power supply state of the power supply circuit 115e after the power supply circuit 115e is turned into the power supply state of the internal power supply circuit 115e, so that the power supply circuit 115e is turned into the power supply circuit 114 is turned from the power supply state of the power supply circuit 115e supply circuit 114, and the power supply circuit 114 is dynamically switched from the power supply circuit according to the power supply state of the power supply circuit 114.

FIG. 6 is a power diagram illustrating embodiments according to the invention, where the horizontal axis represents time and the vertical axis represents power, the power control circuit 114 controls the power supply output of the power supply circuit belonging to the second group to remain active when the power control circuit 114 operates in the normal power control state, the power control circuit 114 may switch the power supply circuit belonging to the second group from the normal power control state (active state) to the low power control state in the self-refresh mode, according to the related description of FIG. 4, the power control circuit 114 may switch the power supply output of the power supply circuit belonging to the second group from the normal power control state (active state) to the low power control state, the power control circuit 114 may operate in the floating state to reduce leakage current, the power control circuit 114 may switch the power supply output of the power supply circuit belonging to the second group from the floating state back to the active state when the power control circuit 114 operates in the normal power control state, the power control circuit 114 may further manage the power supply circuit belonging to the second group in the self-refresh mode, as shown in FIG. 6.

FIG. 7 is a power diagram illustrating an embodiment of according to the invention, wherein the horizontal axis represents time and the vertical axis represents power, wherein the power control circuit 114 controls the power supply output of the power supply circuit belonging to the third group to remain active when the power control circuit 114 operates in the normal power control state, according to the related description of FIG. 4, the power control circuit 114 can switch the power supply circuit belonging to the third group from the normal power control state (active state) to the low power control state, wherein the power supply output of the power supply circuit belonging to the third group can be clamped (clamp) to the ground voltage VSS, for example, the voltage VBB and the voltage VNWL are used to maintain memory cell data (cell data) at high temperatures, but are not required to be used at room temperature, so if the operating temperature of the pSRAM110 is below the threshold temperature, the voltage VBB and the voltage VNWL can be clamped to the ground voltage VSS, the power control circuit 114 controls the power supply circuit belonging to the third group to remain active when the power control circuit 114 operates in the normal power control state, thus the power control circuit 114 can be reset to the power supply state shown in the power control mode .

Referring to table 1, fig. 3 and fig. 4, when the power control circuit 114 operates in the low power control state and the normal power control state, the power control circuit 114 controls the power supply output of the power supply circuit belonging to the fourth group to be kept in an active state, for example, the peripheral circuit 111b needs the voltage VINT to periodically issue the internal self-refresh command aref, even in the self-refresh mode, the peripheral power supply circuit 115b should be kept in the active state to continuously supply the voltage VINT to the peripheral circuit 111b, and the sense amplifier power supply circuit 115d can be kept in the active state because the consumption current of the voltage VBLH is very low in terms of .

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Thus , power to the pSRAM in the self-refresh mode can be further managed to reduce the current consumed by the pSRAM in the refresh mode.