阅读说明：本技术 用于半导体器件布局的分数高度转换单元 (Fractional height conversion cell for semiconductor device layout ) 是由 黄志伟 阿什瓦尼·库马尔·斯里瓦斯塔瓦 于 2019-07-11 设计创作，主要内容包括：本公开涉及用于半导体器件布局的分数高度转换单元。本文公开的主题一般涉及半导体器件,并且更具体地,涉及半导体器件布局,包括诸如包含finFET型器件的单元。例如,半导体器件可以包括finFET型器件,其布置在包括分数高度单元的标准单元结构中。(Subject matter disclosed herein relates generally to semiconductor devices and, more particularly, to semiconductor device layouts, including cells such as including finFET-type devices.)

An integrated circuit device of the type , comprising:

an th cell, the th cell including a th plurality of fins of a th diffusion type aligned along a 0 th direction and a second plurality of fins of a second diffusion type aligned along the th direction, wherein a number of the th plurality of fins of the th diffusion type is at least equal to a number of the second plurality of fins of the second diffusion type, and wherein or more fins of the th plurality of fins of the th diffusion type are located below a supply voltage electrode.

2. The integrated circuit device of claim 1 further comprising or more second cells having a standard cell height and or more third cells having a dual standard cell height, wherein the th cell provides a transition between the or more second cells having a standard cell height and the or more third cells having a dual standard cell height.

3. The integrated circuit device of claim 2 wherein the th cell has a fractional cell height that is greater than the standard cell height.

4. The integrated circuit device of claim 3, wherein the fractional cell height is about 1.5 times the standard cell height.

5. The integrated circuit device of claim 4, wherein a ratio of a number of the plurality of fins of the th diffusion type to a number of the second plurality of fins of the second diffusion type is 3: 1.

6. The integrated circuit device of claim 5 wherein the number of the plurality of fins of the th diffusion type is 6 and the number of the second plurality of fins of the second diffusion type is 2.

7. The integrated circuit device of claim 1, wherein the th cell has a height that is about 2.5 times a standard cell height, and wherein or more of the second plurality of fins of the second diffusion type are located below a common source electrode.

8. The integrated circuit device of claim 7, wherein a ratio of a number of the plurality of fins of the th diffusion type to a number of the second plurality of fins of the second diffusion type is about 1.67: 1.

9. The integrated circuit device of claim 8 wherein the number of the plurality of fins of the th diffusion type is 10 and the number of the second plurality of fins of the second diffusion type is 6.

10. The integrated circuit device of claim 1 wherein the th diffusion type comprises an n-type diffusion, and wherein the second diffusion type comprises a p-type diffusion.

11. The integrated circuit device of claim 1 wherein the th diffusion type comprises a p-type diffusion, and wherein the second diffusion type comprises an n-type diffusion.

12. The integrated circuit device of claim 1 further comprising a plurality of semiconductor fingers arranged in a second direction substantially orthogonal to the th direction.

The semiconductor device of species , comprising:

at least th finFET cells having a height of ;

at least second finFET cells having a second height, wherein the second height is approximately an integer multiple of the th height, and

at least third finFET cells having a third height, wherein the third height is a non-integer multiple of the th height, and wherein the third height is greater than the th height.

14. The semiconductor device of claim 13, wherein the at least -th finFET cell, the at least -standard finFET cell, and the at least -third finFET cell comprise a plurality of fins of -th diffusion type and a plurality of fins of a second diffusion type, respectively.

15. The semiconductor device of claim 14, wherein the at least finFET cells comprise a plurality of fins of the th diffusion type and a plurality of fins of the second diffusion type, wherein the number of the plurality of fins of the second diffusion type is equal to the number of the plurality of fins of the th diffusion type.

16. The semiconductor device of claim 15, wherein the at least third finFET cells comprise the diffusion type plurality of fins and the second diffusion type plurality of fins, wherein the second diffusion type plurality of fins is greater in number than the diffusion type plurality of fins.

17. The semiconductor device of claim 16 wherein the third height is about 1.5 times the height and wherein the second height is about 2.0 times the height .

18. The semiconductor device of claim 16 wherein the third height is approximately 2.5 times the height and wherein the second height is approximately 2.0 times the height .

19. The semiconductor device of claim 13, wherein the at least third finFET cells provide a transfer between a region including the at least th finFET cells and a region including the at least second finFET cells.

20, a method, comprising:

at least partially according to a specified semiconductor device layout:

reading a specification for a th finFET cell type having a height of from a cell library stored in a memory of a computing device;

forming at least cells of the th finFET cell type having the th height on a semiconductor wafer according to the specified semiconductor device layout;

reading a specification of a second finFET cell type having a second height from the cell library;

forming at least cells of the second finFET cell type having the second height on the semiconductor wafer in accordance with the specified semiconductor device layout;

reading a specification of a third finFET cell type of a third height from the cell library;

forming at least cells of the third finFET cell type having the third height on the semiconductor wafer according to the specified semiconductor device layout, wherein the third height is a non-integer multiple of the th height, and wherein the third height is greater than the th height.

21. The method of claim 20 wherein said forming said at least cells of said third finFET cell type having said third height comprises providing a transition between said at least cells of said finFET cell type having said height and said at least cells of said second finFET cell type having said second height.

22. The method of claim 21, wherein the th height comprises a standard cell height specified by the cell library, wherein the second height comprises a dual cell height, and wherein the third cell height comprises a fractional cell height that is about 1.5 times the standard cell height.

23. The method of claim 21, wherein the th height comprises a standard cell height specified by the cell library, wherein the second height comprises a dual cell height, and wherein the third cell height comprises a fractional cell height that is about 2.5 times the standard cell height.

24. The method of claim 21, wherein said forming said at least cells of said third finFET cell type having said third height comprises forming a th plurality of fins of a th diffusion type aligned along a th direction and a second plurality of fins of a second diffusion type aligned along said th direction, wherein said th plurality of fins of said th diffusion type is greater in number than said second plurality of fins of said second diffusion type.

25. The method of claim 24 wherein said forming the plurality of fins of the th diffusion type comprises forming or more of the plurality of fins of the th diffusion type to be located below a supply voltage electrode.

Technical Field

Subject matter disclosed herein relates generally to semiconductor devices and, more particularly, to semiconductor device cell layouts, including cells such as those comprising finFET-type devices.

Background

In cases, the integrated circuit may be designed based on desired functionality using cells from a cell library, which may be combined using computer-based layout tools to form the desired circuit, also in cases, the cell library may be based on a finFET-based design architecture, which gains increasing acceptance in response to continued desire for lower power, higher performance, and/or more compact designs.

Drawings

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. However, both as to organization and/or method of operation, together with objects, features, and/or advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

fig. 1 is an illustration of an example finFET transistor structure, in accordance with an embodiment.

Fig. 2 is an illustration of an example layout of delineated cells (including standard height cells and dual height cells with NWELL offsets) from a cell library, according to an embodiment.

FIG. 3 is a diagram depicting an exemplary layout of cells (including fractional height conversion cells) from a cell library, according to an embodiment.

FIG. 4 is a diagram depicting an exemplary layout of cells (including fractional height conversion cells) from a cell library, according to an embodiment.

Fig. 5 is a diagram illustrating an example finFET layout including standard height cells and dual height cells with NWELL offset, according to an embodiment.

Fig. 6 is a diagram depicting an example finFET layout including fractional height conversion cells, according to an embodiment.

FIG. 7 is a diagram depicting an example standard height NAND cell, according to an embodiment.

FIG. 8 is a diagram depicting an example fractional height NAND cell, according to an embodiment.

Figure 9 depicts an illustration of an example process for forming fractional height finFET cells on a semiconductor wafer, in accordance with an embodiment.

It should be understood that the accompanying drawings are not to scale , such as for simplicity and/or clarity of illustration, for example, that the dimensions of some aspects may be exaggerated relative to other aspects.

Reference in this specification to "claimed subject matter" means subject matter that is intended to be covered by or more claims, or any portion thereof, and is not intended to be referring to the complete claim set, a particular combination of claim sets (e.g., method claims, apparatus claims, etc.), or a particular claim.

Detailed Description

Reference throughout this specification to embodiments, implementations, examples, embodiments, and/or the like means that a particular feature, structure, characteristic, and/or the like described in connection with the particular embodiments and/or examples is included in at least embodiments and/or examples of the claimed subject matter.

In some cases , the cell library may be based on a finFET-based design architecture that gains increasing acceptance in response to continued desire for lower power, higher performance, and/or more compact designs.

As used herein, "finFET" refers to a cell structure of a semiconductor device that is characterized, at least in part, by a plurality of fins of diffusion types or more, "fins" refers to elongated and/or linear diffusion structures of substantially rectangular and/or substantially triangular cross-section, e.g., projecting upward from an underlying substrate fig. 1 depicts, for example, an exemplary layout of an embodiment 100 of an exemplary finFET transistor structure fig. 1 depicts, a top view and a cross-sectional view fig. embodiments in which a finFET transistor (e.g., finFET transistor 100) may be comprised of fins of a particular diffusion type (e.g., fin 102), embodiments in which fin 102 may comprise an n-type diffusion material, other embodiments in which fin 102 may comprise a p-type diffusion material, embodiments in which a fin (e.g., fin 102) may be formed of any of a variety of materials (including materials such as silicon, silicon germanium, etc., to name a few examples.) furthermore, for example, in embodiments, a gate electrode (e.g., gate electrode 104) may comprise a plurality of materials such as silicon, silicon germanium, tantalum, and/or tantalum nitride, and/or any of these subject matter, such as silicon oxide, titanium nitride, 368678, in addition to the scope of these embodiments.

Moreover, although FIG. 1 depicts fins 102 having a substantially rectangular cross-section protruding substantially perpendicularly from substrate 105, other embodiments may include fins of different shapes.

In some examples , a cell library may include or more standard height cells as used herein, "standard height" refers to a specific height specified for a particular cell library.A cell having a "standard" height may be said to include "standard height", "single height" and/or "1.0 height" cells.in embodiments, a cell library may include single height cells of different widths.furthermore, in embodiments, a cell library may include cells having a height different from the standard height.for example, as described below, an exemplary semiconductor device layout may include or more single height cells and/or or more dual height cells.other height cells may also be incorporated.

Fig. 2 is an illustration of an embodiment 200 depicting an portion of an exemplary semiconductor device including an exemplary layout of cells, for example, semiconductor device layout 200 includes a plurality of single height cells 210, also depicting that such as semiconductor device layout 200 is a dual height cell 230 in embodiments, a single cell (e.g., cell 210 and/or 230) may include a plurality of diffusion type fins and another plurality of second diffusion type fins, as shown in exemplary layout 200. furthermore, as noted above, in embodiments, a dual height cell (e.g., cell 230) includes a dual height cell with an NWELL offset.

As described above, for example, in instances, a fill region (e.g., fill region 220) may be inserted into a semiconductor device layout to provide an offset for a particular cell (e.g., dual height cell 230). also in instances, a fill region (e.g., fill region 220) may have a height of half of a single height cell.for example, dual height cell 230 abuts single height cell 210 with an offset of half of a standard cell height.in instances, a fill region (e.g., fill region 220) may include unused fins and/or may provide little or no functionality.

Fig. 3 is a diagram depicting an example layout 300 for at least a portion of a semiconductor device, for example, the semiconductor device layout 300 includes a plurality of single height cells 310, and an example dual height cell 330, further, similar to the example layout 200 described above, a single cell (e.g., cell 310 and/or 330) may include a plurality of -diffusion type fins and another plurality of second diffusion type fins, as shown in the example layout 300, further, similar to the example layout 200 described above, a dual height cell (e.g., dual height cell 330) abuts a single height cell (e.g., single height cell 310) with an offset of half the standard cell height .

As described above, for example, utilizing a fill area (e.g., fill area 220) to facilitate shifting of dual height cells may result in underutilization of disadvantageous semiconductor wafer areas.A fill area (e.g., fill area 220) may include unused fins and/or may provide little or no functionality.thus, for example, a semiconductor wafer area dedicated to the fill area may not contribute to chip functionality.A semiconductor device layout employing dual height cell shifting, for example, embodiments may include or more fractional height cells.A "fractional height" may refer to a height that includes a non-integer multiple of a standard height.A fractional height cell (e.g., cell 320) may have a height that is about 1.5 times the height of a single height cell (e.g., cell 310). in embodiments, the use of a fractional height cell may allow the use of an area of a semiconductor wafer that may otherwise be used to fill an area in some cases.g., in exemplary layout 200 may be replaced by at least a fractional height cell (e.g., cell 320) that may be used in some cases to replace a fractional height cell in a single height cell library of a semiconductor wafer area (e.g., a fractional height cell 320).

In embodiments, an increased number of available fins may be generated by replacing the single height cell and the fill area with fractional height cells, for example, by converting fill area fins to active fins and/or utilizing fins located below the power rail, a fractional height cell having a height of about 1.5 times the height of the single height cell may be twice or more the number of fins of a particular diffusion type as compared to the number of fins of a particular diffusion type in the single height cell in embodiments, a 1.0 height cell may include, for example, 2 n-type fins and2 p-type fins, further, for example, in embodiments, a 1.5 height cell may include 2 p-type fins and may include 6 n-type fins, in another embodiment, for example, a 1.5 height cell may include 2 n-type fins and may include 6 p-type fins, further , in embodiments, a fractional height cell may have a height that is not an integer multiple of the height of the single height cell, wherein the fractional height cell height is greater than the single height cell, further, in embodiments, the fractional height cell may achieve a specific increased performance of the unit (e.g., increased) may result in an overall increased performance of the conversion cell, such as discussed below, in 39320).

For example, in addition to providing an increase in drive strength by replacing single height cells and fill regions with fractional height conversion cells (e.g., due to an increase in the number of available fins), embodiments may also provide the advantage of greater device density per unit area for semiconductor devices in embodiments, the greater device density per unit area may yield various potential advantages, including such things as reduced cost, improved circuit performance, reduced power consumption, and the like.

Fig. 4 is a diagram depicting an example layout 400 for at least portions of a semiconductor device, for example, semiconductor device layout 400 includes a plurality of single height cells (e.g., cell 410 and/or cell 411), and an example 2.5 height cell 425 and an example 1.5 height conversion cell 415, further, like the example layouts 200 and/or 300 described above, a single cell (e.g., cell 410, 411, 415, and/or 425) such as may include a plurality of diffusion type fins and another plurality of second diffusion type fins, as shown in example layout 400. in embodiments, a 2.5 height cell (e.g., cell 425) directly abuts (e.g., does not use a conversion cell) a single height cell (e.g., single height cell 410). in embodiments, to abut another specific single height cells (e.g., single height cell 411), a conversion cell (e.g., 1.5 height cell 415) may be used.

Additionally, in embodiments, for example, the 2.5 height cell may include additional fins, as compared to a dual height cell, due at least in part to the filler cell pins being converted to active fins and due at least in part to the utilization of fins in the conversion region that would otherwise be idle, hi embodiments, utilizing fins under the supply voltage and/or common source electrode and/or utilizing fins in the conversion region may allow for an increase in the number of active fins and thus increase semiconductor wafer area utilization.

Fig. 5 is a diagram illustrating an embodiment 500 of an exemplary finFET semiconductor device layout, including standard height cells (e.g., cell 510) and dual height cells (e.g., cell 520), as shown in exemplary layout 500, standard height cells (e.g., cell 510) and/or dual height cells (e.g., cell 520) may include a plurality of p-type fins (e.g., fin 580) and a plurality of n-type fins (e.g., fin 570). as also depicted in exemplary layout 500, various cells (e.g., standard height cells 510 and/or dual height cells 520) may include a plurality of fingers (e.g., finger 560) aligned in a direction substantially orthogonal to fins 570 and/or 580. exemplary layout 500 also illustrates elements including metal layers of voltage supply electrodes 501 and/or 502. in embodiments, voltage supply electrodes may include common source (VSS) electrodes, and voltage supply electrodes may include such as supply Voltage (VDD) electrodes, and voltage supply electrodes 502 may include such as supply Voltage (VDD) electrodes, also depicted in exemplary layout 500. in other embodiments, the subject matter of the present invention may be applied to any of the inter-level configuration of the subject matter of the present disclosure, and/or other inter-level configurations, for example, and/or inter-layer configurations, and/or inter-layer arrangements, such as may be applied to any of the subject matter of the present subject matter of the subject matter described herein, for example, and/or other, and/or to be applied to the subject matter of the present disclosure, for example, and/or to the like, and/or to be applied to the present disclosure, for example, and/or to the exemplary layout 500.

As shown in exemplary layout 500, in instances, a combination of single height cells (e.g., cell 510) and/or dual height cells (e.g., cell 520) may be implemented with filler cells (e.g., cell 531 and/or 535) . for example, filler cells 531 and/or 535 may include, for example, unused fins, such as fin 540, and may also include, for example, half-filled cell region 530. As described above, fins within the filled region (e.g., fins within regions 530 and/or 540) may not be used in some cases, such as exemplary layout 500. furthermore, fins below the supply voltage electrode of a single height cell (e.g., fins below VSS electrode 501 of single height cell 510 and/or fins below VDD electrode 502) may not be used in exemplary layout 500.

For exemplary layout 500, a single height cell (e.g., cell 510) may include 2N-type fins (e.g., N-type fin 570) and 2P-type fins (e.g., P-type fin 580). further, for exemplary layout 500, a dual height cell (e.g., dual height cell 520) may include 6N-type fins (e.g., N-type fin 570) and 6P-type fins (e.g., P-type fin 580). for every of cells 510 and/or 520, the ratio of P-type fins to N-type fins (e.g., "β" ratio P/N) may include a 1: 1 ratio.

As described above, a dual height cell (e.g., dual height cell 520) may be referred to as a "dual height cell with NWELL offset". In embodiments, a p-type fin (e.g., fin 580) may be formed over an NWELL structure within a substrate.in embodiments, a dual height cell (e.g., cell 520) including an NWELL region may be characterized at least in part by embedded power rails (e.g., power rails 501 and 502). for example, as shown in FIG. 5, for dual height cell 520, power rails 501 and/or 502 may be inserted so as to align with corresponding power rails of other cells within a logic block.

Fig. 6 is an illustration of an embodiment 500 depicting an example finFET layout including an example fractional height conversion cell (e.g., cell 610), in embodiments, layout 600 may share similarities with example layout 500 discussed above, for example, a dual height cell (e.g., cell 520) may include a plurality of p-type fins (e.g., fin 580) and a plurality of n-type fins (e.g., fin 570). further, example layout 500 may include a plurality of fingers (e.g., finger 560) aligned in a direction substantially orthogonal to fins 570 and/or 580. example layout 600 also shows portions of metal layers including voltage supply electrodes 501 and/or 502. example layout 600 also depicts interlayer interconnects 505. as described above, circuit input terminals a and/or B and associated metal layer electrodes and/or interlayer interconnects 505 are merely examples, and claimed subject matter is not limited in scope to any particular arrangement, configuration, and/or number of interlayer interconnects, for example, claimed subject matter is not limited in scope to any particular arrangement, configuration, and/or other claimed subject matter is not limited in scope, for example, in scope, in relation to other claimed subject matter 610, such as claimed subject matter.

In embodiments, exemplary layout 600 may include a fractional height conversion cell (e.g., cell 610) and/or a combination of dual height cells (e.g., cell 520). In addition, exemplary layout 600 also depicts that fins from semi-standard cell height fill area 530 and from below supply voltage electrode 502 are incorporated into a fractional height conversion cell (e.g., cell 610). for exemplary layout 500, a fractional height conversion cell (e.g., cell 610) may include 2 n-type fins (e.g., n-type fin 570) and 6 p-type fins (e.g., p-type fin 580). furthermore, for exemplary layout 600, as in example 500 discussed above, a dual height cell (e.g., dual height cell 520) may include 6 n-type fins (e.g., n-type fin 570) and 6 p-type fins (e.g., p-type fin 580). for cell 520, the value of the ratio of p-type fins to n-type fins β may be 1.0. for fractional height conversion cell 610, at least in part due to the fact that the fractional height conversion cell 502 and the fractional fin ratio of n-type fins in the area 502 and n-type fin area 630 is not limited by the subject matter of the range of the fractional height conversion cell 600, which is about 2.2 and β.

As can be seen by examining the example layout 500 of fig. 5 and the example layout 600 of fig. 6, implementing a fractional height conversion cell (e.g., cell 610), rather than implementing a single height cell and corresponding fill area, may incorporate and/or use a greater number of fins for similar semiconductor wafer areas.

Fig. 7 is an illustration of an embodiment 700 depicting an exemplary single height NAND cell layout for an exemplary cell library in embodiments, the exemplary layout 700 can include a plurality of p-type diffusion fins (e.g., p-type fins 755) and/or a plurality of n-type diffusion fins (e.g., n-type fins 750). furthermore, in embodiments, the exemplary single height NAND cell layout 700 can include a plurality of fingers (e.g., fingers 760) aligned in a direction substantially orthogonal to fins 755 and/or 750.

In embodiments, exemplary single height NAND cell layout 700 may include 2 n-type fins (e.g., n-type fin 750), and/or may include 2 p-type fins (e.g., fin 755) with a β ratio of 1: 1. furthermore, in embodiments, an exemplary single height NAND cell layout (e.g., layout 700) with a poly-half offset structure may exhibit a contact poly pitch value of 5. for example, in terms of a plurality of polysilicon fingers arranged according to a particular pitch size of a particular cell library of a particular cell, "contact poly pitch" (CPP) may be used to describe the width of a cell (e.g., cell 510). for exemplary layout 700, CPP is 5, with 2 n-type fins 750 and2 p-type fins.

In embodiments, exemplary layout 800 may include a plurality of p-type diffusion fins (e.g., p-type fins 855) and/or a plurality of n-type diffusion fins (e.g., n-type fins 850). further, in embodiments, exemplary fractional height NAND cell layout 800 may include a plurality of fingers (e.g., fingers 860) aligned in a direction substantially orthogonal to fins 855 and/or 850. similar to exemplary layout 600 discussed above, exemplary fractional height NAND cell layout 800 may include a metal layer including input terminals A, B and C, and VSS electrode 801 and VDD electrode 802.

In embodiments, exemplary fractional height NAND cell layout 800 may include 6 n-type fins (e.g., n-type fins 850), and/or may include 2 p-type fins (e.g., fins 855) with a β ratio of 0.33 in addition, in embodiments, exemplary fractional height NAND cell layout 800 may exhibit a cell area value of 7.5CPP (5CPP multiplied by 1.5 height). in contrast, to create a single height cell with 6 n-type fins, active transistors (e.g., A, B and C poly) are folded (e.g., additional poly fingers are added to the widened cell) 3 times, resulting in a unit area value of 11CPP (e.g., 3 fingers for the active transistor are folded 3 times plus 2 dummy poly fingers on both sides). it is apparent that in embodiments, the 7.5 area value for exemplary fractional height NAND cell layout 800 is a smaller area value than the 11 area value for exemplary single height NAND cell layout 600, and its fractional height density is greater for CPP devices.

For example, another potential advantages that may be realized by utilizing fractional height conversion cells (e.g., exemplary cells 610 and/or 800) may include speeding up relatively slow stacked transistors in cells used generally at , including but not limited to NAND2, NAND3, NAND4, NOR2, NOR3, NOR4, AOI31, AOI211, OAl31, OAI211, etc. for example, rather than utilizing single height cells having the same number of n-type and/or p-type fins, embodiments may include fractional height cells that include a greater number of n-type and/or p-type fins.

For example, although single height cells, 1.5 height cells, and/or dual height cells have been described in connection with embodiments herein, other embodiments may include other cell heights, such as 2.5, for example, in embodiments, a β ratio of fractional height conversion cells having a height 2.5 times the height of a standard cell may be characterized by a β ratio of 1.67 (including 10 p-type fins and 6 n-type fins), of course, the claimed subject matter is not limited by the scope of these aspects.

Fig. 9 depicts an illustration of an embodiment 800 of an exemplary process for forming fractional height finFET cells on a semiconductor wafer. Embodiments in accordance with the claimed subject matter may include all blocks 910 through 960, less than blocks 910 through 960, and/or more than blocks 910 through 960. Further, the order of blocks 910-960 is merely an exemplary order, and the subject matter is not limited in scope in these respects.

In embodiments, as shown at block 910, specifications for a th finFET cell type of th height may be read from a library of cells stored in a memory of a computing device based at least in part on the particular semiconductor device layout in addition, in embodiments, as shown at block 920, at least cells of a th finFET cell type of th height may be formed on the semiconductor wafer based on the particular semiconductor device layout in addition, as shown at blocks 930 and 940, specifications for a second finFET cell type of a second height may be read from the library of cells and, for example, at least cells of the second finFET cell type of the second height may be formed on the semiconductor wafer based on the particular semiconductor device layout.

Also, at least cells of a third finFET cell type of the third height are formed on the semiconductor wafer according to the particular semiconductor device layout, as shown at block 960, wherein in embodiments the third height is a non-integer multiple of the th height, and wherein the third height is greater than the th height.

In embodiments, forming at least cells of a third finFET cell type of a third height may include providing a transition between at least cells of a finFET cell type of a height and at least cells of a second finFET cell type of a second height embodiments the height may include a standard cell height specified by a cell library and the second height may include, for example, a dual cell height, further in embodiments the third cell height may include a transition cell height such as about 1.5 times the standard cell height.

In embodiments, forming at least cells of a third FinFET cell type of a third height may include forming a 2 th plurality of fins of a 1 th diffusion type aligned in a 0 th direction and a second plurality of fins of a second diffusion type aligned in a 3 th direction further, in embodiments, for example, the th plurality of fins of a th diffusion type may be greater in number than the second plurality of fins of the second diffusion type further, forming the th plurality of fins of a th diffusion type may include forming or more of the th plurality of fins of a th diffusion type located below the supply voltage electrode.

In the context of this patent application, the term "connection," the term "component," and/or similar terms are intended to be physical, but not always tangible.

Thus, in particular contexts of use, such as where tangible components are being discussed, the terms "coupled" and "connected" are used in a manner such that the terms are not synonymous.A similar term may also be used in a manner in which a similar intent is exhibited.

In this patent application, in a particular use environment, such as where tangible components (and/or similarly, tangible materials) are discussed above, a distinction is made between "on.. and" over.. as examples, depositing a substance on a substrate refers to deposition that involves no direct physical and tangible contact between the deposited substance and the substrate (e.g., an intermediate substance), however, depositing "over" the substrate is understood to potentially include depositing "on" the substrate (as "on.. can also be accurately described as" over.. and "including where or more intermediates are understood).

In a particular use environment where appropriate, a similar distinction is made between "under a.

It should also be understood that terms such as "above" and "below" as used herein are to be interpreted in a manner similar to the aforementioned terms "upward," "downward," "top," "bottom," and the like, which terms may be used to facilitate discussion, but are not intended to necessarily limit the scope of the claimed subject matter.

It should also be noted that the terms "type" and/or "analog," as used herein, such as where the feature, structure, characteristic, and/or analog is referred to, at least in part, and/or in such a manner as to present minor variations (even perhaps not otherwise considered a variation due to the entirety of with the feature, structure, characteristic, and/or analog), do not normally prevent the feature, structure, characteristic, and/or analog from being "type" and/or "analog," if minor variations are small enough such that the feature, structure, characteristic, and/or analog would still be considered substantially as present such variations as are present.

In the context of this patent application, unless otherwise indicated, the term "or" if used in connection with a list, e.g., A, B or C is intended to mean A, B and C, where an inclusive meaning is used, and A, B or C is intended to be used, an exclusive meaning is used, hi accordance with such an understanding, "and" is used in an inclusive sense and is intended to mean A, B and C, and "and/or" may be used with sufficient caution to indicate that all of the aforementioned meanings are intended, although such usage is not required.

Further, for the case where embodiments of the claimed subject matter are involved and are constrained by tests, measurements, and/or specifications on degree, it is intended to be understood in the following manner as examples, in a given case, it is assumed that values of the physical property are to be measured if alternative rational methods of testing, measuring, and/or specification on degree are reasonably possible for a person of ordinary skill, at least for attribute purposes, the examples are continued, at least for implementation purposes, unless explicitly stated otherwise, the claimed subject matter is intended to encompass those alternative rational methods.

Subject matter is directed to or more specific measures within the scope of the claimed subject matter, such as with respect to a physical manifestation capable of being physically measured, such as but not limited to, temperature, pressure, voltage, current, electromagnetic radiation, and the like, with the proviso that the claimed subject matter does not conform to the abstract notional exception of legal subject matter.

Thus, for a given measurement, for example, components may include deterministic components that may ideally include physical values typically in the form of or more of the signals, signal samples, and/or states (e.g., found by or more measurements), and components may include stochastic components that may have various sources that may be difficult to quantify.

In the preceding description, various aspects of claimed subject matter have been described. For purposes of explanation, details such as quantities, systems, and/or configurations are set forth as examples. In other instances, well-known features are omitted and/or simplified in order not to obscure claimed subject matter. While certain features have been illustrated and/or described herein, many modifications, substitutions, changes, and/or equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and/or changes as fall within the claimed subject matter.