trimming circuits
阅读说明：本技术 一种修调电路 (trimming circuits ) 是由 张明 王新安 汪波 焦炜杰 杨金权 马学龙 于 2018-07-19 设计创作，主要内容包括：本专利申请提供一种修调电路,PAD通过金属线连接金属熔丝FUSE、电阻R1,金属熔丝FUSE另一端接地,电阻R1的另一端接反相器Ⅰ(CMOS1)输入端,反相器Ⅰ(CMOS1)的输出端接或门的输入端A,或门的输入端B接比较器U的输出端,比较器U的输入端接探针,或门的输出端接MOS管Ⅰ的栅极,MOS管Ⅰ的源极接电源AVDD、漏极接MOS管Ⅱ源极,MOS管Ⅱ的栅极接控制部分、漏极接控制offset的调整部分,本专利申请通过探针引入电流至PAD,烧断金属熔丝,电流经电阻R1、反相器Ⅰ(CMOS1)后,高电平变低电平,而经比较器至或门B输入端的电平为高电平,MOS管Ⅰ、MOS管Ⅱ导通,修调offset,同时还可根据控制部分输入的信号切换至控制负offset的调整部分的修调,利用上述结构进行芯片的失调电压以及温漂的调整,在微小的代价下,提高芯片的性能指标。(The application provides trimming circuits, wherein, the PAD is connected with a metal FUSE FUSE and a resistor R1 through a metal wire, the other end of the metal FUSE FUSE is grounded, the other end of the resistor R1 is connected with the input end of an inverter I (CMOS 1), the output end of the inverter I (CMOS 1) is connected with the input end A of or the input end B of is connected with the output end of a comparator U, the input end of the comparator U is connected with a probe or the output end of is connected with the grid of an MOS tube I, the source of the MOS tube I is connected with a power supply AVDD, the drain is connected with the source of the MOS tube II, the grid of the MOS tube II is connected with a control part and the drain is connected with an adjusting part for controlling offset, the current is introduced to the PAD through the probe, the metal FUSE is blown, the high level becomes low after the current passes through the resistor R1 and the inverter I (CMOS 1), the level of the input end of the comparator or B is high level, the MOS tube I and the MOS tube are conducted, the offset is adjusted, and the offset of the voltage of the chip is adjusted by utilizing the above-mentioned indexes, and the small offset of the chip.)
The trimming circuit comprises a trimming circuit (4) and a probe (5), and is characterized in that the trimming circuit (4) is arranged on a chip (1), the trimming circuit (4) is connected with a bonding pad (3) in a scribing groove (2) through a lead, and the probe (5) is connected with the bonding pad (3) and used for introducing current to the bonding pad (3).
2. The trimming circuits of claim 1, wherein the trimming circuit (4) includes a metal FUSE FUSE, a resistor R1, an inverter I (CMOS 1), a MOS transistor I, a MOS transistor II, a comparator U, or , the pad (3) is connected with the metal FUSE FUSE, the resistor R1 through a metal wire, the other end of the metal FUSE FUSE is grounded, the other end of the resistor R1 is connected with the input end of the inverter I (CMOS 1), the output end of the inverter I (CMOS 1) is connected with the input end A of the , or the input end B of the is connected with the output end of the comparator U, the input end of the comparator U is connected with a probe, or the output end of the is connected with the gate of the MOS transistor I, the source AVDD and the drain of the MOS transistor II are connected with the source of the MOS transistor II, the gate of the MOS transistor II is connected with the control portion, and the drain is connected with the adjustment portion for.
3. The trimming circuits of claim 2, further comprising a trimming portion for controlling negative offset, wherein the trimming portion for controlling negative offset comprises an inverter II (CMOS 2) and a MOS transistor III, the gate of the MOS transistor II is connected to the input terminal of the inverter II (CMOS 2) through a lead, the output terminal of the inverter II (CMOS 2) is connected to the gate of the MOS transistor III, the source of the MOS transistor III is connected to the common terminal of the drain of the MOS transistor I and the source of the MOS transistor II through a lead, and the drain of the MOS transistor III is connected to the trimming portion for controlling negative offset.
4. The trimming circuits of claim 2, wherein the resistor R1 is connected to the common terminal of the inverter (CMOS 1) and further connected to a power supply VDD via a lead.
5. The trimming circuit of claim 2, wherein the metal FUSE FUSE is buried in a passivation layer on the surface of the scribe line (2).
Technical Field
The application relates to the field of semiconductors, in particular to trimming circuits, which are used for adjusting offset voltage (offset) and temperature drift of the offset voltage, and improving the overall performance index of a chip at a small cost.
Background
With the development of integrated circuit processes and design technologies, circuit performance requirements are higher and higher in order to meet the application requirements of , but circuit characteristics are always affected by non-ideal factors of a semiconductor manufacturing process, the parasitic effects are mainly shown in the aspects of current mirror mismatch, resistance matching deviation, temperature coefficient of resistance, resistance-capacitance mismatch, absolute resistance deviation, temperature coefficient of resistance, resistance-capacitance mismatch, transistor mismatch, temperature drift offset and input offset voltage caused by package stress, and the errors are random, exist between chips, between wafers and between batches, cannot be effectively simulated and predicted through simulation software, and can be reduced by optimizing the process control accuracy in a targeted manner, but the process complexity and the manufacturing cost of the chips are increased.
In order to realize a high-precision analog integrated circuit on a standard process, adjustment after manufacturing of a chip becomes a mainstream solution for adjusting temperature drift, optimizing circuit performance and improving chip yield, the trimming technology is widely applied to a high-precision low-offset amplifier, a low-temperature ticket high-performance reference source, a radio frequency circuit, a high-performance AD/DA converter and a complex SoC chip, except for performance improvement, in order to realize different performances on the same chips, the circuit structure and blood parameters can be programmed through the trimming technology, so that different application requirements are met.
According to the literature, "ic trimming technology analysis, huangxiaozong, yuehai, huangwen just, and the future", the mainstream ic trimming technologies currently existing are laser trimming, fuse trimming, zener diode breakdown, electronic fuse and memory trimming, etc.
The basic principle of laser trimming is that a laser beam is focused on a resistive film through a lens, the resistive film is vaporized under the action of instantaneous high temperature, and cuts are formed on the resistive film along with the movement of the light beam under the action of continuous laser pulses, so that the conductive area (namely the number of resistor squares) of the resistor is changed, and the purpose of changing the resistor (increasing the resistance) is achieved.
The laser trimming is just as early as 1972, the trimming of a thick-film resistor is used, the thin-film resistor is usually made of nickel-chromium alloy or chromium-silicon alloy, the laser is locally heated, so that the microstructure or chemical composition of a local material is changed, the overall resistance is increased, the diameter of a laser beam spot is about a circular area of 3-10 um, the moving part of the laser beam spot is slightly different according to the precision of equipment, the laser spot is moved for laser bombardment, continuous fine adjustment is carried out, the change of the resistance value is continuously monitored, the trimming is stopped until satisfactory resistance is obtained, the precision is higher compared with other modes, the resistance precision can reach within 0.05 percent, the cost is high, and in essence, the laser trimming is also damages to a resistor body.
Content of the patent application
The application provides trimming circuits, which are used for adjusting chips after manufacturing, particularly adjusting temperature drift and improving the yield of the chips.
Preferably, the trimming circuit comprises a metal FUSE FUSE, a resistor R1, an inverter I (CMOS 1), a MOS transistor I, a MOS transistor II, a comparator U or 3, the metal FUSE FUSE and the resistor R1 are connected through a metal wire, the other end of the metal FUSE FUSE is grounded, the other end of the resistor R1 is connected with the input end of the inverter I (CMOS 1), the output end of the inverter I (CMOS 1) is connected with the input end A of or the input end B of is connected with the output end of the comparator U, the input end of the comparator U is connected with a probe or the output end of is connected with the gate of the MOS transistor I, the source electrode of the MOS transistor I is connected with the AVDD, the drain electrode of the MOS transistor II is connected with the source electrode, the gate electrode of the MOS transistor II is connected with the control part, and the drain.
Preferably, the apparatus further comprises an adjustment part adjusting part controlling the negative offset, wherein the adjustment part controlling the negative offset comprises: the gate of the MOS tube II is connected with the input end of the inverter II (CMOS 2) through a lead, the output end of the inverter II (CMOS 2) is connected with the gate of the MOS tube III, the source of the MOS tube III is connected with the common end of the drain of the MOS tube I and the source of the MOS tube II through a lead, and the drain of the MOS tube III is connected with the adjusting part for controlling the negative offset.
Preferably, the common terminal of the resistor R1 connected to the inverter i (CMOS 1) is further connected to the power supply VDD via a lead.
Preferably, the metal FUSE may be buried in a passivation layer on the surface of the scribe line.
The chip has the advantages that current is introduced to a PAD through a probe, a metal fuse is blown, the high level of the current is changed into low level after the current passes through a resistor R1 and an inverter I (CMOS 1), the level from a comparator to an input end or B is high level, an MOS tube I and an MOS tube II are conducted, offset is adjusted, meanwhile, the adjustment of an adjustment part for controlling negative offset can be switched according to signals input by a control part, the offset voltage and the temperature drift of the chip can be adjusted by using the structure, and the yield of the chip is improved.
Drawings
FIG. 1 is a schematic structural diagram of the present patent application;
FIG. 2 is a schematic diagram of a circuit utilizing the present patent application;
in the figure, 1, chip; 2. scribing a groove; 3. a pad; 4. a trimming circuit; 5. and (3) a probe.
Detailed Description
As shown in fig. 1, the present patent application includes: the probe 5 and the trimming circuit 4 are arranged on the chip 1, the trimming circuit 4 is connected through a metal wire, the probe 5 is connected with a current to a PAD (or PAD) 3 in the
The trimming circuit 4 shown in FIG. 2 comprises a metal FUSE FUSE, a resistor R1, an inverter I (CMOS 1), a MOS transistor I, a MOS transistor II, a comparator U or 3, the metal FUSE FUSE and the resistor R1 are connected through a metal wire, the other end of the metal FUSE FUSE is grounded, the other end of the resistor R1 is connected with the input end of the inverter I (CMOS 1), the output end of the inverter I (CMOS 1) is connected with the input end A of or the input end B of is connected with the output end of the comparator U, the input end of the comparator U is connected with a probe or the output end of is connected with the gate of the MOS transistor I, the source of the MOS transistor I is connected with a power supply AVDD, the drain is connected with the source of the MOS transistor II, the gate of the MOS transistor II is connected with a control part, and the.
Preferably, the common terminal of the resistor R1 connected to the inverter i (CMOS 1) is further connected to the power supply VDD via a lead.
Preferably, the apparatus further comprises an adjustment part adjusting part controlling the negative offset, wherein the adjustment part controlling the negative offset comprises: the gate of the MOS tube II is connected with the input end of the inverter II (CMOS 2) through a lead, the output end of the inverter II (CMOS 2) is connected with the gate of the MOS tube III, the source of the MOS tube III is connected with the common end of the drain of the MOS tube I and the source of the MOS tube II through a lead, and the drain of the MOS tube III is connected with the adjusting part for controlling the negative offset.
Preferably, the metal FUSE may be buried in a passivation layer on the surface of the
Preferably, the plurality of groups of independent trimming circuits may be provided in the wafer, and the trimming circuits may be located in different chips and scribe
In a normal state, namely in an initial state shown in fig. 2, the offset is not adjusted, namely, FUSE grounding, the voltage between the resistor R1 and the common terminal of FUSE is low level, the level between the resistor R1 and the common terminal of the inverter i (CMOS 1) is low (0), the low level is changed into high level (0 is changed into 1) after passing through the inverter i (CMOS 1), or the a input end of is high level, or the output end of is high level, the MOS transistor i does not meet Ugs >0 and is in a cut-off state, and the offset is not adjusted.
When the offset is adjusted, the control part gives a control signal (high level), the probe 5 introduces current to the PAD3, the metal FUSE FUSE is blown under the instantaneous voltage, the high level becomes low (1 becomes 0) after the current passes through the resistor R1 and the inverter I (CMOS 1), the level from the comparator to the input end of the transistor or B is high, the MOS transistor I and the MOS transistor II are conducted, and the offset is adjusted.
Similarly, when the adjustment part of the trimming control negative offset is time-shared, the control part gives a negative trimming control signal (low level), at this time, the MOS transistor ii is turned off, and after passing through the inverter ii (CMOS 2), the low level becomes high level, the MOS transistor iii is turned on, and the adjustment part of the trimming control negative offset.
It will be appreciated by those skilled in the art that modifications and variations can be made to the embodiments described above without departing from the spirit and scope of the present application, and therefore, and its equivalents may be covered by the claims of this application.
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