阅读说明：本技术 半导体器件和电子控制装置 (Semiconductor device and electronic control device ) 是由 相马治 于 2019-07-11 设计创作，主要内容包括：本公开涉及半导体器件和电子控制装置。提供了一种能够切断从负载到电源的反向电流的半导体器件和电子控制装置。功率晶体管QN1被提供在正电源端子Pi2(+)与负载驱动端子Po2(+)之间,并且具有耦合到正电源端子Pi2(+)的源极和背栅。功率晶体管QN2与功率晶体管QN1被串联提供,并且功率晶体管QN2的源极和背栅耦合到负载驱动端子Po2(+)。升压器CP1a对功率晶体管QN1的栅极充电。当负电源端子Pi2(-)的电位高于正电源端子Pi2(+)的电位时,栅极放电电路DCG1a将功率晶体管QN1的栅极电荷放电到源极。(A power transistor QN1 is provided between a positive power terminal Pi2(+) and a load driving terminal Po2(+) and has a source and a back gate coupled to the positive power terminal Pi2 (+). A power transistor QN2 is provided in series with a power transistor QN1, and the source and the back gate of the power transistor QN2 are coupled to a load driving terminal Po2 (+). A booster CP1a charges a gate of the power transistor QN 1. when a potential of the negative power terminal Pi2(-) is higher than a potential of the positive power terminal Pi2(+), a gate discharge circuit DCG1a discharges a gate charge of the power transistor QN1 to the source.)

1, semiconductor device, comprising:

a positive power supply terminal and a negative power supply terminal coupled to a power supply; and

a load drive terminal coupled to a load;

wherein a source and a back gate of an th power transistor are coupled to the positive power supply terminal side, and a drain of the th power transistor is coupled to the load drive terminal side, and

wherein a source and a back gate of a second power transistor are coupled to the load drive terminal and a drain of the second power transistor is coupled to the positive power supply terminal; and

a th boost circuit for charging the gate of the th power transistor, and

an th gate discharge circuit for discharging the th power transistor's gate potential to the source when the potential of the negative power supply terminal is higher than the potential of the positive power supply terminal.

2. The semiconductor device as set forth in claim 1,

wherein the semiconductor device is formed by a semiconductor package.

3. The semiconductor device as set forth in claim 2,

wherein the th gate discharge circuit includes an n-channel type shorting transistor for shorting the gate to the source of the th power transistor when the potential of the negative power supply terminal is higher than the potential of the positive power supply terminal.

4. The semiconductor device of claim 3, further comprising:

a negative potential detection circuit for determining whether a negative potential applied to the positive power supply terminal is on a positive side or a negative side of a predetermined negative threshold potential with respect to the negative power supply terminal, and for controlling the shorting transistor to be turned on in case of the positive side, and for controlling the shorting transistor to be turned off in a second case of the negative side.

5. The semiconductor device as set forth in claim 4,

wherein the negative potential detection circuit has an th resistor and a th zener diode provided in series between the positive power supply terminal and the negative power supply terminal, and the negative potential detection circuit determines whether the negative threshold potential is on the positive side or the negative side by detecting whether the th zener diode breaks down.

6. The semiconductor device as set forth in claim 4,

wherein the negative potential detection circuit has a second zener diode having a terminal coupled to the positive power supply terminal, and in the second semiconductor device, a potential that is positive by a breakdown voltage of the second zener diode with respect to the potential of the positive power supply terminal is applied to a gate of the th power transistor via the th boosting circuit.

7. The semiconductor device as set forth in claim 4,

wherein the th power transistor has a lower stress structure than the second power transistor.

8. The semiconductor device as set forth in claim 3,

wherein the shorting transistor is turned off when the potential of the positive power supply terminal is applied to the gate during an active period of the control input signal, and the semiconductor device further includes a capacitor that maintains a gate potential of the shorting transistor during the active period of the control input signal during an inactive period of the control input signal.

9. The semiconductor device of claim 8, further comprising:

a control transistor provided between the positive power supply terminal and the gate of the short-circuit transistor, the control transistor controlling the gate of the short-circuit transistor to be in a high-impedance state by being controlled to be turned off in an inactive period of the control input signal.

10. The semiconductor device as set forth in claim 2,

wherein the th gate discharge circuit has a second resistor for passing a gate discharge current that is less than a gate charge current generated when the th boost circuit turns on the th power transistor.

11. The semiconductor device of claim 2, further comprising:

a second boost circuit for charging the gate of the second power transistor when the control input signal is asserted; and

a second gate discharge circuit to discharge the gate charge of the second power transistor to the source when the control input signal is deactivated.

12, an electronic control device, comprising:

a microcontroller and relay arrangement and a battery and load;

wherein the relay device includes:

a positive power supply terminal and a negative power supply terminal coupled to the battery; and

a load drive terminal coupled to a load;

wherein a source and a back gate of an th power transistor are coupled to the positive power supply terminal side, and a drain of the th power transistor is coupled to the load drive terminal side, and

wherein a source and a back gate of a second power transistor are coupled to the load drive terminal and a drain of the second power transistor is coupled to the positive power supply terminal; and

a th boost circuit for charging the gate of the th power transistor, and

an th gate discharge circuit for discharging the th power transistor's gate potential to the source when the potential of the negative power supply terminal is higher than the potential of the positive power supply terminal.

13. The electronic control device according to claim 12,

wherein the th gate discharge circuit includes an n-channel type shorting transistor for shorting the gate to the source of the th power transistor when the potential of the negative power supply terminal is higher than the potential of the positive power supply terminal.

14. The electronic control device according to claim 13,

wherein the relay device further comprises a negative potential detection circuit for determining whether a negative potential applied to the positive power supply terminal is on a positive side or a negative side of a predetermined negative threshold potential with respect to the negative power supply terminal, and for controlling the shorting transistor to be turned on in case of the positive side, and for controlling the shorting transistor to be turned off in a second case of the negative side.

15. The electronic control device according to claim 14,

wherein the negative potential detection circuit has an th resistor and a th zener diode provided in series between the positive power supply terminal and the negative power supply terminal, and the negative potential detection circuit determines whether the negative threshold potential is on the positive side or the negative side by detecting breakdown of the th zener diode.

16. The electronic control device according to claim 14,

wherein the negative potential detection circuit has a second Zener diode having a terminal coupled to the positive power supply terminal, and

wherein in the second case, a potential that is positive by a breakdown voltage of the second zener diode relative to the potential of the positive power supply terminal is applied to a gate of the th power transistor via the th boost circuit.

17. The electronic control device according to claim 14,

wherein the th power transistor has a lower stress structure than the second power transistor.

18. The electronic control device according to claim 14,

wherein when the potential of the positive power supply terminal is applied to the gate during an active period of the control input signal, the shorting transistor is turned off, and

wherein the relay device further has a capacitor that holds the gate potential of the short-circuiting transistor during an active period of the control input signal during an inactive period of the control input signal.

19. The electronic control device according to claim 18,

wherein the relay device further has a control transistor provided between the positive power supply terminal and the gate of the short-circuit transistor, an

Wherein the control transistor controls the gate of the shorting transistor to be in a high impedance state by being controlled to be turned off during an inactive period of the control input signal.

20. The electronic control device according to claim 12,

wherein the electronic control device is mounted on a vehicle.

Technical Field

The present disclosure relates to a semiconductor device and an electronic control apparatus, and for example, to a technique for cutting off a reverse current from a load to a power supply.

Background

In Japanese unexamined patent application publication No.2007-82374 (hereinafter "patent document 1"), kinds of power supply reverse connection protection circuits are disclosed which include an n-channel FET [1] and an n-channel FET [2] in order on the positive terminal side on a power supply path from the positive terminal of a battery to a power supply target, the drains of the FET [1] and the FET [2] being commonly connected, and gate voltages of the FET [1] and the FET [2] being generated by a charge pump circuit, the operating power supply being supplied from the drain side to the charge pump circuit.

In japanese unexamined patent application publication No.2003-37933 (hereinafter, "patent document 2"), kinds of protection devices are disclosed, which include a p-channel FET whose drain is on the power supply terminal side on the power supply path from the power supply terminal on the positive electrode side to the power supply input terminal of the electronic apparatus.

Disclosure of Invention

In an electronic control apparatus (electronic control unit) or the like for a vehicle, for example, a relay composed of two series transistors may be provided to control energization between a power source and a load of the two series transistors are required to break reverse conduction from the load to the power source in addition , it is desirable that the two series transistors are n-channel type transistors as shown in patent document 1 to reduce the size and loss of the relay.

The embodiments described below are made in consideration of the above circumstances, and other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

kinds of semiconductor devices according to embodiments include positive and negative power supply terminals coupled to a power supply, and a load drive terminal coupled to a load to control excitation between the power supply and the load in response to a control input, the semiconductor device includes n-channel 0 th and second power transistors, a th voltage boost circuit, and a th gate discharge circuit the th power transistor is provided between the positive power supply terminal and the load drive terminal, and has a source and a back gate coupled to the positive power supply terminal side, and a drain coupled to the load drive terminal side, the second power transistor is provided in series with the th power transistor between the positive power supply terminal and the load drive terminal, and the source and the back gate are coupled to the load drive terminal side, and the drain is coupled to the positive power supply terminal side, the th voltage boost circuit charges the gate of the th power transistor, the th gate discharge circuit discharges the gate charge of the th power transistor to the source when the potential of the negative power supply terminal is higher than the potential of the positive terminal.

According to the above-described embodiments, the reverse current supply from the load to the power supply can be cut off.

Drawings

Fig. 1 is a schematic diagram showing a configuration example of a vehicle to which an electronic control apparatus according to an th embodiment of the invention is applied;

fig. 2 is a schematic diagram showing an exemplary configuration of a main portion of the electronic control apparatus;

fig. 3 is a block diagram showing a schematic configuration example of a semiconductor device (relay apparatus) according to an th embodiment;

fig. 4 is a circuit diagram showing a detailed configuration example of a main portion in the semiconductor device (relay apparatus) in fig. 3;

fig. 5 is a cross-sectional view showing a configuration example of each transistor in the voltage applying circuit in fig. 4;

fig. 6 is a schematic diagram showing an outline of the semiconductor device (relay apparatus) in fig. 3;

fig. 7 is a block diagram showing a schematic configuration example of a semiconductor device (relay apparatus) according to the second embodiment;

fig. 8 is a circuit diagram showing a schematic configuration of a negative potential detection circuit in the semiconductor device (relay apparatus) in fig. 7;

fig. 9 is a circuit diagram showing a detailed configuration example of a main portion in the semiconductor device (relay apparatus) in fig. 7;

fig. 10 is a circuit diagram showing a configuration example when the circuit in fig. 9 is formed on a wiring substrate;

fig. 11 is a schematic diagram comparing the relay arrangement in fig. 7 with the relay arrangement according to fig. 10;

fig. 12 is a waveform diagram showing an example of a prerequisite problem in a semiconductor device (relay apparatus) according to the third embodiment;

fig. 13 is a block diagram showing a schematic configuration example of a semiconductor device (relay apparatus) according to a third embodiment;

fig. 14 is a circuit diagram showing a detailed configuration example of a main portion in the semiconductor device (relay apparatus) in fig. 13;

fig. 15 is a circuit diagram showing a detailed configuration example of the delay circuit in fig. 13;

fig. 16 is a waveform diagram illustrating an example of the operation of the circuit in fig. 14; and

fig. 17 is a schematic diagram ((a), (b), and (c)) showing different configurations of a relay device as a comparative example of th embodiment of the present invention.

Detailed Description

In the following embodiments, the description will be made by dividing into a plurality of sections or embodiments when for convenience sake, but these sections and embodiments are not independent from each other unless specifically stated, and sections and embodiments are related to modified examples, details, supplementary explanation, etc. of another section and embodiment, and part or all of them.

Further, in the following embodiments, it goes without saying that constituent elements (including element steps and the like) are not necessarily required unless they are specifically specified and unless they are considered to be clearly necessary in principle.

In addition, although a MOSFET (metal oxide semiconductor field effect transistor (referred to as MOS transistor)) is used as an example of a MISFET (metal insulator semiconductor field effect transistor) in the embodiment, a non-oxide film is not excluded as a gate insulating film.

In all the drawings for explaining the embodiments, the same members are denoted by the same reference numerals in principle, and the repetitive description thereof is omitted.

th embodiment

Fig. 1 is a schematic diagram showing an exemplary configuration of a vehicle to which an electronic control device according to the present embodiment is applied, a vehicle (e.g., a motor vehicle) VCL shown in fig. 1 includes a battery BAT, a fuse box FSU, an electronic control device (particularly, a relay box) ECU, a body control module BCM, and a plurality of loads LD [1],... No., LD [ k ],. No., LD [ n ]. the fuse box FSU is used to transmit electric power of the battery BAT to the electronic control device ECU and protect them from high current.

The loads LD [1] to LD [ n ] are various electrical components for automobiles, and correspond to, for example, DC motors, lamps, heaters, various inductive loads, various capacitor loads, and the like. The body control module BCM controls various loads, here LD [ k ],... and LD [ n ]. The electronic control device (relay box) ECU includes a plurality of relays (switches), and supplies the power of the battery BAT transmitted through the fuse box FSU to various loads (here, LD [1],...... -.) and the body control module BCM through the relays. That is, the electronic control unit ECU controls the excitation between the battery BAT and the load.

Here, it is desirable for the electronic control device ECU to have low loss with respect to supplying the electric power of the battery BAT to various loads. In addition, it is desirable that the electronic control unit ECU be compact. Since the restriction on the mounting position of the relay box is alleviated by the miniaturization, for example, the efficiency of the wiring route of the wire harness can be improved. The efficiency of routing helps to reduce weight, cost, wear, etc. of the vehicle.

Fig. 2 is a schematic diagram showing an exemplary configuration of a main portion of the electronic control apparatus in fig. 1. The electronic control unit ECU shown in fig. 2 includes a microcontroller MCU mounted on a printed circuit board, a relay unit RLY, a power supply regulator VREG, and an external resistor Re. The electronic control unit ECU supplies a battery power supply (also referred to as a battery power supply potential) VB on the high potential side from the battery BAT via a battery terminal Pi1(+) on the positive electrode side. The electronic control unit ECU supplies a low-potential-side battery power supply (also referred to as a ground power supply potential) GND from the battery BAT via a negative-side battery terminal Pi1 (-). When the ground power supply potential GND is 0V, the battery power supply potential VB is usually 12V or the like.

The power regulator VREG generates power (e.g., 5V) for the microcontroller MCU from the battery power supply VB. As is well known, a microcontroller MCU includes a memory for storing various programs and data, a processor for executing the programs stored in the memory, various analog peripheral circuits, and various digital peripheral circuits. The device RLY controls excitation between the battery BAT and the load LD IN response to a control input signal IN from the MCU. Specifically, the relay device RLY controls energization from the battery BAT to the load LD to be turned on when the control input signal IN is asserted (asserted) and turned off when the control input signal IN is de-asserted (negated).

In addition, the relay device RLY includes a diagnostic circuit for performing self-diagnosis. The relay device RLY outputs a result notification signal PF, which is a diagnostic result of the diagnostic circuit, to the microcontroller MCU. In this embodiment, when the diagnosis result is abnormal, the relay device RLY notifies the microcontroller MCU of the abnormality by controlling the potential level of the result notification signal PF to a predetermined level via the external resistor Re. The microcontroller MCU recognizes the abnormality by converting the potential level of the result notification signal PF into a digital signal by an analog-to-digital conversion circuit.

The load LD is coupled to the positive load drive terminal Po1(+) and the negative load drive terminal Po1(-) of the electronic control device ECU the output potential VO from the relay device RLY is applied to the load drive terminal Po1(+), and the ground power supply potential GND is applied to the load drive terminal Po1(-) and the battery terminal Pi1 (-).

Fig. 17(a), 17(b) and 17(c) are schematic diagrams showing different configuration examples of a relay device as a comparative example in fig. 2, for example, in the case where the load LD is a DC motor or the like, if the battery BAT is erroneously reverse-connected, reverse rotation (i.e., a failure) occurs due to the reversal of the excitation.

The relay device RLY' a shown in fig. 17(a) includes a mechanical switch (mechanical relay) MSW for energizing the load LD. Since mechanical switch MSW is mechanically opened at OFF, when battery BAT is reversely connected, the reverse current supply can be cut OFF. However, when the mechanical switch MSW is used, it is difficult to miniaturize the mechanical switch MSW, so that the installation position of the relay device RLY' a may be limited. In addition, since the mechanical switch MSW has a contact life, the installation position of the relay device RLY' a may be limited due to maintenance.

The relay device RLY' b shown in fig. 17(b) includes a diode Dr and an n-channel type power transistor (e.g., MOSFET) QN2 coupled in series, and the series circuit energizes the load LD. The back gate and source of the power transistor QN2 are coupled to the load LD, and the on/off of the power transistor QN2 is controlled by the driver DV that receives the control input signal IN. The power transistor QN2 includes a parasitic diode Dn2 between the source (back gate) and the drain, the parasitic diode QN2 having a cathode on the drain side (anode on the source side). Therefore, for example, when the battery BAT is reversely connected, the power transistor QN2 is reversely excited by the parasitic diode Dn2 even if the battery BAT is in an off state.

Thus, a diode Dr having the power transistor QN2 as a cathode is provided. When the battery BAT is connected in reverse, the diode Dr may cut off the reverse current unless it breaks down. As described above, by using the semiconductor element Dr and the semiconductor element QN2, the size of the relay device RLY' b can be reduced as compared with the case of using the mechanical switch MSW. However, when the diode Dr is used, when a forward current (i.e., a current from the battery BAT to the load LD) is supplied, a loss accompanying a forward voltage occurs, and thus there is still a problem from the viewpoint of reducing the loss.

In the relay device RLY' c shown in fig. 17(c), a p-channel type power transistor (e.g., MOSFET) QP1 is provided in place of the diode Dr. power transistor QP1 shown in fig. 17(c) with a parasitic diode Dp1, the source of the parasitic diode Dp1 being coupled to the power transistor QN2 side and the cathode of the parasitic diode Dp1 being the power transistor QN2 side, the power transistor QP1 is turned on when the gate of the power transistor QP1 is coupled to the negative battery terminal Pi1(-) and the battery BAT is connected in turn, the power transistor QP1 is turned on, on the other , when the battery BAT is connected in the reverse direction, the power transistor QP1 is turned off, the parasitic diode Dp1 of the power transistor BAT is also reverse-biased, thereby cutting off the reverse current source.

However, when the p-channel type is used, the on-resistance in the region of increases as compared with the case of using the n-channel type, as a result, it is disadvantageous in terms of miniaturization or low loss as compared with the case of using the n-channel type.

Fig. 3 is a block diagram showing a schematic configuration of a semiconductor device (relay apparatus) according to an th embodiment, the semiconductor device (relay apparatus) RLYa shown IN fig. 3 is an Intelligent Power Device (IPD) constituted by semiconductor packages, and is applied to the relay apparatus rly shown IN fig. 2. the relay apparatus RLYa includes a positive power terminal Pi2(+) and a negative power terminal Pi2(-) coupled to a power supply, a positive load drive terminal Po2(+) coupled to a load LD, and another terminal of the load LD to which a control input signal IN is input is coupled to a negative load drive terminal Po2 (-).

The positive power supply terminal Pi2(+) is coupled to the power supply (supply potential) [1a ] VD1a, and the negative power supply terminal Pi2(-) is coupled to the power supply (supply potential) [3] VD 3. The negative-side load drive terminal Po2(-) is coupled to a power supply (power supply potential) [2] VD 2. As shown in fig. 2, when the battery BAT is coupled to the positive power supply terminal Pi2(+) and the negative power supply terminal Pi2(-), the power supply potential [1a ] VD1a becomes the battery power supply potential VB, and the power supply potential [3] VD3 becomes the ground power supply potential GND. The power supply potential [2] VD2 is also the ground power supply potential GND. The power supply [3] VD3 serves as a ground power supply for control, and the power supply [2] VD2 serves as a ground power supply for power supply.

The relay device RLYa includes an input buffer IBF, a level shifter LS, a control circuit CTLa, boost circuits CP1a and CP2, a backflow prevention circuit RCF, gate discharge circuits DCG1a and DCG2, and power transistors QN1 and QN 2. The circuit RCF turns on the power supply [1a ] VD1a and the power supply [1b ] VD1b when the circuit RCF is "VD 1a > VD 3" (i.e., the battery BAT is connected in the forward direction), and turns off the power supply [1a ] VD1a and the power supply [1b ] VD1b when the circuit RCF is "VD 1a < VD 3" (i.e., the battery BAT is connected in the reverse direction). The power supply (power supply potential) [1b ] VD1b is a high potential internal power supply (internal power supply potential).

The power transistors QN1 and QN2 are, for example, n-channel MOSFETs. The power transistor QN1 is provided between the positive power terminal Pi2(+) and the positive load drive terminal Po2(+), and its source and back gate are coupled to the positive power terminal Pi2(+) side and its drain is coupled to the load drive terminal Po2(+) side. The power transistor QN2 is provided in series with the power transistor QN1 between the positive power terminal Pi2(+) and the positive load drive terminal Po2(+) and has a source and a back gate (+) coupled to the load drive terminal Po2(+) side and a drain coupled to the positive power terminal Pi2(+) side. An output potential VO corresponding to the on/off states of the power transistors QN1, QN2 is applied to the positive load drive terminal Po2 (+).

The input buffer IBF receives the control input signal IN from the control input terminal Pi3, and outputs the control input signal IN to the control circuit CTLa via the level shifter LS. The level shifter LS converts the control input signal IN, which varies at a predetermined amplitude when the ground power supply potential GND is set to the "L" level, into a signal, which varies at a predetermined amplitude when the power supply potential [1b ] VD1b is set to the "H" level. The control circuit CTLa operates with reference to a power supply (power supply potential) [4] VD4, and the control circuit operates with the power supply [1b ] VD1 b. The power supply [4] VD4 is an internal ground power supply IGND, and is generated by, for example, lowering the power supply [1b ] VD1b by a predetermined potential. For example, when the power supply potential [1b ] VD1b is 12V, the power supply potential [4] VD4 is 6V, and the like. The power supply [4] VD4 is a variable power supply and is shorted to the power supply [1b ] VD1b during standby to save power.

IN response to the control input signal IN, the control circuit CTLa outputs an enable signal S _ EN1 to the boost circuit CP1a and outputs an enable signal S _ EN2 to the boost circuit CP 2. Specifically, for example, when the control input signal IN is enabled, the control circuit CTLa enables both the enable signals S _ EN1 and S _ EN2, and when the control input signal IN is disabled, the control circuit CTLa disables both the enable signals S _ EN1 and S _ EN 2.

The booster circuits CP1a and CP2 are operated with the power supply [1b ] VD1b with reference to the power supply (power supply potential) [5] VD 5. The power supply [5] VD5 is an internal ground power supply IGND, and is generated and controlled in the same manner as the power supply [4] VD 4. The booster circuit CP1a generates a boosted potential (specifically, a power supply potential higher than the power supply potential [1a ] VD1a) in response to the assertion of the enable signal S _ EN1 to turn on the power transistor QN1, and charges the gate of the power transistor QN1 with the boosted potential. Similarly, the boost circuit CP2 generates a boosted potential to turn on the power transistor QN2 in response to the assertion of the enable signal S _ EN2, and charges the gate of the power transistor QN2 with the boosted potential.

When the potential of the negative power terminal Pi2(-) is higher than the potential of the positive power terminal Pi2(+) (i.e., when the battery BAT is reversely connected), the gate discharge circuit DCG1a discharges the gate charge of the power transistor QN1 to the source), in other , unlike the gate discharge circuit DCG1a, the gate discharge circuit DCG2 discharges the gate charge of the power transistor QN2 to the source in response to the invalidation of the enable signal S _ EN 2.

Fig. 4 is a circuit diagram showing a detailed configuration example of a main portion in the semiconductor device (relay apparatus) of fig. 3, showing the main portion of the relay apparatus ( th embodiment) fig. 5 is a cross-sectional view showing an example of a structure of a transistor in the booster of fig. 4 shows a detailed configuration around the backflow preventing circuit RCF, the boosting circuit CP1a, and the gate discharge circuit DCG1a in fig. 3. the backflow preventing circuit RCF includes a backflow preventing diode Dc and a pMOS transistor MP1 coupled in parallel between the power supply [1a ] VD1a and the power supply [1b ] VD1 b.

Here, when the battery BAT is reversely connected, a current may flow from the power supply [3] VD3 to the power supply [1b ] VD1b backward via the ESD protection diode De1, which is forward biased, and a current may flow from the power supply [1b ] VD1b to the power supply [1a ] VD1a backward. Therefore, the backflow prevention diode Dc prevents a current from flowing from the power supply [1b ] VD1b back to the power supply [1a ] VD1 a. However, in the backflow prevention diode Dc, when the battery BAT is forward-connected, a forward voltage drop occurs. Therefore, the gate of the pMOS transistor MP1 is coupled to the power supply [3] VD3 so that they turn on when the batteries BAT are connected in sequence, and the power supply potential [1b ] VD1b and the power supply potential [1a ] VD1a are controlled to have the same potential. When the battery BAT is reversely connected, the pMOS transistor MP1 is turned off, and the parasitic diode Dp3 of the battery BAT is also reversely biased.

For example, in an on-vehicle system of a 12V system as shown in fig. 1, since the reverse voltage is generally rated at-16V, the breakdown voltage of the reverse current prevention diode Dc may be 16V or higher and is designed to be, for example, 20V or the like. The breakdown voltage of pMOS transistor MP1 may be greater than or equal to that of diode Dc to prevent backflow if only the reverse voltage is considered, but it is desirable that diode Dc be designed to be greater than or equal to 50V in consideration of dump surge or the like when battery BAT is connected in the forward direction.

The booster circuit (charge pump circuit) CP1a includes a pMOS transistor MP2 and a resistor R2 coupled in series between a power supply [1b ] VD1b and a load drive terminal Po2(+), and nMOS transistors MN1 to MN3 and capacitors C1 to C3. serving as bodies of the booster circuit a clock signal CK (inverted clock signal CKB) from an oscillation circuit (not shown) is applied to a end of each of the capacitors C1 to C3 the gate discharge circuit DCG1a includes a resistor R1 for discharging a gate charge of the power transistor QN1 to a source, and a protection diode D2 for protecting a gate of the power transistor QN 1.

IN such a configuration, first, it is assumed that the battery BAT is connected IN the forward direction and the control input signal IN is asserted. IN this case, the enable signal S _ EN1 is also asserted IN response to assertion of the control input signal IN. The pMOS transistor MP2 is turned on in response to the active level of the enable signal S _ EN1, and supplies the power supply potential [1b ] VD1b to the back gates of the nMOS transistors MN1 to MN 3.

Each of the nMOS transistors MN1 to MN3 is formed on an n-type semiconductor substrate SUB, as shown in fig. 5. A p-type well PW is formed on the main surface of the semiconductor substrate SUB. In the p-type well PW, an n-type source diffusion layer DFs and a drain diffusion layer DFd serving as a source (S) and a drain (D), and a p-type feed diffusion layer DFb serving as a Back Gate (BG) are formed. A gate electrode GE serving as a gate (G) is disposed over the source diffusion layer DFs and the drain diffusion layer DFd with a gate insulating film interposed therebetween.

In such a configuration, there is an npn-type parasitic bipolar transistor BT having the source diffusion layer DFs and the drain diffusion layer DFd as emitters, the p-type well PW as a base, and the semiconductor substrate SUB as a collector. The power supply potential [1b ] VD1b is supplied to the semiconductor substrate SUB at a specific position (not shown). As described above, when the power supply potential [1b ] VD1b is supplied to the back gate BG via the pMOS transistor MP2, the parasitic bipolar transistor BT is turned on.

When the parasitic bipolar transistor BT is turned on, the parasitic bipolar transistor BT performs a charging operation on the capacitors C1 to C3 of fig. 4 by causing a charging current to flow through the source diffusion layer DFs and the drain diffusion layer DFd, and in addition, performs an initial charging on the gate of the power transistor QN1 in this case, the booster CP1a of fig. 4 applies a clock signal CK (inverted clock signal CKB) to the end of each of the capacitors C1 to C3 to sequentially pump the capacitors C1 to C3, thereby generating a predetermined boosted potential.

On the other hand, , in parallel with the gate charging current flowing to the gate of the power transistor QN1 by the charge pumping operation of the voltage boosting circuit CP1a, the resistor R1 in the gate discharging circuit DCG1a causes the gate discharging current to flow here, the resistor R1 is set to a high resistance value so that the above-mentioned gate discharging current is sufficiently smaller than the gate charging current, as a result, the boosted potential is applied to the gate of the power transistor QN1, and the power transistor QN1 is turned on.

Next, it is assumed that the control input signal IN is deactivated when the battery BAT is connected IN the forward direction. IN this case, IN response to the inactivation of the control input signal IN, the enable signal S _ EN1 is also inactivated. In response to the negative gate level of the enable signal S _ EN1, the pMOS transistor MP2 is turned off. As a result, the back-gate potential of the nMOS transistors MN1 to MN3 in the voltage boosting circuit CP1a is controlled to the same potential as the output potential VO via the resistor R2.

As a result, the parasitic bipolar transistors BT of the nMOS transistors MN1 to MN3 are turned off, and the application of the clock signal CK is stopped with the invalidation of the control signal IN. As a result, the booster circuit CP1a is deactivated. As a result, the electric charge of the gate of the power transistor QN1 is discharged to the source through the resistor R1 in the gate discharge circuit DCG1a, and the gate potential approaches the power supply potential [1a ] VD1a with time. During this discharge, the power transistor QN1 is turned on. However, since the gate discharge circuit DCG2 of fig. 3 rapidly controls the power transistor QN2 to be off in response to the invalidation of the enable signal S _ EN2 even if the power transistor QN1 is turned on, the supply of the forward current from the power supply circuit [1a ] VD1a to the load LD is cut off.

Next, it is assumed that the battery BAT is reversely connected. In this case, the power supply potential [3] VD3 is the battery power supply potential VB, the power supply potential [1a ] VD1a is the ground power supply potential GND, and the power supply potential [1b ] VD1b is "VB-VF" (VF is the forward voltage of the ESD protection diode De 1). The control circuit CTLa does not operate in this potential relationship, and the control circuit outputs the battery power supply potential VB as the enable signal S _ EN 1. As a result, the pMOS transistor MP2 turns off, and the back gate potential of the nMOS transistors MN1 to MN3 becomes the same potential as the load drive terminal Po2(+) (for example, approximately the battery power supply potential VB).

On the other hand side, when the battery BAT is reversely connected, the power transistor QN1 is turned off by the resistor R1 in the gate discharge circuit DCG1a in the booster CP1a, although the pumping operation is not performed because the clock signal is not generated due to the reverse connection, the parasitic bipolar transistor BT is turned on in response to the potential (for example, the battery power supply potential VB) from the load driving terminal Po2(+), and the charging operation is performed on the capacitors C1 to C3, however, the charging current at this time (in other words, the gate charging current of the power transistor QN1) can be adjusted by the resistor R2.

Thus, if the resistance of the resistor R2 is designed to be so high that the gate discharge current of the resistor R1 is sufficiently larger than the gate charge current determined by the resistor R2 and the hfe of the parasitic bipolar transistor BT, the power transistor QN1 remains in the off state.

Fig. 6 is a schematic diagram showing an external configuration of the semiconductor device (relay apparatus) of fig. 3, as shown in fig. 6, the semiconductor device (relay apparatus) RLYa of fig. 3 is composed of semiconductor chips or semiconductor packages, in addition to , for example, a relay apparatus RLY'd as a second comparative example shown in patent document 1 has a configuration in which a plurality of components (two power transistor components (QN1, QN2) and two booster circuit components (CP '1, CP '2)) are mounted on a BD wiring board 1.

As described above, when the semiconductor device (relay apparatus) RLYa of fig. 3 is used, the size of the device can be reduced as compared with the relay apparatus RLY'd of the second comparative example. As a result, the restriction on the position for mounting the relay device is relaxed, and the wiring route of the wire harness in the vehicle as shown in fig. 1 can be simplified. Such simplification of the wire harness contributes to weight, cost, power consumption, and the like of the vehicle.

IN the embodiment, when the control input signal IN is active at the time of the forward connection of the battery BAT, the booster circuit CP1a is active IN both the charging operation and the pumping operation, and the power transistor QN1 is turned on by "the gate charging current of the booster circuit CP1 a" > "the gate discharging current of the gate discharging circuit DCG1 a. when the battery BAT is forward connected and the control input signal IN is a negative input signal, the booster circuit CP1a is inactive, and the power transistor QN1 is turned off after a predetermined period of time has elapsed due to the gate discharging current of the gate discharging circuit DCG1a, on the other hand , when the battery BAT is reversely connected, the booster circuit CP1a is activated IN a weak charge operation, and the power transistor QN1 is turned off by" the gate charging current of the booster circuit CP1a "<" the gate discharging current of the gate discharging circuit DCG1a ".

Further, by implementing the relay device RLYa by semiconductor packages (IPDs), further -step miniaturization of the device can be achieved.here, although a resistor R1 is provided in the gate discharge circuit DCG1a, an nMOS transistor whose gate is coupled to the power supply [3] VD3 may be provided instead of the resistor R1.

Second embodiment

Relay devices RLY for automobiles as shown in fig. 1 and 2 (for example, a power supply shown by [1a ] VD1a in fig. 3) are generally coupled to a battery power supply VB. in this case, various external surges can be applied to the power supply [1a ] vd1a where, when a positive polarity surge represented by a dump surge caused by an alternator occurs, it is difficult to apply excessive power to the power transistor QN1 shown in fig. 3 because, even if the power transistor QN1 is turned off, the parasitic diode Dn1 is excited, on the other hand , when a negative polarity surge occurs due to a field coil or an inductive load, the power transistor QN1 may consume excessive power due to breakdown at the time of disconnection of the field coil or the inductive load, thereby causing breakdown.

Fig. 7 is a block diagram showing a schematic configuration of a semiconductor device (relay apparatus) according to a second embodiment, the semiconductor device (relay apparatus) RLYb shown in fig. 7 is different from the configuration shown in fig. 3 in the following five points as an th difference, a power transistor QN1(L) is provided instead of the power transistor QN1 shown in fig. 3, the withstand voltage of the power transistor QN1(L) is lower than that of the power transistor QN1 and the power transistor QN2 as a specific example, the withstand voltage of the power transistor QN2 (and the power transistor QN1) is 40V or the like, and the withstand voltage of the power transistor QN1(L) is 20V or the like.

As a second difference, the gate discharge circuit DCG1b includes a shorting transistor MN16 instead of the resistor R1 in fig. 4, as shown in detail in fig. 9. As a third difference, the booster circuit CP1b is constituted by the booster circuit bodies (MN1 to MN3, C1 to C3) shown in fig. 4. As a fourth difference, a negative potential detection circuit VNDET is provided instead of the backflow prevention circuit RCF shown in fig. 3. The negative potential detection circuit VNDET controls a short-circuit transistor in the gate discharge circuit DCG1b by a negative potential detection signal [1] S _ DET1, and controls the voltage boosting circuit CP1b by a negative potential detection signal [1] S _ DET 2. Therefore, as a fifth difference, the control circuit CTLb does not output the enable signal S _ EN1 shown in fig. 3.

In the vehicle-mounted system of the 12V system shown in fig. 1 and 2, normally, in consideration of erroneous connection at the start of jumping or the like, the DC rating of positive polarity needs to be 28V, further , and the DC rating of negative polarity (which is not assumed to be such as the start of jumping or the like) is usually-16V, focusing on such a rating potential difference between positive and negative polarities, the power transistor QN1(L) can be realized with a low withstand voltage configuration.

However, when a negative surge such as-60V to-120V is applied to the power supply [1a ] VD1a, the loss caused by the breakdown of the power transistor QN1(L) increases by an amount corresponding to the low withstand voltage, therefore, for example, when the method disclosed in patent document 2 is used, the power transistor may be controlled to be on when the negative surge is applied, so that such loss may be reduced and the power transistor may be protected.

Fig. 8 is a circuit diagram showing a schematic configuration example of a negative potential detection circuit in the semiconductor device (relay apparatus) of fig. 7, in which the main part of the relay apparatus (second embodiment) is explained in detail. Fig. 9 is a circuit diagram showing a detailed configuration of a main portion of the semiconductor device (relay apparatus) of fig. 7. For example, in fig. 7, when the battery BAT is reversely connected and when a negative surge is applied to the power supply [1a ] VD1a, the negative potential reference power supply [3] VD3 is applied to the power supply [1a ] VD1 a. However, it is desirable that the power transistor QN1(L) be turned off when the battery BAT is reversely connected and be turned on when a negative surge is applied to the battery BAT. Therefore, the negative potential detection circuit VNDET is provided to distinguish the reverse connection of the battery BAT and the application of the negative surge, and the power transistor QN1(L) is turned on/off according to the result of distinguishing the reverse connection of the battery BAT and the application of the negative surge.

The negative potential detection circuit VNDET shown in fig. 8 includes a resistor R11 and a negative potential discrimination circuit JDG in addition to the pMOS transistor MP1 and the reverse current prevention diode Dc in the reverse current prevention circuit RCF shown in fig. 4. A resistor R11 and a backflow prevention diode (zener diode) Dc are provided in series between the power supply [1a ] VD1a (in other words, the positive power supply terminal Pi2(+)) and the power supply [1b ] VD1 b. Here, the power supply [1b ] VD1b is coupled to the power supply [3] VD3 (in other words, the negative power terminal Pi2(-)) via the ESD protection diode De1, which is forward biased, when the battery BAT is reversely connected or when a negative surge is applied to the battery BAT. Therefore, the resistor R11 and the backflow prevention diode Dc are substantially arranged in series between the positive power terminal Pi2(+) and the negative power terminal Pi2 (-).

Further , when a negative surge exceeding the breakdown voltage of the backflow prevention diode Dc (e.g., -negative surge of the negative side of 20V) is applied to the power supply [1a ] VD1a, the backflow prevention diode Dc breaks down, thereby generating a predetermined potential difference between both ends of the resistor R11.

As will be described in detail with reference to fig. 9, when the battery BAT is reversely connected, the negative potential determination circuit JDG controls the gate discharge circuit DCG1b to be on via the negative potential detection signal [1] S _ DET1 and deactivates the voltage boosting circuit CP1b via the negative potential detection signal [2] S _ DET2, as a result, the power transistor QN1(L) is turned off to cut off the reverse conduction, in addition , when a negative surge is applied, the negative potential determination circuit JDG controls the gate discharge circuit DCG1b to be off via the negative potential detection signal [1] S _ DET1 and causes the voltage boosting circuit CP1b to output a predetermined potential more positive than the power supply potential [1a ] VD1a via the negative potential detection signal [2] S _ DET2, as a result, the power transistor QN1(L) is turned on, and power loss due to the negative surge can be reduced.

In addition , when the batteries BAT are connected in sequence, the power supply [1a ] VD1a and the power supply [1b ] VD1b have substantially the same potential via the pMOS transistor MP1 in this case, the negative potential determination circuit JDG controls the gate discharge circuit DCG1b to be off via the negative potential detection signal [1] S _ DET1, and activates the voltage boosting circuit CP1b via the negative potential detection signal [2] S _ DET2, thereby controlling the power transistor QN1(L) to be on.

As described above, the negative potential detection circuit VNDET determines whether the negative potential applied to the power supply [1a ] VD1a (the positive power supply terminal Pi2(+)) is on the positive side or the negative side with respect to the power supply [3] VD3 (the negative power supply terminal Pi2(-)) as a reference, is higher than a predetermined negative threshold potential (i.e., -20V or the like based on the breakdown voltage of the reverse current prevention diode Dc.) then, the negative potential detection circuit VNDET controls the gate discharge circuit DCG1b to be turned on in the case of the positive side (e.g., -12V or the like associated with the reverse connection of the battery BAT), and controls the gate discharge circuit DCG1b to be turned off in the case of the negative side (e.g., -100V or the like associated with the negative surge).

Fig. 9 shows an example of the configuration around the negative potential detection circuit VNDET, around the voltage boosting circuit CP1b, and around the gate discharge circuit DCG1b shown in fig. 7 and 8. The gate discharge circuit DCG1b includes a protection diode D2 and an nMOS transistor (short-circuit transistor) MN16 coupled in parallel between the power supply [1a ] VD1a and the gate of the power transistor QN1 (L). The booster CP1b includes nMOS transistors MN1 to MN3 and capacitors C1 to C3, which are the same as in fig. 4.

The negative potential detection circuit vndeta (vndet) includes a negative potential determination circuit JDGa. The negative potential discrimination circuit JDGa includes nMOS transistors MN11 to MN15, resistors R12 to R15, a pMOS transistor MP11, a diode D11, and a capacitor C11. A negative potential detection signal [1] S _ DET1 from the negative potential determination circuit JDGa is applied to the gate of the nMOS transistor (short-circuit transistor) MN16 in the gate discharge circuit DCG1 b.

A negative potential detection signal [2] S _ DET2 from the negative potential determination circuit JDGa is applied to the back gates of the nMOS transistors MN1 to MN3 in the voltage boosting circuit CP1 b. A diode (zener diode) D11 is coupled between the power supply [1a ] VD1a (in other words, the positive power supply terminal Pi2(+)) and the back gate of the nMOS transistors MN1 to MN3 as the power supply [1a ] VD1a on the anode side (cathode on the back gate side).

In fig. 9, the power supply [3] VD3 is coupled to the ground supply potential GND of the battery BAT, in particular via an external resistor such as 100 Ω. The breakdown voltage of the backflow prevention diode Dc in the negative potential detection circuit VNDETa is, for example, 20V or the like, which is substantially the same as the breakdown voltage of the power transistor QN1 (L). As described above, from the viewpoint of protecting the power transistor QN1(L), the breakdown voltage of the backflow prevention diode Dc is desirably set to be equal to or lower than the breakdown voltage of the power transistor QN1(L) (but, higher than the battery power supply potential VB).

In this configuration, first, it is assumed that the batteries BAT are connected in sequence. In this case, since the power supply [1b ] VD1b becomes substantially the same potential as the power supply [1a ] VD1a through the pMOS transistor MP1, the negative potential discrimination circuit JDGa does not perform the discrimination operation. The negative potential determining circuit JDGa controls the nMOS transistor MN16 in the gate discharge circuit DCG1b to be off by controlling the negative potential detection signal [1] S _ DET1 to be substantially the power supply potential [1a ] VD1a via the resistor R12. The negative potential determination circuit JDGa supplies the power supply potential [1a ] VD1a to the back gates of the nMOS transistors MN1 to MN3 in the voltage boosting circuit CP1b via the diode D11. As a result, the booster CP1b performs a charging operation and a pumping operation based on a clock signal (not shown) to raise the gate potential of the power transistor QN1(L) to a potential at which the power transistor QN1(L) can operate in a sufficiently linear range.

Next, it is assumed that the battery BAT is reversely connected. In this case, since the backflow preventing diode Dc does not break down, a potential difference is not generated between both ends of the resistor R11. Accordingly, the nMOS transistor MN11 is turned off, and the power supply potential [1b ] VD1b (i.e., about the battery power supply potential VB) is transmitted through the resistor R12, so that the nMOS transistor MN12 is turned on and the pMOS transistor MP11 is turned off. As a result, the negative potential detection signal [1] S _ DET1 becomes the same potential as the power supply [1b ] VD1b (approximately the battery power supply potential VB), and the negative potential detection signal [2] S _ DET2 becomes the same potential as the power supply [1a ] VD1a (i.e., the ground power supply potential GND).

The nMOS transistor MN16 in the gate discharge circuit DCG1b is turned on in response to the negative potential detection signal [1] S _ DET 1. In the booster circuit CP1b, the parasitic bipolar transistor BT in fig. 5 is turned on in response to the negative potential detection signal [2] S _ DET2, and the oscillator circuit does not operate, so that the pumping operation is not performed. Therefore, booster CP1b is deactivated. As a result, the power transistor QN1(L) is turned off to cut off reverse conduction.

Next, it is assumed that a negative surge (for example, -60V to-120V) is applied to power supply [1a ] VD1a when batteries BAT are connected in sequence. Since the potential relationship between the power supply [1a ] VD1a and the power supply [3] VD3 is the same as that at the time of the reverse connection of the battery BAT described above, the power transistor QN1(L) is turned off by turning on the nMOS transistor MN16 unless the reverse connection of the battery BAT and the application of the negative surge are distinguished.

Here, when the control input signal IN shown IN fig. 7 is at an active level, the power transistor QN1(L) is initially turned on, and therefore no particular problem arises even if a negative surge is applied to the control input signal IN, on the other hand , when the control input signal IN is at an inactive level (i.e., when the boost circuit CP1b is initially inactive), it is necessary to design the control input signal IN to turn on the power transistor QN1(L), unlike the case when the battery BAT is connected IN reverse to the boost circuit QN 1.

When a negative surge is applied to the power supply [1a ] VD1a, the reverse current prevents the diode Dc from breaking down via the ESD protection diode De1, and a potential difference is generated between both ends of the resistor R11. The forward voltage of the power supply [1b ] VD1b through the ESD protection diode De1 becomes lower than the potential of the power supply [3] VD3 and becomes higher than the power supply potential [1a ] VD1 a. As a result, the nMOS transistor MN11 turns on, and the negative potential detection signal [1] S _ DET1 becomes the same potential as the power supply signal [1a ] VD1 a. As a result, nMOS transistor MN16 in gate discharge circuit DCG1b is turned off.

In addition, in response to the turning on of the nMOS transistor MN11, the pMOS transistor MP11 turns on and the nMOS transistor MN12 turns off. As a result, a current flows from the pMOS transistor MP11 through the resistor R13 and the diode D11. As a result, the negative potential detection signal [2] S _ DET2 becomes positive with reference to the power supply potential [1a ] VD1a by the breakdown voltage (for example, 6V) of the diode (zener diode) D11.

In the booster CP1b, the parasitic bipolar transistor BT is turned on in response to the negative potential detection signal [2] S _ DET2, and a charging operation is performed. IN the booster circuit CP1b, since the pumping operation is not performed according to the invalidation of the control input signal IN, only the charging operation of the booster circuit CP1b is activated. As a result, a turn-on voltage determined by the breakdown voltage of the diode (zener diode) D11 may be applied between the gate and the source of the power transistor QN1 (L). At this time, the nMOS transistor MN16 is turned off. As a result, when a negative surge is applied, the power transistor QN1(L) can be controlled to be on. As described above, the breakdown voltage of the diode D11 only needs to be a value at which the power transistor QN1(L) can operate in a sufficiently linear range.

Here, the base current of the parasitic bipolar transistor (BT in fig. 5) in the booster CP1b may be adjusted by the resistor R13, and the on speed of the power transistor QN1(L) may be determined by the resistor R13, for example, if rapid on is desired, the resistor R13 may be set to a small resistance value here, the nMOS transistor MN16 is provided in the gate discharge circuit DCG1b in another aspect, it is not easy to use a pMOS transistor instead of an nMOS transistor, that is, in order to discharge the gate potential of the power transistor QN1(L) to the ground power supply potential GND while the power supply [1a ] VD1a is at the ground power supply potential GND when the battery BAT is reversely connected, a negative potential needs to be applied to the gate of the pMOS transistor.

In order to prevent a jitter in the vicinity of the breakdown voltage of the reverse current prevention diode Dc, it is desirable that the negative potential detection signal [1] S _ DET1 and the negative potential detection signal [2] S _ DET2 are latched in a state when a negative surge is applied. nMOS transistors MN13 to MN15, resistors R14 and R15, and a capacitor C11 are provided as elements for latching. When the power supply potential [1a ] VD1a returns to the positive electrode, the latch is released because the potential difference between the power supply potential [1a ] VD1a and the power supply potential [1b ] VD1b becomes small.

As described above, by rapidly turning on the power transistor QN1(L) when a negative surge is applied, the loss of the power transistor QN1(L) can be greatly reduced compared to when breakdown is performed, and a low withstand voltage configuration can be applied to the power transistor QN1 (L). In addition, the power transistor QN1(L) can be protected. Specific examples of the loss are shown below.

Assuming that the breakdown voltage of the power transistor QN1(L) is "BV 1", the on-resistance is "Ron 1", the negative surge potential is "Vsr", and the load resistance is "RL", the loss PL1 in the case of breakdown is represented by equation (1), and the loss PL2 in the case of on is represented by equation (2). For example, PL1 is 1600W and PL2 is 50W when Vsr is-100V, BV1 is 20V, Ron1 is 5m Ω and RL is 1 Ω.

PL1＝BV1×(|Vsr|-BV1)/RL (1)

PL2＝Ron×(|Vsr|-RL)2 (2)

Fig. 10 is a circuit diagram showing a configuration example when the circuit of fig. 9 is formed on a wiring substrate. As shown in fig. 10, the circuit of fig. 9 may be realized by mounting a plurality of components on the circuit board BD 2. In fig. 10, the charging circuit CU is a circuit corresponding to the parasitic bipolar transistor BT of fig. 5 at the time of application of the negative surge, and the boosting circuit CU is mounted in the driver DVb 1. Fig. 11 is a schematic diagram comparing a schematic example of the relay device of fig. 7 and the relay device of fig. 10.

As shown in fig. 11, in the relay apparatus (printed circuit board BD2) according to fig. 10, the number of components is greatly increased as compared with the relay apparatus RLYb of fig. 7, and therefore, it is difficult to miniaturize the apparatus. Further, the gate oxide film breakdown voltage of pMOS transistor MPb1 in fig. 10 needs to be 40V or more in consideration of dump surge, but since a typical gate oxide film breakdown voltage is 20V, the breakdown voltage of zener diode ZDb2 needs to be set to 20V or less. If the battery power supply potential VB is set to about 8V to 16V and the temperature characteristic is taken into consideration, the breakdown voltage of the zener diode ZDb2 needs to be in the range of 16V to 20V, which may make it difficult to select components.

IN the second embodiment, when the control input signal IN is enabled while the battery BAT is connected IN sequence, the charge operation and the pumping operation of the boosting circuit CP1b are both activated the nMOS transistor MN16 IN the gate discharge circuit DCG1b is turned off because the source is coupled to the power supply [1a ] VD1a, the gate is coupled to the power supply [1a ] VD1a via the pMOS transistor MP1 and the resistor R12, and the boosted potential is applied to the drain.

When the battery BAT is reversely connected, the booster CP1b is disabled, and the nMOS transistor MN16 is turned on because its source is coupled to the power supply [1a ] VD1a and its gate is coupled to the power supply [3] VD3 via the ESD protection diode De1 and the resistor R12. As a result, the power transistor QN1(L) is turned off. Further, when the battery BAT is connected IN the forward direction, when the control input signal IN is deactivated, and when a negative surge is applied to the control input signal IN, the voltage boosting circuit CP1b is activated IN the charging operation of the voltage boosting circuit CP 1B. nMOS transistor MN16 is off because its source is coupled to power supply [1a ] VD1a and its gate is also coupled to power supply [1a ] VD1a via nMOS transistor MN 11. As a result, the power transistor QN1(L) is turned on.

Further, by configuring the power transistor QN1(L) so that it can be driven at the time of negative surge application, loss at the time of negative surge application can be reduced, and a structure having a lower withstand voltage than that of the power transistor QN2 can be applied to the power transistor QN1 (L).

Third embodiment

As described above, the gate potential of the nMOS transistor MN16 in the gate discharge circuit DCG1b shown in fig. 9 is controlled by the negative potential detection signal [1] S _ DET1 as a prerequisite of the third embodiment. When the battery BAT is connected in the forward direction, the negative potential detection signal [1] S _ DET1 becomes substantially the same potential as the power supply signal [1a ] VD1 a. Therefore, the nMOS transistor MN16 is turned off, and the gate charge of the power transistor QN1(L) is not discharged. That is, the power transistor QN1(L) cannot be controlled to be off.

IN another aspect, the power supply to the load LD is controlled by the power transistor QN2, and the power transistor QN2 is turned on and off rapidly IN response to the control input signal IN, therefore, by controlling the power transistor QN2 to be off regardless of the state of the power transistor QN1(L), the supply of forward current to the load LD can be cut off.

Therefore, although no fatal problem occurs because the power transistor QN1(L) cannot be controlled to be off, a problem may occur when a capacitor load or the like is used. For example, when a capacitor load is used and cranking (cranking) occurs at the time of invalidation of the control input signal IN, since the potential of the capacitor load > the power supply potential [1a ] VD1a, the charge of the capacitor load may escape to the power supply [1a ] VD1a, and may not be recovered thereafter.

Fig. 12 is a waveform diagram showing an exemplary problem as a prerequisite of the relay apparatus (semiconductor device) according to the third embodiment. Fig. 12 shows changes IN the power supply potential [1a ] VD1a, the gate potentials of the power transistors QN1(L) and QN2, and the potential of the output potential VO when the control input signal IN is deactivated at time t1 and startup occurs between time t2 and t 5.

When the control input signal IN is inactivated at time t1, the gate potential of the power transistor QN2 is lowered by the gate discharge circuit DCG2 until the gate potential of the control input signal IN becomes equal to the output potential VO. of the load drive terminal Po2(+) and , since the nMOS transistor MN16 IN the gate discharge circuit DCG1b is not turned on, the gate potential of the power transistor QN1(L) is held at a potential at which the power transistor QN1(L) can be turned on strictly speaking, the gate potential of the power transistor QN1(L) is lowered to the power supply potential [1a ] VD1a for a long period due to the leakage current of the respective elements coupled to the gate, but IN fig. 12, it is assumed that there is no leakage current.

When the start-up occurs at time t2 and the power supply potential [1a ] VD1a falls, the charge of the capacitor load coupled to the load drive terminal Po2(+) escapes to the power supply [1a ] VD1a via the parasitic diode Dn2 of the power transistor QN2 and the channel of the power transistor QN1 (L). During the period from the time t4 to the time t5, the power supply potential [1a ] VD1a returns to the original potential. However, since the power transistor QN2 is turned off, the potential of the capacitor load (the output potential VO) is held at the potential that falls during the period from time t3 to time t4 without newly supplying the discharged electric charges.

For example, when a unit having a capacitor load as a backup power source exists downstream of the relay device, the capacitor load may be used. In this case, for example, there may occur a risk that the downstream unit is cut off by a low voltage. Therefore, it is advantageous to use a relay device (semiconductor device) of a third embodiment which will be described later.

Fig. 13 is a block diagram showing a schematic configuration of a semiconductor device (relay apparatus) according to a third embodiment, the semiconductor device (relay apparatus) RLYc shown in fig. 13 is different from the configuration shown in fig. 7 in four points is different in that a load LD2 is a capacitor load, as a second difference, a delay circuit DLY is added, and as a third difference, a gate discharge circuit dcg3 is added, as a fourth difference, as shown in detail in fig. 14, a gate potential of a power transistor QN1(L) is input to a negative potential detection circuit VNDET.

The delay circuit DLY outputs the delay signal S _ DLY that is active for a predetermined period of time, which is triggered by a transition of the control signal INx output from the input buffer IBF to inactive (i.e., a transition of the control input signal IN to inactive). The gate discharge circuit DCG3 is provided between the gate of the power transistor QN1(L) and the power supply [3] VD3, and receives the delay signal S _ DLY from the delay circuit DLY to discharge the gate charge of the power transistor QN1(L) toward the power supply [3] VD 3.

Fig. 14 is a circuit diagram showing a detailed configuration example of a main portion of the semiconductor device (relay apparatus) shown in fig. 13 to show the main portion of the relay apparatus (third embodiment). Fig. 15 is a circuit diagram showing a detailed configuration example of the delay circuit in fig. 13. Fig. 14 shows examples of the configuration around the negative potential detection circuit VNDET, around the booster circuit CP1b, around the gate discharge circuit DCG1b, and around the gate discharge circuit DCG3 shown in fig. 13.

In comparison with the configuration shown in fig. 9, the negative potential determination circuit JDGc in the negative potential detection circuit vndetc (vndet) further includes an nMOS transistor MN21 coupled in series with the resistor R12 and a capacitor C21 provided between the gate of the nMOS transistor MN16 and the power supply [3] VD 3. The gate of NMOS transistor MN21 is coupled to the gate of power transistor QN1 (L). The gate discharge circuit DCG3 includes a resistor R21 and an nMOS transistor MN22 coupled in series between the gate of nMOS transistor MN21 (and power transistor QN1(L)) and the power supply [3] VD 3. The delayed signal S _ DLY is applied to the gate of nMOS transistor MN 22.

First, an outline of the circuit shown in fig. 14 will be described. The reason for the problem described with reference to fig. 12 is that the nMOS transistor MN16 in the gate discharge circuit DCG1b is controlled to be turned on when the battery BAT is connected in the reverse direction, but to be kept turned off when the battery BAT is connected in the forward direction. As a result, even if the control input signal IN is disabled when the battery BAT is connected IN the forward direction, the on state of the power transistor QN1(L) can be maintained, and therefore, charge loss occurs at the time of startup.

Here, the reason why the nMOS transistor MN16 is kept off is that, in terms of the gate potential of the nMOS transistor MN16 following the power supply potential [1a ] vd1a, further , it is assumed that when the power supply potential [1a ] VD1a fluctuates due to startup, the gate potential of the nMOS transistor MN16 keeps the gate potential of the power supply potential [1a ] VD1a before startup, without following the gate potential [1a ] vd1a-in which case the nMOS transistor MN16 is automatically turned on because the gate-source voltage is generated in accordance with the change in the power supply potential [1a ] VD1 a-as a result, the power transistor QN1(L) can be controlled to be off.

Therefore, the capacitor C21 is provided, and the capacitor C21 holds the potential of the negative potential detection signal [1] S _ DET1, that is, the gate potential of the nMOS transistor MN16 before starting. Specifically, when the power supply potential [1a ] VD1a is applied to the gate (negative potential detection signal [1] S _ DET1) during the active period of the control input signal IN, the nMOS transistor (short-circuit transistor) MN16 is turned off. During the inactive period of the control input signal IN, the capacitor C21 holds the gate potential of the nMOS transistor MN16 during the active period of the control input signal IN.

However, since the power supply potential [1b ] VD1b is interlocked with the change in the power supply potential [1a ] VD1a, if the nMOS transistor MN21 is not provided, the potential of the capacitor C21 is interlocked with the power supply potential [1b ] VD1b, and the power supply potential [1a ] VD1a before the start cannot be held. Thus, an nMOS transistor (control transistor) MN21 is provided. The nMOS transistor MN21 is provided between the power supply [1b ] VD1b (and thus the power supply [1a ] VD1a (positive power supply terminal Pi2(+)) and the gate of the nMOS transistor MN 16. During the inactive period of the control input signal IN, the nMOS transistor MN21 is controlled to be off, thereby controlling the gate of the nMOS transistor MN16 to a high impedance state.

Specifically, the gate of nMOS transistor MN21 is coupled to the gate of power transistor QN1(L) and has the same potential as the gate, therefore, when a change in power supply potential [1a ] VD1a occurs, power supply potential [1a ] VD1a is applied to the gate of nMOS transistor MN16, and the gate potential of power transistor QN1(L) is controlled to be power supply potential [1a ] vd1a in a changed state after the start-up occurs, in nMOS transistor MN21, the source (power supply potential [1b ] VD1b) fluctuates from the fluctuating power supply potential [1a ] VD1a , but since the gates also fluctuate in the same manner, they remain off.

On the other hand, , for example, when the gate of the power transistor QN1(L) is held at a boosted potential before startup, the power transistor QN1(L) is turned on and the nMOS transistor MN21 is also turned on here, as described above, IN order to turn off the nMOS transistor MN21 during the inactive period of the control input signal IN, it is necessary to initially control the nMOS transistor MN21 to be turned off when the control input signal IN is shifted from the active level to the inactive level.

Otherwise, when the power supply potential [1a ] VD1a fluctuates, the negative potential detection signal [1] S _ DET1 starts to follow the power supply potential [1a ] VD1a in the state of the fluctuation, so that the nMOS transistor MN16 does not conduct, and as a result, the nMOS transistor MN21 can also remain conducting. Accordingly, a gate discharge circuit DCG3 is provided. When the control input signal IN is transitioned from the active level to the inactive level, the gate discharge circuit DCG3 sets the gate potentials of the nMOS transistor MN21 and the power transistor QN1(L) to "VD 1 a-VF" (VF is the forward voltage of the protection diode D2). As a result, the gate discharge circuit DCG3n controls the MOS transistor MN21 to be off, and further, the gate discharge circuit also controls the power transistor QN1(L) to be off.

Next, details of the circuits shown in fig. 14 and 15 will be described. The delay circuit DLY shown in fig. 15 includes nMOS transistors MN31 to MN33, pMOS transistors MP31 to MP34, resistors R31 to R33, capacitors C31 to C33, a diode D31, an inverter IV31, and current sources IS31 and IS 32. The current sources IS31 and IS32 are implemented by current mirror circuits, depletion transistors in which gates and sources are shorted, or the like. Note that the resistors R31 to R33 may be replaced with depletion type transistors or the like in which the gate and the source are shorted.

The current source IS31, the diode D31, and the resistor R33 generate a power supply (power supply potential) [6] VD6, the power supply (power supply potential) [6] VD6 being a reference of the power supply [1b ] VD1 b. The control signal INx from the input buffer IBF is input to the gates of the nMOS transistor MN31 and the pMOS transistor MP 31. The capacitors C32 and C33, the resistor R32, the nMOS transistor MN33, the pMOS transistors MP33 and MP34, and the inverter IV31 constitute a timer circuit. The delayed signal S DLY is output by inverter IV 31. The inverter IV31 also has a function of shifting the level of a signal between the power supply [1b ] VD1b and the power supply [6] VD6 to a signal between the power supply [1b ] VD1b and the power supply [3] VD 3.

IN such a configuration, IN response to the assertion of the control signal IN, the control signal INx reaches an active level, IN this case, the VD3 level. As a result, the nMOS transistor MN31 is turned off, and the power supply [1b ] VD1b and the power supply [6] VD6 have the same potential. That is, the power supply [6] VD6 is deactivated without generating a predetermined power supply. The pMOS transistor MP31 is turned on, and the node Na has the same potential as the power supply [1b ] VD1 b.

When the control input signal IN is switched from active to inactive, the control signal INx becomes an inactive level, IN this case, the VD1b level, and the nMOS transistor MN31 is turned on while the pMOS transistor MP31 is turned off. However, at this time, since the pMOS transistor MP32 is turned off, the potential of the node Na changes from the power supply potential [1b ] VD1b to the power supply [3] VD3 with a time constant determined by the capacitor C31 and the resistor R31.

In another aspect, immediately after the control signal INx IS switched from the active level (VD3 level) to the inactive level (VD1b level), the potential of the node Na IS in the vicinity of the power supply potential [1b ] VD1 b. therefore, the nMOS transistor MN32 IS turned on and the power supply [6] VD6 IS generated by the diode D31 and the current source IS 31. that IS, the power supply [6] VD6 IS activated as will be described later in detail, immediately after the power supply [6] VD6 IS generated, since the potential of the node Nb IS at the power supply potential [6] VD6, the pMOS transistor MP32 IS turned on and the on state of the nMOS transistor MN32 IS maintained regardless of the time constant determined by the capacitor C31 and the resistor R31.

The capacitor C32, the resistor R32, and the nMOS transistor MN33 are provided to initialize the potential of the node Nb, and immediately after the power supply [6] VD6 is generated, the nMOS transistor MN33 is controlled to be turned on to lower the potential of the node Nb to the level of the power supply potential [6] VD 6. As a result, the pMOS transistor MP32 is turned on, and the nMOS transistor MN32 remains turned on, as described above, regardless of the time constants of the capacitor C31 and the resistor R31.

After a predetermined period determined by the capacitor C32 and the resistor R32 has elapsed, the nMOS transistor MN33 is turned off. As a result, the capacitor C33 starts to be charged by a current obtained by mirroring the current of the current source IS32 by the pMOS transistor MP33 and MP34, and the potential of the node Nb IS changed from the power supply potential [6] VD6 to the power supply potential [1b ] VD1 b. The delay signal S _ DLY becomes an active level in a period from the activation time of the power supply [6] VD6 to the time when the potential of the node Nb reaches the threshold of the inverter IV31, and in this period, the delay signal S _ DLY turns on the nMOS transistor MN22 in the gate discharge circuit DCG 3.

When the potential of the node Nb reaches the threshold of the inverter IV31, the delay signal S _ DLY becomes negative gate level, and the nMOS transistor MN22 in the gate discharge circuit DCG3 is turned off the length of the active period of the delay signal S _ DLY is set appropriately in conjunction with the resistance value of the resistor R21 in the gate discharge circuit DCG3 so that the gate charge of the power transistor QN1(L) is discharged in the active period of the delay signal S _ DLY. when the potential of the node Nb exceeds the threshold of the inverter IV31 and approaches the power supply potential [1b ] VD1b, the pMOS transistor MP32 is turned off.

As a result, the potential of the node Na changes from the power supply potential [1b ] VD1b to the power supply potential [3] VD3 according to a time constant determined by the capacitor C31 and the resistor R31, and the nMOS transistor MN32 turns off. As a result, the potential of the power supply [6] VD6 becomes the same as the potential of the power supply [1b ] VD1b, and the current consumed by the delay circuit DLY becomes zero.

Fig. 16 is a waveform diagram illustrating an example of the operation of the circuit of fig. 14. When the control input signal IN is deactivated, the delay signal S _ DLY is activated for a predetermined time period, i.e., time t1 to t 3. The gate charge of the power transistor QN1(L) needs to be discharged in the period from t1 to t3, and needs to be discharged more slowly than the gate charge of the power transistor QN 2. In this case, the gate charge of the power transistor QN1(L) is discharged at time t2, and the gate charge of the power transistor QN2 is discharged after time t1 and before time t 2. With respect to this discharging sequence, if the power transistor QN1(L) is turned off before the power transistor QN2, the combined resistance of the power transistor QN1(L) and the power transistor QN2 may be discontinuous, thereby generating switching noise.

The period from the time t4 to the time t7 is a period in which the potential of the power supply [1a ] VD1a changes due to startup. Since the power transistor QN1(L) is turned off at time t2 (i.e., the gate and source are coupled to the power supply [1a ] VD1a) during the potential change, the potential of the capacitor load (output potential VO) is not transferred to the power supply [1a ] VD1a, which is different from the case of fig. 12.

That is, since the nMOS transistor MN11 and the nMOS transistor MN21 in fig. 14 are turned off during the potential change, the negative potential detection signal [1] S _ DET1 is held by the capacitor C21 at a level before the time t1 (around the power supply potential [1a ] VD1a level before the potential change period). As a result, in the potential change period, the nMOS transistor MN16 in the gate discharge circuit DCG1b controls the gate potential of the power transistor QN1(L) to be equal to the power supply potential [1a ] VD1a after the potential change period.

Note that even if such control is not used, the gate potential of the power transistor QN1(L) follows the source potential to some extent through the gate-drain capacitance. However, since a balance between the gate-source capacitance of the power transistor QN1(L) and the charging operation of the booster CP1b associated with the residual charge of the negative potential detection signal [2] S _ DET2 can be considered, it is preferable to perform the above-described control.

IN the third embodiment, IN addition to performing the same operation as that of the second embodiment, when the batteries BAT are connected IN sequence and the control input signal IN is disabled, the capacitor C21 also holds the gate potential of the nMOS transistor MN16 before the start when the nMOS transistor MN21 is turned off at the time of the start occurring at the disabling of the control input signal IN. As a result, the nMOS transistor MN16 is automatically turned on because the source potential is lowered by the start-up, and thus the power transistor QN1(L) is turned off. When the battery BAT is reversely connected, the nMOS transistor MN21 may be turned off, but since the parasitic diode Dn21 having the power supply [1b ] VD1b as its anode is turned on, the operation is the same as that of the second embodiment.

By using this method, the same effect as the second embodiment can be obtained. Further, during the inactive period of the control input signal IN, the power transistor QN1(L) can be controlled to be off, and even when the power supply potential [1a ] VD1a fluctuates due to the start-up, the power transistor QN1(L) can be kept off. As a result, charge loss in the capacitor load can be prevented. Here, various circuits are added to the configuration example of fig. 9, but similar circuits may also be added to the configuration example of fig. 4.

Although the invention made by the present inventors has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist thereof.