阅读说明：本技术 电平转换电路 (Level conversion circuit ) 是由 徐辉 陈春平 于 2018-07-20 设计创作，主要内容包括：本申请涉及一种电平转换电路。电平转换电路,包括：电平转换单元和半边反馈单元；电平转换单元包括：输入节点、用以输出具有所需电平的输出信号的输出节点、反相输入节点和用以输出与输出信号反相的反相输出信号的反相输出节点；边反馈单元耦接在输出节点和反相输出节点之间。通过在输出节点和反相输出节点之间耦接一半边反馈单元,在电平转换单元的多个供电电源上电或掉电时序不同步时,对输出信号进行反馈补偿,使输出节点输出高电平或低电平状态确定的信号。(The application relates to a level conversion circuit, which comprises a level conversion unit and a half-edge feedback unit, wherein the level conversion unit comprises an input node, an output node used for outputting an output signal with a required level, an inverting input node and an inverting output node used for outputting an inverted output signal inverted to the output signal, the edge feedback unit is coupled between the output node and the inverting output node, and the half-edge feedback unit is coupled between the output node and the inverting output node so that when power-on or power-off time sequences of a plurality of power supplies of the level conversion unit are not synchronous, feedback compensation is carried out on the output signal, and the output node outputs a signal determined by a high level state or a low level state.)

The level shift circuit of 1, kinds is characterized by comprising a level shift unit and a half feedback unit;

the level conversion unit includes: an input node, an output node to output an output signal having a desired level, an inverting input node, and an inverting output node to output an inverted output signal that is inverted from the output signal;

the half-side feedback unit is coupled between the output node and the inverting output node.

2. The circuit of claim 1, further comprising a level shift acceleration unit coupled between the input stage of the level shift unit and the output stage of the level shift unit, wherein the level shift acceleration unit is configured to accelerate a level shift speed of the level shift unit.

3. The circuit of claim 2, wherein the half-side feedback unit comprises an NMOS transistor, the NMOS transistor is coupled between the output node and the inverted output node, and a source of the NMOS transistor is connected to ground.

4. The level shift circuit of claim 3, wherein the level shift unit comprises PMOS transistor, second PMOS transistor, third PMOS transistor, fourth PMOS transistor, second NMOS transistor and third NMOS transistor;

the source electrode of the PMOS tube is used for being connected with a power supply, the drain electrode of the PMOS tube is connected with the source electrode of the third PMOS tube, and the grid electrode of the PMOS tube is connected with the inverted output node;

the source electrode of the second PMOS tube is used for being connected with power supply, the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube, and the grid electrode of the second PMOS tube is connected with the output node;

the grid electrode of the third PMOS tube is connected with the input node, and the drain electrode of the third PMOS tube is connected with the output node;

the grid electrode of the fourth PMOS tube is connected with the inverted input node, and the drain electrode of the third PMOS tube is connected with the inverted output node;

the grid electrode of the second NMOS tube is connected with the input node, the source electrode of the second NMOS tube is connected with the grounding point, and the drain electrode of the second NMOS tube is connected with the output node;

the grid electrode of the third NMOS tube is connected with the inverted input node, the source electrode of the third NMOS tube is connected with the grounding point, and the drain electrode of the third NMOS tube is connected with the inverted output node.

5. The level shift circuit according to claim 4, wherein the level shift accelerating unit comprises a fourth NMOS transistor and a fifth NMOS transistor, a drain of the fourth NMOS transistor is connected to the output node, a source of the fourth NMOS transistor is connected to a drain of the second NMOS transistor, a gate of the fourth NMOS transistor and a gate of the fifth NMOS transistor are both used for connecting the power supply, a drain of the fifth NMOS transistor is connected to the inverted output node, and a source of the fifth NMOS transistor is connected to a drain of the third NMOS transistor.

6. The circuit of claim 5, wherein the second NMOS transistor and the third NMOS transistor are both type NMOS transistors, and the PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are all type PMOS transistors.

7. The circuit of claim 6, wherein the NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor are NMOS transistors of a second type, and a turn-on voltage of the type NMOS transistor is smaller than a turn-on voltage of the second type NMOS transistor.

8. The level shifting circuit of any one of claims 1-7 , further comprising a inverter coupled in series between the input node and the inverting input node, the inverter being powered by a second power supply.

9. The circuit of claim 8, further comprising a second inverter, wherein an output of the second inverter is connected to the input node, an input of the second inverter is used for receiving an input signal, and the second inverter is powered by the second power supply.

10. The level shift circuit of any of claims , further comprising a buffer having an input for receiving an input signal and an output coupled to the level shift unit.

Technical Field

The invention relates to the technical field of level conversion, in particular to level conversion circuits.

Background

In many semiconductor integrated circuits, circuit signals are not very stable in power-on or power-off processes of a power supply, and especially when power is supplied by using multiple power domains, the power-on or power-off sequence of each power domain is asynchronous, so that the circuit signals are easily uncontrollable, which is particularly obvious in a level conversion circuit, and directly causes errors in output signals of the level conversion circuit, and possibly generates a problem of large electric leakage and damages related devices.

Disclosure of Invention

Based on this, it is necessary to provide kinds of level shift circuits for the problem of the case where the output signal is erroneous due to the level shift circuits.

The embodiment of the invention provides level conversion circuits, which comprise a level conversion unit and a half feedback unit;

the level conversion unit includes: an input node, an output node to output an output signal having a desired level, an inverting input node, and an inverting output node to output an inverted output signal inverted from the output signal;

the half-side feedback unit is coupled between the output node and the inverted output node.

In embodiments, the level shift circuit further comprises a level shift accelerating unit coupled between the input stage of the level shift unit and the output stage of the level shift unit, and the level shift accelerating unit is configured to accelerate a level shift speed of the level shift unit.

In embodiments, the half-side feedback unit comprises a NMOS transistor, a NMOS transistor is coupled between the output node and the inverted output node, and a source of the NMOS transistor is connected to ground.

In embodiments, the level shifter unit comprises a PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor and a third NMOS transistor;

the source electrode of the PMOS tube is used for being connected with a power supply, the drain electrode of the PMOS tube is connected with the source electrode of the third PMOS tube, and the grid electrode of the PMOS tube is connected with the inverted output node;

the source electrode of the second PMOS tube is used for being connected with th power supply, the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube, and the grid electrode of the second PMOS tube is connected with the output node;

the grid electrode of the third PMOS tube is connected with the input node, and the drain electrode of the third PMOS tube is connected with the output node;

the grid electrode of the fourth PMOS tube is connected with the inverted input node, and the drain electrode of the third PMOS tube is connected with the inverted output node;

the grid electrode of the second NMOS tube is connected with the input node, the source electrode of the second NMOS tube is connected with the grounding point, and the drain electrode of the second NMOS tube is connected with the output node;

the grid electrode of the third NMOS tube is connected with the inverted input node, the source electrode of the third NMOS tube is connected with the grounding point, and the drain electrode of the third NMOS tube is connected with the inverted output node.

In embodiments, the level shift acceleration unit includes a fourth NMOS transistor and a fifth NMOS transistor, a drain of the fourth NMOS transistor is connected to the output node, a source of the fourth NMOS transistor is connected to a drain of the second NMOS transistor, a gate of the fourth NMOS transistor and a gate of the fifth NMOS transistor are both used for connecting a power supply, a drain of the fifth NMOS transistor is connected to the inverted output node, and a source of the fifth NMOS transistor is connected to a drain of the third NMOS transistor.

In embodiments, the second NMOS transistor and the third NMOS transistor are both NMOS transistors of type, and the th PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are all PMOS transistors of type.

In embodiments, the , the fourth and the fifth NMOS transistors are NMOS transistors of the second type, and the turn-on voltage of the NMOS transistor of the second type is smaller than that of the NMOS transistor of the second type.

In of the embodiments, the level shifter circuit further includes a th inverter connected in series between the input node and the inverting input node, the th inverter being powered by the second power supply.

In embodiments, the level shift circuit further comprises a second inverter, an output terminal of the second inverter is connected to the input node, an input terminal of the second inverter is used for inputting the input signal, and the second inverter is powered by the second power supply.

In embodiments, the level shift circuit further comprises a buffer, an input terminal of the buffer is used for inputting the input signal, and an output terminal of the buffer is connected with the level shift unit.

The or more embodiments provided by the invention have at least the following beneficial effects that the level conversion circuit provided by the embodiment of the invention comprises a level conversion unit and a half-edge feedback unit, wherein the level conversion unit comprises an input node, an output node used for outputting an output signal with a required level, an inverting input node and an inverting output node used for outputting an inverted output signal inverted with the output signal, and the half-edge feedback unit is coupled between the output node and the inverting output node.

Drawings

FIG. 1 is a schematic diagram of the structure of level shift units in an embodiment;

FIG. 2 is a schematic diagram of a level shifter circuit in embodiments;

FIG. 3 is a schematic diagram of another embodiments of level shifting circuits;

FIG. 4 is a schematic diagram of a level shifter circuit in another embodiments;

FIG. 5 is a schematic diagram of a level shifter circuit in another embodiments;

FIG. 6 is a schematic diagram of the structure of a level shifter circuit in further embodiments;

fig. 7 is a schematic diagram of the structure of the level shifter circuit in embodiments.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It should be noted that when elements are referred to as being "connected" to another elements, it may be directly connected to another elements and combined therewith to form , or intervening elements may be present.

The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention, the term "and/or" as used herein includes any and all combinations of or more of the associated listed items.

The embodiment of the invention provides level shift circuits, which comprise a level shift unit 10 and a half-edge feedback unit 20, wherein the level shift unit 10 comprises an input node, an output node a for outputting an output signal Vout with a required level, an inverting input node and an inverting output node b for outputting an inverted output signal Vout inverted to the output signal Vout, and the half-edge feedback unit 20 is coupled between the output node a and the inverting output node b.

The input node is an input node for receiving a signal with a predetermined level, the inverted input node is a node for receiving an electrical signal inverted from the signal with the level input by the input node, the output nodes a and b output inverted signals, the half-edge feedback unit 20 is a circuit for compensating the output signal Vout to make the output state of the output signal Vout predetermined when the output state is uncertain due to different power-on or power-off timings of the power supplies of the level shifter unit 10.

Specifically, for example, as shown in fig. 2 to 4, when the level shift unit 10 shown in fig. 1 is powered by multiple power supplies, and the output state of the output node a is uncertain when the power supply timing is different, the level shift circuit provided in the embodiment of the present invention, by coupling the half-edge feedback unit 20 between the output node a and the inverted output node b of the level shift unit 10, when the signal Vin is input to the level shift unit 10 through the input node and the inverted input node, and the level shift unit 10 is powered by multiple power supplies, if the power supply timings of the input stage and the output stage of the level shift unit 10 are different, the half-edge feedback unit 20 may be activated to operate during the power supply of at least power supplies, and the half-edge feedback unit 20 feeds back the output signal Vout of the output node a, so that the output node a outputs an electrical signal with a fixed state , that is, a desired level.

The level shift circuit provided by the embodiment of the invention comprises a level shift unit 10 and a half feedback unit 20, wherein the half feedback unit 20 is coupled between an output node a and an inverted output node b, and when the power-on or power-off time sequences of a plurality of power supplies of the level shift unit 10 are asynchronous, the output signal Vout is subjected to feedback compensation, so that the output node a outputs a signal determined by a high level or low level state.

In embodiments, as shown in fig. 5 to 7, the level shift circuit further includes a level shift accelerating unit 30, the level shift accelerating unit 30 is coupled between the input stage of the level shift unit 10 and the output stage of the level shift unit 10, and the level shift accelerating unit 30 is configured to accelerate the level shift speed of the level shift unit 10.

The level shift accelerating unit 30 is a circuit that can accelerate the level shift speed of the level shift unit 10. Specifically, the level shift accelerating unit 30 is coupled between the input stage of the level shift unit 10 and the output stage of the level shift unit 10, and under the power supply of the power supply and the action of the input signal Vin, the level shift accelerating unit 30 may select a low-voltage tube as a transistor device used in the input stage of the level shift unit 10, so as to accelerate the level shift speed of the level shift unit 10 on the premise of realizing the normal operation of the level shift unit 10.

In embodiments, as shown in fig. 2 and 3, the half-side feedback unit 20 includes a NMOS transistor Mn2, a NMOS transistor Mn2 coupled between the output node a and the inverted output node b, and a NMOS transistor Mn2 having a source connected to ground.

Specifically, if the gate and the drain of the 6 th NMOS transistor Mn are connected to the output node a and the inverted output node b, respectively, when the power supply timings of the plurality of power supply sources to the level conversion unit 10 are different, when a certain power supply source is supplied with power, the gate and the source of the NMOS transistor Mn are at a high potential, the drain and the source are at a low potential, so that the output node a outputs a high level, similarly, if the gate and the drain of the NMOS transistor Mn are connected to the inverted output node b and the output node a, respectively, when the power supply timings of the plurality of power supply sources to the level conversion unit 10 are different, when the power supply source of the NMOS transistor Mn is connected to the inverted output node b and the output node a, the gate and the source of the NMOS transistor Mn are at a high potential, the drain and the source are at a low potential, so that the output node a outputs a high level, the drain and the source of the NMOS transistor Mn are at a low potential, so that the power supply source of the NMOS transistor Mn and the drain of the NMOS transistor Mn are at a low potential, so that the output node b are connected, the drain of the NMOS transistor Mn, and the NMOS transistor Mn, so that the drain of the NMOS transistor Mn are connected to the drain of the output transistor Mn, the drain of the NMOS transistor Mn, and the drain of the NMOS transistor Mn, and the NMOS transistor Mn, respectively, and the NMOS transistor Mn, and the NMOS transistor, and the NMOS.

In one embodiment, as shown in fig. 2 to 4, the level shifter unit 10 includes a third PMOS transistor Mp, a second PMOS transistor Mp, a third PMOS transistor Mp, a fourth PMOS transistor Mp, a second NMOS transistor Mn, and a third NMOS transistor Mn, wherein a source of the third PMOS transistor Mp is connected to a third power supply Vd, a drain of the third PMOS transistor Mp is connected to a source of the third PMOS transistor Mp, a gate of the third PMOS transistor Mp is connected to an inverting output node b, a source of the second PMOS transistor Mp is connected to a second power supply Vd, a drain of the second PMOS transistor Mp is connected to a source of the fourth PMOS transistor Mp, a gate of the second PMOS transistor Mp is connected to an output node a, a gate of the third PMOS transistor Mp is connected to an input node, a drain of the third PMOS transistor Mp is connected to an output node a, a gate of the fourth PMOS transistor Mp is connected to an inverting input node, a drain of the third PMOS transistor Mp is connected to an inverting output node b, a gate of the second PMOS transistor Mn is connected to an inverting output node a, a drain of the second NMOS transistor Mn is connected to an inverting input node Mn, and a drain of the third PMOS transistor Mn is connected to an inverting output node Mn, and a drain of the third NMOS transistor Mn is connected to an inverting output node Mn.

In embodiments, as shown in fig. 5 and 6, the level shift accelerating unit 30 includes a fourth NMOS transistor Mn3 and a fifth NMOS transistor Mn4, a drain of the fourth NMOS transistor Mn3 is connected to the output node a, a source of the fourth NMOS transistor Mn3 is connected to the drain of the second NMOS transistor Mn0, a gate of the fourth NMOS transistor Mn3 and a gate of the fifth NMOS transistor Mn4 are both used to connect to the power supply Vd33, a drain of the fifth NMOS transistor Mn4 is connected to the inverted output node b, and a source of the fifth NMOS transistor Mn4 is connected to the drain of the third NMOS transistor Mn 1.

Specifically, as shown in fig. 5 and 6, the fourth NMOS transistor Mn3 and the fifth NMOS transistor Mn4 are coupled between the input end (input node, inverted input node) and the output end (output node a, inverted output node b) of the level shift unit 10, the fourth NMOS transistor Mn3 and the fifth NMOS transistor Mn4 may both be NMOS transistors of 3.3V, and under this condition, the second NMOS transistor Mn0 and the third NMOS transistor Mn1 may use low-voltage transistors lower than 3.3V, so as to increase the level shift speed of the level shift unit 10. It should be noted that the level shift accelerating unit 30 may further include other circuit structures, for example, as shown in fig. 7, the level shift accelerating unit 30 may further include a seventh NMOS transistor Mn6 and an eighth NMOS transistor Mn7, the seventh NMOS transistor Mn6 is coupled between the fourth NMOS transistor Mn3 and the second NMOS transistor Mn0, and the eighth NMOS transistor Mn7 is coupled between the fifth NMOS transistor Mn4 and the third NMOS transistor Mn 1.

In embodiments, the second NMOS transistor Mn0 and the third NMOS transistor Mn1 are both NMOS transistors of type , and the PMOS transistor Mp0, the second PMOS transistor Mp1, the third PMOS transistor Mp2 and the fourth PMOS transistor Mp3 are all PMOS transistors of type .

Specifically, the models of the second NMOS transistor Mn0 and the third NMOS transistor Mn1 can be the same and are symmetrically arranged, and the PMOS transistor Mp0, the second PMOS transistor Mp1, the third PMOS transistor Mp2 and the fourth PMOS transistor Mp3 can be transistors of the same model .

In embodiments, the th NMOS transistor Mn2, the fourth NMOS transistor Mn3 and the fifth NMOS transistor Mn4 are NMOS transistors of the second type, and the turn-on voltage of the th NMOS transistor is lower than that of the second NMOS transistor.

Specifically, the -th NMOS transistor Mn2, the fourth NMOS transistor Mn3, and the fifth NMOS transistor Mn4 may be NMOS transistors of the same model as , and the second NMOS transistor Mn0 and the third NMOS transistor Mn1 may be low-voltage transistors having a voltage lower than the -th NMOS transistor Mn2, the fourth NMOS transistor Mn3, and the fifth NMOS transistor Mn 4. for example, the -th NMOS transistor Mn2, the fourth NMOS transistor Mn3, and the fifth NMOS transistor Mn4 may be NMOS transistors of 3.3V, and the second NMOS transistor Mn0 and the third NMOS transistor Mn1 may be low-voltage NMOS transistors of 2.5V.

In embodiments, as shown in fig. 2-7, the level shift circuit further includes a inverter INV2 connected in series between the input node and the inverting input node, the inverter INV2 is powered by a second power supply Vd12, specifically, the inverter INV2 is directly connected in series between the input node and the inverting input node, the inverter INV2 is powered by the second power supply Vd12, when an input signal Vin is input from the input node, i.e. the input end of the inverter, the input signal Vin between the input node and the inverting input node can be ensured to be inverted.

In practical application, if the above problem occurs, that is, the power-on or power-off timing sequence of the power supply is different, the circuit structures shown in fig. 2, 4, 5, and 7 may ensure that the output is at a high level, and the circuit structures shown in fig. 3 and 6 may ensure that the output is at a low level.

In embodiments, the level shifter circuit further includes a second inverter INV1, an output end of the second inverter INV1 is connected to the input node, an input end of the second inverter INV1 is used for receiving the input signal Vin, and the second inverter INV1 is powered by the second power supply Vd 12.

Specifically, as shown in fig. 2, for example, when power is supplied to different power domains, the second power supply Vd is powered on slower than the 0 th power supply Vd, power supply to the 1 st power supply Vd is completed, power supply to the 2 nd inverter INV and the second inverter INV is not completely established, so that the output states of the first inverter INV and the second inverter INV are uncertain, and the third PMOS transistor Mp and the fourth PMOS transistor Mp in the level conversion unit 10 are turned on, the output voltage levels of the output node a and the inverted output node b in the level conversion unit 10 may be an intermediate voltage, when the output voltages of the output node a and the inverted output node b are the intermediate voltage, the NMOS transistor Mn in the level conversion unit 10 may be in an amplification state, a positive feedback loop composed of the NMOS transistor Mn, the PMOS transistor Mp and the third PMOS transistor Mp in the level conversion unit 10 is established, so that the voltage level of the output node a is increased quickly to a high level, and the output voltage level of the inverted output signal V is equal to a high level, so that the output voltage level of the power supply voltage of the second power supply is equal to V3.

In embodiments, as shown in fig. 2-7, the level shift circuit further includes a buffer, an input terminal of the buffer is used for receiving the input signal Vin, and an output terminal of the buffer is connected to the level shift unit 10. in particular, the buffer is terminated at the input terminal of the level shift unit 10 to implement the buffering function for the input signal Vin.

In embodiments, as shown in fig. 2-7, the buffer includes two inverters connected in series, specifically, the buffer period may include the th inverter INV2 and the second inverter INV1, which function as an input buffer.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.