阅读说明：本技术 电平转换器 (Level shifter ) 是由 曹亚历 邵博闻 于 2019-10-21 设计创作，主要内容包括：本申请涉及数字集成电路技术领域,具体涉及一种电平转换器,包括：逻辑运算电路、电平转换电路、下电自保持电路和输出电路；逻辑运算电路用于对输入信号进行逻辑运算,并输出控制信号给电平转换电路；电平转换电路用于根据所接收到的控制信号输出电平转换信号；下电自保持电路,下电自保持电路连接在电平转换电路和输出电路之间,用于根据下电信号控制电平转换信号自保持输出。本申请通过逻辑运算电路使得满足特定逻辑关系的输入信号能够控制电平转换电路进行高低电平转换,转换后的电平转换信号经过下电自保持电路,即使电路发出下电信号,电平转换信号仍能够自保持输出,记忆下电前电平转换器的输出电平。(The application relates to the technical field of digital integrated circuits, in particular to level converters which comprise a logic operation circuit, a level conversion circuit, a power-down self-holding circuit and an output circuit, wherein the logic operation circuit is used for carrying out logic operation on an input signal and outputting a control signal to the level conversion circuit, the level conversion circuit is used for outputting a level conversion signal according to the received control signal, and the power-down self-holding circuit is connected between the level conversion circuit and the output circuit and used for controlling self-holding output of the level conversion signal according to the power-down signal.)

1, kinds of level shifters, wherein the level shifter comprises a logic operation circuit, a level shift circuit, a power-down self-holding circuit and an output circuit;

the logic operation circuit is used for performing logic operation on an input signal and outputting a control signal to the level conversion circuit;

the level conversion circuit is used for outputting a level conversion signal according to the received control signal;

and the power-down self-holding circuit is connected between the level conversion circuit and the output circuit and is used for controlling the self-holding output of the level conversion signal according to a power-down electric signal.

2. The level shifter of claim 1, wherein the level shifter circuit comprises PMOS transistors and a second PMOS transistor;

the th PMOS tube and the second PMOS tube have source electrodes connected with each other and are connected with an external high level signal, the gate electrode of the th PMOS tube is connected with the drain electrode of the second PMOS tube to form an electric node, and the drain electrode of the th PMOS tube is connected with the gate electrode of the second PMOS tube to form a second node;

the th node and the second node are respectively and correspondingly connected with the th output end and the second output end of the logic operation circuit.

3. The level shifter of claim 2, wherein the logical operation circuit includes an th logical operation circuit and a second logical operation circuit;

the th logic operation circuit comprises a th signal input end and a second signal input end, and the output end of the th logic operation circuit is the th output end of the logic operation circuit;

the second logic operation circuit comprises an th signal inverting input end and a second signal inverting input end, and the output end of the second logic operation circuit is a second output end of the logic operation circuit.

4. The level shifter of claim 3, wherein the -th logical operation circuit is a NAND circuit, and the second logical operation circuit is a NOR circuit.

5. The level shifter of claim 3 or 4, wherein the th logic operation circuit comprises a th NMOS transistor and a second NMOS transistor;

the source electrode of the NMOS transistor is connected with the drain electrode of the second NMOS transistor, the source electrode of the second NMOS transistor is grounded, and the drain electrode of the NMOS transistor is the output end of the logical operation circuit;

the gate of the NMOS transistor is the signal input terminal of the logical operation circuit, and the gate of the second NMOS transistor is the second signal input terminal of the logical operation circuit.

6. The level shifter of any , wherein the second logic operation circuit comprises a third NMOS transistor and a fourth NMOS transistor;

the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube are connected to form the output end of the second logic operation circuit, and the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are connected and grounded;

the grid electrode of the third NMOS tube is the signal inverting input end of the second logic operation circuit, and the grid electrode of the fourth NMOS tube is the second signal inverting input end of the second logic operation circuit.

7. The level shifter of claim , wherein the output circuit comprises a inverter and a second inverter connected in series, wherein an input of the inverter is an input of the output circuit, and an output of the second inverter is an output of the output circuit.

8. The level shifter of any , wherein the power down self-holding circuit comprises a transmission control circuit and a level holding circuit;

the transmission control circuit is connected between the output end of the level conversion circuit and the input end of the output circuit and is used for controlling the on-off of the output end of the level conversion circuit;

the acquisition terminal M4 of the level holding circuit is connected with the output terminal of the th inverter, and the output control terminal M3 of the level holding circuit is connected with the input terminal of the th inverter.

9. The level shifter of any , wherein the transmission control circuit comprises a third PMOS transistor and a fifth NMOS transistor;

the source electrode of the third PMOS tube is connected with the source electrode of the fifth NMOS tube and connected to the input end of the output circuit, and the drain electrode of the third PMOS tube is connected with the drain electrode of the fifth NMOS tube and connected to the output end of the level conversion circuit;

the grid electrode of the third PMOS tube is used for being connected with a power-off control signal, the grid electrode of the fifth NMOS tube is used for being connected with an inverted power-off control signal, and the phase of the power-off control signal is opposite to that of the inverted power-off control signal.

10. The level shifter of any , wherein the level hold circuit comprises a fourth PMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor connected in series in sequence;

a source electrode of the fourth PMOS tube is connected with an external high-level signal, and a grid electrode of the fourth PMOS tube is connected with a grid electrode of the seventh NMOS tube to form the acquisition end;

the drain electrode of the fifth PMOS tube is connected with the drain electrode of the sixth NMOS tube to form the output control end;

the grid electrode of the fifth PMOS tube is used for being connected with the inverted power-off control signal, and the sixth NMOS tube is used for being connected with the power-off control signal.

Technical Field

The application relates to the technical field of digital integrated circuits, in particular to level converters.

Background

The level shifter is widely used in the field of digital circuits, since different digital circuits need to match their levels when they work in coordination, the voltage domain conversion needs to be implemented by the level shifter.

Disclosure of Invention

The application provides level shifters, which can solve the problem of information loss at the power-down moment of the level shifters in the related art.

, the embodiment of the application provides kinds of level shifters, which include a logic operation circuit, a level shift circuit, a power-down self-holding circuit and an output circuit;

the logic operation circuit is used for performing logic operation on the input signal and outputting a control signal to the level conversion circuit;

the level conversion circuit is used for outputting a level conversion signal according to the received control signal;

and the power-down self-holding circuit is connected between the level conversion circuit and the output circuit and is used for controlling the self-holding output of the level conversion signal according to the power-down signal.

Optionally, the level shifter circuit includes th PMOS transistor and a second PMOS transistor;

the PMOS tube and the second PMOS tube have source electrodes connected with each other and external high level signals, the gate electrode of the PMOS tube is connected with the drain electrode of the second PMOS tube to form an electric node, and the drain electrode of the PMOS tube is connected with the gate electrode of the second PMOS tube to form a second node;

the node and the second node are respectively connected to the output terminal and the second output terminal of the logic operation circuit.

Optionally, the logic operation circuit comprises an th logic operation circuit and a second logic operation circuit;

the th logical operation circuit comprises a th signal input end and a second signal input end, and the output end of the th logical operation circuit is the th output end of the logical operation circuit;

the second logic operation circuit comprises an th signal inverting input terminal and a second signal inverting input terminal, and the output terminal of the second logic operation circuit is the second output terminal of the logic operation circuit.

Optionally, the th logical operation circuit is a nand circuit, and the second logical operation circuit is a nor circuit.

Optionally, the th logic operation circuit comprises a th NMOS transistor and a second NMOS transistor;

the source electrode of the NMOS transistor is connected with the drain electrode of the second NMOS transistor, the source electrode of the second NMOS transistor is grounded, and the drain electrode of the NMOS transistor is the output end of the logical operation circuit;

the gate of the NMOS transistor is the signal input terminal of the logical operation circuit, and the gate of the second NMOS transistor is the second signal input terminal of the logical operation circuit.

Optionally, the second logic operation circuit includes a third NMOS transistor and a fourth NMOS transistor;

the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube to form the output end of the second logic operation circuit, and the source electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube and is grounded;

the grid electrode of the third NMOS tube is the th signal inverting input end of the second logic operation circuit, and the grid electrode of the fourth NMOS tube is the second signal inverting input end of the second logic operation circuit.

Optionally, the output circuit comprises an th inverter and a second inverter which are connected in series, wherein an input end of the th inverter is an input end of the output circuit, and an output end of the second inverter is an output end of the output circuit.

Optionally, the power-down self-holding circuit includes a transmission control circuit and a level holding circuit;

the transmission control circuit is connected between the output end of the level conversion circuit and the input end of the output circuit and is used for controlling the on-off of the output end of the level conversion circuit;

the acquisition end of the level holding circuit is connected with the output end of the th inverter, and the output control end of the level holding circuit is connected with the input end of the th inverter.

Optionally, the transmission control circuit includes a third PMOS transistor and a fifth NMOS transistor;

the source electrode of the third PMOS tube is connected with the source electrode of the fifth NMOS tube and connected to the input end of the output circuit, and the drain electrode of the third PMOS tube is connected with the drain electrode of the fifth NMOS tube and connected to the output end of the level conversion circuit;

the grid electrode of the third PMOS tube is used for being connected with a power-off control signal, the grid electrode of the fifth NMOS tube is used for being connected with an inverted power-off control signal, and the phase of the power-off control signal is opposite to that of the inverted power-off control signal.

Optionally, the level holding circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor connected in series in sequence;

a source electrode of the fourth PMOS tube is connected with an external high-level signal, and a grid electrode of the fourth PMOS tube is connected with a grid electrode of the seventh NMOS tube to form a collecting end;

the drain electrode of the fifth PMOS tube is connected with the drain electrode of the sixth NMOS tube to form an output control end;

the grid electrode of the fifth PMOS tube is used for connecting the inverted power-off control signal, and the sixth NMOS tube is used for connecting the power-off control signal.

The technical scheme at least comprises the following advantages: the level shifter can avoid calling various chips, the input signal meeting specific logic relation can control the level shifter circuit to perform high-low level shift through the logic operation circuit, the level shift signal after the shift passes through the power-off self-holding circuit, if the power-off self-holding circuit sends a power-off signal, the level shift signal can still be output in a self-holding mode, and the influence on the output of the signal due to the power-off of the circuit is avoided.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic block circuit diagram of an embodiment of the present application.

Fig. 2 is a circuit diagram of an embodiment of the present application.

Fig. 3 is a simulation diagram of an embodiment of the present application.

100. Logic operation circuit, 110, th logic operation circuit, 120, second logic operation circuit, 200, level conversion circuit, 300, power-down self-holding circuit, 310, transmission control circuit, 320, level holding circuit.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are partial embodiments of the present application, rather than complete embodiments.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application.

In the description of the present application, it should be noted that unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" shall be construed , and for example, they may be fixed or detachable connections or physical connections, mechanical or electrical connections, direct or indirect connections via an intermediate medium, communication between two elements, wireless or wired connections.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

The present application provides level shifters, as shown in fig. 1, each of which includes a logic operation circuit 100, a level shift circuit 200, a power-down self-holding circuit 300, and an output circuit, wherein the logic operation circuit 100 is configured to perform a logic operation on an input signal and output a control signal to the level shift circuit 200, the level shift circuit 200 is configured to output a level shift signal according to the received control signal, and the power-down self-holding circuit 300 is connected between the level shift circuit 200 and the output circuit, and is configured to control a self-holding output of the level shift signal according to the power-down signal.

The level shifter enables the input signal meeting the specific logic relationship to control the level shifter circuit 200 to perform high-low level shifting through the logic operation circuit 100, the shifted level shifter signal passes through the power-down self-holding circuit 300, and if the power-down self-holding circuit 300 sends a power-down signal, the level shifter signal can still be output in a self-holding manner, so that the influence on the signal output due to the power-down of the circuit is avoided.

As shown in fig. 2, the level shifter circuit 200 includes th PMOS transistor P1 and second PMOS transistor P2, the sources of the th PMOS transistor P1 and second PMOS transistor P2 are connected to connect an external high level signal VDDG, the gate of the th PMOS transistor P1 is connected to the drain of the second PMOS transistor P2 to form an electrical node M1, the drain of the th PMOS transistor P1 is connected to the gate of the second PMOS transistor P2 to form a second node M2, the first node M1 and the second node M2 are respectively connected to the first output terminal and the second output terminal of the logic operation circuit 100, and the second node M2 is the output terminal of the level shifter circuit 200.

If the input signal satisfies the logic relationship of the logic operation circuit 100, the output terminal of the logic operation circuit 100 outputs a low level, the node M1 is a low level, the PMOS transistor P1 is turned on and the second PMOS transistor P2 is turned off, so that the second node M2 is pulled high, and the voltage thereof is equal to the voltage of the external high level signal VDDG, optionally, the voltage of VDDG is 1.387v, so that the voltage domain conversion can be realized by adjusting the magnitude of VDDG.

The logic operation circuit 100 comprises an th logic operation circuit 110 and a second logic operation circuit 120, the th logic operation circuit 110 comprises a th signal input terminal A and a second signal input terminal B, the output terminal of the th logic operation circuit 110 is the th output terminal of the logic operation circuit 100, the second logic operation circuit 120 comprises a th signal inverting input terminal AB and a second signal inverting input terminal BB, and the output terminal of the second logic operation circuit 120 is the second output terminal of the logic operation circuit 100.

When the signal input from the th signal input terminal a and the signal input from the second signal input terminal B are both at high level, the th output terminal of the logic operation circuit 100 outputs low level, the second output terminal of the logic operation circuit 100 outputs high level, that is, the output terminal of the th logic operation circuit 110 outputs low level, and the output terminal of the second logic operation circuit 120 outputs high level, optionally, the th logic operation circuit 110 is a nand circuit, and the second logic operation circuit 120 is a nor circuit, and the signal input from the th signal input terminal a and the signal input from the th signal inverting input terminal AB are inverted, and the signal input from the second signal input terminal B and the signal input from the second signal inverting input terminal AB are inverted, so that the th PMOS transistor P1 and the second PMOS transistor P2 are alternately turned on by controlling the logical relationship of the two input signals, thereby controlling the level shift circuit 200 to output level shift signals.

The th logic operation circuit 110 comprises a th NMOS transistor N1 and a second NMOS transistor N2, wherein the source of the th NMOS transistor N1 is connected with the drain of the second NMOS transistor N2, the source of the second NMOS transistor N2 is grounded, the drain of the th NMOS transistor N1 is the output end of the th logic operation circuit 110, the gate of the th NMOS transistor N1 is the th signal input end A of the th logic operation circuit 110, and the gate of the second NMOS transistor N2 is the second signal input end B of the th logic operation circuit 110.

The NMOS transistor N1 and the second NMOS transistor N2 are connected in series, the drain of the NMOS transistor N1 is the output end of the logical operation circuit 110, and when and only when the signal input end A and the second signal input end B both input high levels, the drain of the NMOS transistor N1 is low level, so that the PMOS transistor P1 is turned on, and the second node M2 is high level.

The second logic operation circuit 120 comprises a third NMOS transistor N3 and a fourth NMOS transistor N4, the drain electrode of the third NMOS transistor N3 is connected with the drain electrode of the fourth NMOS transistor N4 to form the output end of the second logic operation circuit 120, the source electrode of the third NMOS transistor N3 is connected with the source electrode of the fourth NMOS transistor N4 and is grounded, the grid electrode of the third NMOS transistor N3 is the signal inversion input end AB of the of the second logic operation circuit 120, and the grid electrode of the fourth NMOS transistor N4 is the signal inversion input end AB of the second logic operation circuit 120.

The third NMOS tube N3 and the fourth NMOS tube N4 are connected in parallel, when the signal inverting input end AB or the second signal inverting input end AB inputs high level, the second node M2 is low level, the PMOS tube P1 is conducted, and a NOR circuit is realized through a small number of MOS tubes, so that the layout area can be reduced, and the circuit delay path is avoided.

The output circuit comprises an th inverter D1 and a second inverter D2 which are connected in series, the input end of the th inverter D1 is the input end of the output circuit, the output end of the second inverter D2 is the output end of the output circuit, the power-down self-holding circuit 300 comprises a transmission control circuit 310 and a level holding circuit 320, the transmission control circuit 310 is connected between the output end of the level conversion circuit 200 and the input end of the output circuit and used for controlling the on-off of the output end of the level conversion circuit 200, an acquisition end M4 of the level holding circuit 320 is connected with the output end of the th inverter D1, and an output control end M3 of the level holding circuit 320 is connected with the input end of the D1 of the th inverter.

The level hold circuit 320 is connected in parallel to both ends of the th inverter D1, and when the transmission control circuit 310 controls the output terminal of the level shift circuit 200 to be open, the level hold circuit 320 and the th inverter D1 together implement a signal self-locking function, so that when the output terminal of the level shift circuit 200 is open, the level shifter can still output a level signal before the open circuit.

The transmission control circuit 310 comprises a third PMOS transistor P3 and a fifth NMOS transistor N5; the source electrode of the third PMOS tube P3 and the source electrode of the fifth NMOS tube N5 are connected in parallel and connected to the input end of the output circuit, and the drain electrode of the third PMOS tube P3 and the drain electrode of the fifth NMOS tube N5 are connected in parallel and connected to the output end of the level shift circuit 200; the gate of the third PMOS transistor P3 is connected to the power-down control signal SLEEP, and the gate of the fifth NMOS transistor N5 is connected to the inverted power-down control signal SLEEP, which is opposite in phase to the inverted power-down control signal SLEEP.

When the blanking control signal SLEEP is at a high level, the inverted blanking control signal SLEEP b is at a low level, so that the third PMOS transistor P3 and the fifth NMOS transistor N5 are both turned off, and thus the output end of the level shift circuit 200 is open, and the input end of the th inverter D1 in the initial state when the output end of the level shift circuit 200 is open is at a high level, and the level shifter output is still at a high level after being inverted twice by the th inverter D1 and the second inverter D2, and because the level hold circuit 320 and the th inverter D1 jointly implement the signal latching function, the input end of the th inverter D1 can still be kept at a high level after the output end of the level shift circuit 200 is open, and thus the level shifter output is still at a high level.

The level holding circuit 320 comprises a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth NMOS transistor N6 and a seventh NMOS transistor N7 which are sequentially connected in series; the source electrode of the fourth PMOS tube P4 is connected with an external high-level signal, and the grid electrode of the fourth PMOS tube P4 is connected with the grid electrode of the seventh NMOS tube N7 to form a collecting end M4; the drain electrode of the fifth PMOS pipe P5 and the drain electrode of the sixth NMOS pipe N6 are connected to form an output control end M3; the gate of the fifth PMOS transistor P5 is connected to the inverted power-down control signal SLEEP, and the sixth NMOS transistor N6 is connected to the power-down control signal SLEEP.

When the power is off, the power-off control signal SLEEP is at a high level, the reverse phase power-off control signal slepb is at a low level, that is, the fifth PMOS transistor P5 and the sixth NMOS transistor N6 are both turned on, the fourth PMOS transistor P4 and the seventh NMOS transistor N7 form sets of inverters, and since the inverters are connected in parallel to the two ends of the inverter D1, a self-locking cycle is formed from the output control terminal M3 to the acquisition terminal M4 to the control terminal M3, so that the state of the initial level of the output control terminal M3 can be maintained, and the state of the initial level of the output control terminal M3 is the level state of the output control terminal M3 at the power-off time of the power-off self-holding circuit 300, so that the level switching signal can be self-held to be output after the.

FIG. 3 is a simulation of the present application, wherein A is a voltage signal in the time domain of the th signal input terminal A, B is a voltage signal in the time domain of the second signal input terminal B, X is a voltage signal in the time domain of the output terminal X of the level shifter, SLEEP is a voltage in the time domain of the power-down control signal SLEEP, VDDL is a voltage of the external low level signal VDDL applied to the inverter during the process of the th signal input terminal A and the second signal input terminal B respectively passing through the inverter to obtain the th signal inverting input terminal AB and the second signal inverting input terminal BB;

in the time period of T1, the signal input at the signal input terminal a of is at high level, the signal input at the second signal input terminal is at low level, the power-down control signal SLEEP is at low level, that is, the transmission control circuit 310 is a path, the external high-level signal VDDG is at high level, the output terminal X of the level shifter outputs low level, VDDH represents the voltage of the external high-level signal, M3 represents the voltage of the output control terminal M3 of the level hold circuit, and M4 represents the voltage of the acquisition terminal M4 of the level hold circuit.

In the time period T2, the signal input at the signal input terminal a is at a high level, the signal input at the second signal input terminal is at a high level, the power-down control signal SLEEP is at a low level, that is, the transmission control circuit 310 is a pass, the external high-level signal VDDG is at a high level, and the output terminal X of the level shifter of the present application outputs a high level;

the signal input by the signal input end A of is high level, the signal input by the second signal input end is high level, namely the transmission control circuit 310 is open circuit, the external high level signal VDDG is high level, the output end X of the level shifter outputs low level;

the signal input by the signal input end A of is high level in the T6 time period, the signal input by the second signal input end is high level, the lower electric control signal SLEEP is low level, namely the transmission control circuit 310 is a pass, the external high level signal VDDG is high level, the output end X of the level shifter outputs high level;

during the period T7, the output terminal X of the level shifter should be kept at the high level output of the previous period, and the voltage at the output terminal X of the level shifter is dropped because the external high level signal VDDG is low.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.