Integrated circuit device and method for generating layout of integrated circuit unit
阅读说明:本技术 集成电路器件和集成电路单元的布局图生成方法 (Integrated circuit device and method for generating layout of integrated circuit unit ) 是由 陈建盈 鲁立忠 田丽钧 郭大鹏 于 2019-05-29 设计创作,主要内容包括:生成IC单元的布局图的方法包括通过以下步骤限定所述单元的边界的边界凹槽:所述边界的第一部分沿着第一方向延伸;所述边界的第二部分在垂直于所述第一方向的第二方向上远离所述第一部分延伸,所述第二部分与所述第一部分是连续的;以及所述边界的第三部分在所述第二方向上远离所述第一部分延伸,所述第三部分与所述第一部分是连续的。通过所述有源区在与所述第二方向相反的第三方向上远离所述第一部分延伸将有源区定位在所述单元中。所述布局图存储在非暂时性计算机可读介质中。本发明的实施例还提供了集成电路(IC)器件。(A method of generating a layout of an IC cell includes defining a boundary recess of a boundary of the cell by: a first portion of the boundary extending along a first direction; a second portion of the boundary extending away from the first portion in a second direction perpendicular to the first direction, the second portion being continuous with the first portion; and a third portion of the boundary extending away from the first portion in the second direction, the third portion being continuous with the first portion. An active region is positioned in the cell by the active region extending away from the first portion in a third direction opposite the second direction. The map is stored in a non-transitory computer readable medium. Embodiments of the invention also provide Integrated Circuit (IC) devices.)
1. A method of generating a layout of Integrated Circuit (IC) cells, the IC layout being stored on a non-volatile computer-readable medium, the method comprising:
a boundary groove defining a boundary of the cell by:
a first portion of the boundary extending along a first direction;
a second portion of the boundary extending away from the first portion in a second direction perpendicular to the first direction, the second portion being continuous with the first portion; and
a third portion of the boundary extending away from the first portion in the second direction, the third portion being continuous with the first portion; and
an active region is positioned in the cell by the active region extending away from the first portion in a third direction opposite the second direction.
2. The method of claim 1, further comprising: based on the integrated circuit layout, at least one of:
one or more semiconductor masks; or
At least one component in the semiconductor integrated circuit layer.
3. The method of claim 1, wherein,
the active region is a first active region of a plurality of active regions in the cell; and
the method further includes positioning a second active region of the plurality of active regions by the second active region extending away from the first portion in the third direction.
4. The method of claim 3, wherein,
positioning the first active region of the plurality of active regions comprises: the first active region comprising the plurality of active regions in a PMOS device; and
positioning the second active region of the plurality of active regions comprises: the second active region of the plurality of active regions is included in an NMOS device.
5. The method of claim 1, wherein the first and second light sources are selected from the group consisting of,
the active region is a first active region of a plurality of active regions in the cell, each active region of the plurality of active regions extending in the third direction, an
The method further includes positioning a second active region of the plurality of active regions and a third active region of the plurality of active regions by aligning the second active region, the third active region, the second portion, and the third portion along the first direction.
6. The method of claim 5, wherein,
positioning the second active region of the plurality of active regions comprises: the second active region comprising the plurality of active regions in a PMOS device; and
positioning the third active region of the plurality of active regions comprises: the third active region of the plurality of active regions is included in an NMOS device.
7. The method according to claim 1, wherein the boundary recess defining the boundary of the cell comprises a boundary projection defining the boundary by:
a fourth portion of the boundary extends in the first direction;
a fifth portion of the boundary extending away from the fourth portion in the second direction, the fifth portion being continuous with the fourth portion; and
a sixth portion extending away from the fourth portion in a second direction, the sixth portion being continuous with the fourth portion;
wherein the active region is located between the first portion and the fourth portion.
8. The method of claim 7, wherein,
the active region is a first active region of a plurality of active regions in the cell, each active region of the plurality of active regions extending in the third direction,
the boundary groove defining the boundary of the cell further includes: a seventh portion of the boundary extending in the second direction, the seventh portion being discontinuous from the fourth portion and parallel to the fifth portion and the sixth portion, an
The method further comprises: positioning the second active region of the plurality of active regions by aligning the first active region of the plurality of active regions, a second active region of the plurality of active regions, the fifth portion, the sixth portion, and the seventh portion in the first direction.
9. A method of generating a layout of an Integrated Circuit (IC), the integrated circuit layout being stored on a non-volatile computer-readable medium, the method comprising:
abutting a first cell to a second cell in the integrated circuit layout by:
the boundary protrusion of the first unit is fitted in the boundary groove of the second unit, and
a first gate region of the integrated circuit layout is caused to intersect the boundary protrusion and intersect the first active region of the second cell.
10. An Integrated Circuit (IC) device, comprising:
a plurality of active regions, each of the plurality of active regions extending in a first direction; and
a first gate structure extending in a second direction perpendicular to the first direction, the first gate structure being located over each of the plurality of active regions;
wherein the content of the first and second substances,
a first active region of the plurality of active regions is located between the second active region of the plurality of active regions and a third active region of the plurality of active regions,
the first gate structure is located over an edge of the first active region of the plurality of active regions, an
Each of the second active region of the plurality of active regions and the third active region of the plurality of active regions extends through the first gate structure.
Technical Field
Embodiments of the invention relate generally to the field of semiconductor technology and, more particularly, relate to an integrated circuit device and a method of generating a layout of integrated circuit cells.
Background
Integrated Circuits (ICs) typically include a large number of semiconductor devices, also referred to as IC devices. One way to represent an IC device is a plan view called a layout or IC layout. The IC layout is hierarchical and includes modules that perform high-level functions according to the design specifications of the IC device. Modules are typically built from a combination of cells that may include standard cells and custom cells (custom cells), where each module includes one or more semiconductor structures.
The cell is configured to provide a common, low-level function typically performed by transistors based on a gate region that intersects an active region, sometimes referred to as an Oxide Definition (OD) region. The elements of the cell are arranged within the cell boundaries and are electrically connected to other cells through interconnect structures.
Disclosure of Invention
According to an aspect of the invention, there is provided a method of generating a layout of an Integrated Circuit (IC) cell, the integrated circuit layout being stored on a non-volatile computer-readable medium, the method comprising: a boundary groove defining a boundary of the cell by: a first portion of the boundary extending along a first direction; a second portion of the boundary extending away from the first portion in a second direction perpendicular to the first direction, the second portion being continuous with the first portion; and a third portion of the boundary extending away from the first portion in the second direction, the third portion being continuous with the first portion; and positioning an active region in the cell by the active region extending away from the first portion in a third direction opposite the second direction.
According to another aspect of the present invention, there is provided a method of generating a layout of an Integrated Circuit (IC), the integrated circuit layout being stored on a non-volatile computer-readable medium, the method comprising: abutting a first cell to a second cell in the integrated circuit layout by: the boundary protrusion of the first cell fits within the boundary recess of the second cell, and the first gate region of the integrated circuit layout intersects the boundary protrusion and intersects the first active region of the second cell.
According to still another aspect of the present invention, there is provided an Integrated Circuit (IC) device including: a plurality of active regions, each of the plurality of active regions extending in a first direction; and a first gate structure extending in a second direction perpendicular to the first direction, the first gate structure being located over each of the plurality of active regions; wherein a first active region of the plurality of active regions is located between the plurality of active region second active regions and a third active region of the plurality of active regions, the first gate structure is located over an edge of the first active region of the plurality of active regions, and each of the second active region of the plurality of active regions and the third active region of the plurality of active regions extends through the first gate structure.
Drawings
Various aspects of the invention are better understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a flow diagram of a method of generating a layout diagram of an IC according to some embodiments.
Fig. 2 illustrates an IC layout diagram according to some embodiments.
Fig. 3 illustrates an IC layout diagram according to some embodiments.
Fig. 4 illustrates an active region according to some embodiments.
Fig. 5A is a schematic representation of an IC corresponding to an IC layout diagram according to some embodiments.
Fig. 5B 1-
Fig. 6 is a flow diagram of a method of generating a layout diagram of an IC according to some embodiments.
Fig. 7 illustrates an IC layout diagram according to some embodiments.
Fig. 8 illustrates an IC layout diagram according to some embodiments.
Fig. 9 illustrates an IC layout diagram according to some embodiments.
Fig. 10 illustrates an IC layout diagram according to some embodiments.
Fig. 11 illustrates an IC device according to some embodiments.
Fig. 12 illustrates an IC device according to some embodiments.
Fig. 13 is a schematic diagram of an Electronic Design Automation (EDA) system, in accordance with some embodiments.
Fig. 14 is an IC manufacturing system and IC manufacturing flow associated therewith, in accordance with some embodiments.
Detailed Description
The present disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, configurations, etc., are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second portions are not in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. These iterations are for simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms (such as "below …," "below …," "lower," "above," "upper," etc.) may be used for ease of description to describe one element or component's relationship to another element(s) or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In various embodiments, the IC layout comprises: a first unit having a boundary protrusion on one side; a second cell having a matching boundary groove on a side adjacent the first cell such that when the cells are adjacent in the layout method, the protrusion fits within the groove. The resulting layout can thus intersect the active regions in the protrusions of the first cell and extend into the second cell with gate regions that can be used to define the transistors. The IC layout of the various embodiments, and IC devices based on the IC layout, avoid the use of dummy gate regions at cell boundaries, thereby reducing area requirements as compared to methods that do not include gate regions that can define transistors in a first cell and extend into a second cell.
Fig. 1 is a flow diagram of a
In some embodiments, some or all of the operations of
In some embodiments, some or all of the operations of
In some embodiments, some or all of the operations of
In some embodiments, the operations of
In some embodiments, FIGS. 2-4 and 5B 1-
Each of fig. 2-4 and 5B 1-
The X direction includes a positive X direction shown in fig. 2 to 4 and 5B1 to 5H2 and a negative X direction (not labeled) opposite to the positive X direction. The Y direction includes a positive Y direction shown in fig. 2 to 4 and 5B1 to 5H2 and a negative Y direction (not labeled) opposite to the positive Y direction.
Fig. 2 illustrates an
Fig. 3 illustrates an
In addition to
In various embodiments, one or both of the cells of
In various embodiments, one or both of
As shown in FIG. 2, the
The portion B1 extends in the positive X direction from a point corresponding to the gate rail T1 to a point corresponding to the gate rail T5. Portion B2 extends in the negative Y-direction along gate rail T5 from portion B1 to portion B3. In various embodiments, portion B1 extends from a location other than the point corresponding to gate track T1 and/or portion B1 extends to a location other than the point corresponding to gate track T5, and portion B2 extends along a location other than gate track T5.
The portion B3 extends in the positive X direction from the portion B2 to a point corresponding to the gate rail T6. Portion B4 extends in the negative Y direction along gate rail T6 from portion B3 to portion B5. In various embodiments, portion B3 extends from a location other than the point corresponding to gate track T5 and/or portion B3 extends to a location other than the point corresponding to gate track T6, and portion B4 extends along a location other than gate track T6.
The portion B5 extends in the negative X direction from the portion B4 to a point corresponding to the gate rail T5. Portion B6 extends in the negative Y direction along gate rail T5 from portion B5 to portion B7. In various embodiments, portion B5 extends from a location other than the point corresponding to gate track T6 and/or portion B5 extends to a location other than the point corresponding to gate track T5 and portion B6 extends along a location other than gate track T5.
The portion B7 extends in the negative X direction from the portion B6 to a point corresponding to the gate rail T1. Portion B8 extends in the positive Y-direction along gate rail T1 from portion B7 to portion B9. In various embodiments, portion B7 extends from a location other than the point corresponding to gate track T5 and/or portion B7 extends to a location other than the point corresponding to gate track T1 and portion B8 extends along a location other than gate track T1.
The portion B9 extends in the positive X direction from the portion B8 to a point corresponding to the gate rail T2. Portion B10 extends in the positive Y-direction along gate rail T2 from portion B9 to portion B11. In various embodiments, portion B9 extends from a location other than the point corresponding to gate track T1 and/or portion B9 extends to a location other than the point corresponding to gate track T2 and portion B10 extends along a location other than gate track T2.
The portion B11 extends in the negative X direction from the portion B10 to a point corresponding to the gate rail T1. Portion B12 extends in the positive Y-direction along gate rail T1 from portion B11 to portion B1. In various embodiments, portion B11 extends from a location other than the point corresponding to gate track T2 and/or portion B11 extends to a location other than the point corresponding to gate track T1 and portion B12 extends along a location other than gate track T1.
In the embodiment shown in fig. 2, each of the portions B1, B3, B5, B7, B9, and B11 extends in the X direction. In various embodiments, one or more of portions B1, B3, B5, B7, B9, or B11 extend in a direction other than the X direction and include features in the X direction.
In the embodiment shown in fig. 2, each of the portions B2, B4, B6, B8, B10, and B12 extends in the Y direction. In various embodiments, one or more of B2, B4, B6, B8, B10, or B12 extends in a direction other than the Y direction and includes components in the Y direction.
In the embodiment shown in fig. 2, portion B2 is aligned with portion B6 in the Y direction, portion B3 is aligned with portion B11 in the X direction, portion B5 is aligned with portion B9 in the X direction, and portion B8 is aligned with portion B12 in the Y direction. In various embodiments, portion B2 is misaligned with portion B6 in the Y-direction, portion B3 is misaligned with portion B11 in the X-direction, portion B5 is misaligned with portion B9 in the X-direction, or portion B8 is misaligned with portion B12 in the Y-direction.
Boundaries having shapes other than a rectangular shape are considered to have one or more protrusions and/or one or more recesses based on one or more offsets from the rectangular shape. By the configuration of the
In the embodiment shown in FIG. 2, the
In the embodiment shown in fig. 2, the
In the embodiment shown in fig. 2, each of the boundary protrusions 200P1, 200P2, and 200P3 and each of the boundary grooves 200R1, 200R2, and 200R3 extend in the X direction by a distance equal to the gate pitch GP. In various embodiments, one or more of the boundary protrusions 200P1, 200P2, or 200P3 or the boundary grooves 200R1, 200R2, or 200R3 extend in the X direction by a distance other than the gate pitch GP, for example, a multiple of the gate pitch GP or a fraction of the gate pitch GP.
In the embodiment shown in FIG. 2, each of the boundary protrusions 200P1, 200P2, and 200P3 and each of the boundary grooves 200R1, 200R2, and 200R3 have a shape based on a right angle formed by a continuous boundary portion. In various embodiments, one or more of the boundary protrusions 200P1, 200P2, or 200P3 or the boundary recesses 200R1, 200R2, or 200R3 have a shape based on one or more configurations other than a right angle formed by a continuous boundary portion, such as an acute or obtuse angle formed by a continuous boundary portion, a semi-circular boundary portion, or a boundary component comprising one or more arcs.
As shown in FIG. 3, the
The portion B21 extends in the positive X direction from a point corresponding to the gate rail T1 to a point corresponding to the gate rail T5. Portion B22 extends in the negative Y direction along gate rail T5 from portion B21 to portion B23. In various embodiments, portion B21 extends from a location other than the point corresponding to gate track T1 and/or portion B21 extends to a location other than the point corresponding to gate track T5, and portion B22 extends along a location other than gate track T5.
The portion B23 extends in the positive X direction from the portion B22 to a point corresponding to the gate rail T6. Portion B24 extends in the negative Y direction along gate rail T6 from portion B23 to portion B25. In various embodiments, portion B23 extends from a location other than the point corresponding to gate track T5 and/or portion B23 extends to a location other than the point corresponding to gate track T6, and portion B24 extends along a location other than gate track T6.
The portion B25 extends in the negative X direction from the portion B24 to a point corresponding to the gate rail T5. Portion B26 extends in the negative Y direction along gate rail T5 from portion B25 to portion B27. In various embodiments, portion B25 extends from a location other than the point corresponding to gate track T6 and/or portion B25 extends to a location other than the point corresponding to gate track T5, and portion B26 extends along a location other than gate track T5.
The portion B27 extends from the portion B26 in the X direction to a point corresponding to the gate rail T6. Portion B28 extends in the negative Y direction along gate rail T6 from portion B27 to portion B29. In various embodiments, portion B27 extends from a location other than the point corresponding to gate track T5 and/or portion B27 extends to a location other than the point corresponding to gate track T6, and portion B28 extends along a location other than gate track T6.
The portion B29 extends in the negative X direction from the portion B28 to a point corresponding to the gate rail T2. Portion B30 extends in the positive Y-direction along gate rail T2 from portion B29 to portion B31. In various embodiments, portion B29 extends from a location other than the point corresponding to gate track T6 and/or portion B29 extends to a location other than the point corresponding to gate track T2, and portion B30 extends along a location other than gate track T2.
The portion B31 extends in the negative X direction from the portion B30 to a point corresponding to the gate rail T1. Portion B32 extends in the positive Y-direction along gate rail T1 from portion B31 to portion B33. In various embodiments, portion B31 extends from a location other than the point corresponding to gate track T2 and/or portion B31 extends to a location other than the point corresponding to gate track T1, and portion B32 extends along a location other than gate track T1.
The portion B33 extends in the positive X direction from the portion B32 to a point corresponding to the gate rail T2. Portion B34 extends in the positive Y-direction along gate rail T2 from portion B33 to portion B35. In various embodiments, portion B33 extends from a location other than the point corresponding to gate track T1 and/or portion B33 extends to a location other than the point corresponding to gate track T2, and portion B34 extends along a location other than gate track T2.
The portion B35 extends in the negative X direction from the portion B34 to a point corresponding to the gate rail T1. Portion B36 extends in the positive Y-direction along gate rail T1 from portion B35 to portion B21. In various embodiments, portion B35 extends from a location other than the point corresponding to gate track T2 and/or portion B35 extends to a location other than the point corresponding to gate track T1, and portion B36 extends along a location other than gate track T1.
In the embodiment shown in fig. 3, each of the portions B21, B23, B25, B27, B29, B31, B33, and B35 extends in the X direction. In various embodiments, one or more of portions B21, B23, B25, B27, B29, B31, B33, or B35 extend in a direction other than the X direction and include components in the X direction.
In the embodiment shown in fig. 3, each of portions B22, B24, B26, B28, B30, B32, B34, and B36 extends in the Y-direction. In various embodiments, one or more of portions B22, B24, B26, B28, B30, B32, B34, or B36 extend in a direction other than the Y direction and include features in the Y direction.
In the embodiment shown in fig. 3, portion B22 is aligned with portion B26 in the Y direction, portion B23 is aligned with portion B35 in the X direction, portion B24 is aligned with portion B28 in the Y direction, portion B25 is aligned with portion B33 in the X direction, portion B27 is aligned with portion B31 in the X direction, portion B30 is aligned with portion B34 in the Y direction, and portion B32 is aligned with portion B36 in the Y direction. In various embodiments, portion B22 is misaligned with portion B26 in the Y-direction, portion B23 is misaligned with portion B35 in the X-direction, portion B24 is misaligned with portion B28 in the Y-direction, portion B25 is misaligned with portion B33 in the X-direction, portion B27 is misaligned with portion B31 in the X-direction, portion B30 is misaligned with portion B34 in the Y-direction, and portion B32 is misaligned with portion B36 in the Y-direction.
By the configuration of
In the embodiment shown in FIG. 3, the
In the embodiment shown in FIG. 3, the
In the embodiment shown in fig. 3, each of the boundary protrusions 300P1, 300P2, 300P3, and 300P4 and each of the boundary grooves 300R1, 300R2, 300R3, and 300R4 extend in the X direction by a distance equal to the gate pitch GP. In various embodiments, one or more of the boundary protrusions 300P1, 300P2, 300P3, or 300P4 or the boundary recesses 300R1, 300R2, 300R3, or 300R4 extend in the X direction by a distance other than the gate pitch GP, for example, a multiple of the gate pitch GP or a fraction of the gate pitch GP.
In the embodiment shown in FIG. 3, each of the boundary protrusions 300P1, 300P2, 300P3, and 300P4 and each of the boundary grooves 300R1, 300R2, 300R3, and 300R4 have a shape based on a right angle formed by the continuous boundary portions. In various embodiments, one or more of the boundary protrusions 300P1, 300P2, 300P3, or 300P4 or the boundary recesses 300R1, 300R2, 300R3, or 300R4 have a shape based on one or more configurations other than a right angle formed by a continuous boundary portion, e.g., an acute or obtuse angle formed by a continuous boundary portion, a semi-circular boundary portion, or a boundary component comprising one or more arcs.
At
A first groove is formed bordering the first portion extending in the first direction and the second and third portions extending in the second direction. In some embodiments, defining the boundary groove includes forming one or more boundary grooves in addition to the first boundary groove. In various embodiments, defining the boundary recess includes forming one or more protrusions of the boundary.
In some embodiments, defining the boundary groove includes forming an integral boundary having a closed loop. In various embodiments, defining the boundary groove includes forming an entirety of one of the
In some embodiments, defining the boundary groove includes defining at least some of the
In some embodiments, defining the boundary groove includes defining at least some of the
In some embodiments, defining the boundary groove includes defining at least some of the
In various embodiments, defining the boundary groove includes further defining the boundary by one or more additional portions extending in the first direction or the second direction or in one or more directions opposite the first direction or the second direction.
In some embodiments, further defining the boundary includes forming the overall boundary with a closed loop. In various embodiments, further defining the boundary includes forming an entirety of one of the
In some embodiments, further defining the boundary includes forming one or more boundary grooves in addition to the first boundary groove. In some embodiments, further defining the boundary includes forming one or both of the boundary grooves 200R1 or 200R2 discussed above with reference to fig. 2. In some embodiments, further defining the boundary includes forming one or more of the boundary grooves 300R1, 300R2, 300R3, or 300R4 discussed above with reference to fig. 3.
In some embodiments, further defining the boundary includes forming one or more protrusions of the boundary. In some embodiments, further defining the boundary includes forming one or more of the boundary protrusions 200P1, 200P2, or 200P3 discussed above with reference to FIG. 2. In some embodiments, further defining the boundary includes forming one or more of the boundary protrusions 300P1, 300P2, 300P3, or 300P4 discussed above with reference to fig. 3.
Each of the
Each of
In various embodiments, one or more of
In various embodiments, one or more of
In the embodiment shown in fig. 2 and 3, each of
In the embodiment shown in FIG. 2,
In some embodiments, the
In the embodiment shown in FIG. 2, each of
In some embodiments, the
In the embodiment shown in FIG. 2,
In some embodiments, the
In the embodiment shown in fig. 3,
In some embodiments, the
In the embodiment shown in fig. 3,
In some embodiments, the
In the embodiment shown in fig. 3,
In some embodiments, the
In the embodiment shown in FIG. 3,
In some embodiments,
Fig. 4 illustrates an
In many embodiments,
The gate region P extends along the Y direction, is located at the gate track TR, and crosses each active line 410[1] … 410[ M ]. The gate region P at least partially defines a gate electrode of a gate structure included in the FinFET. In various embodiments, the gate region P at least partially defines a gate electrode, wherein the gate electrode comprises a polysilicon layer, a metal layer, a work function layer, or another material suitable for controlling a channel of a FinFET.
At
Because the second and third portions of the boundary extend away from the first portion in the second direction, extending the first active region in a third direction opposite the second direction results in the first active region being positioned within the cell boundary and aligned with the first boundary recess in the first and third directions.
In some embodiments, the second direction corresponds to a negative X-direction and the third direction corresponds to a positive X-direction, each of which is discussed above with reference to fig. 2-4 and 5B 1-
In some embodiments, positioning the first active region in the cell comprises positioning the first active region within a protrusion of a cell boundary. In various embodiments, positioning the first active region in the cell includes positioning the first active region within one of the boundary protrusions 200P1, 200P2, or 200P3 discussed above with reference to fig. 2, or one or more of the boundary protrusions 300P1, 300P2, 300P3, or 300P4 discussed above with reference to fig. 3.
In some embodiments, positioning the first active region in the cell includes positioning the first active region to not overlap a boundary groove of the cell. In various embodiments, positioning the first active region in the cell includes positioning the first active region to be non-overlapping with one or more of the boundary grooves 200R1, 200R2, or 200R3 discussed above with reference to fig. 2, or one or more of the boundary grooves 300R1, 300R2, 300R3, or 300R4 discussed above with reference to fig. 3.
In various embodiments, locating the first active region includes locating one or more of the
At
In various embodiments, positioning the second active region includes positioning the second active region defining one of an N-type active region or a P-type active region to be the same as or different from the active region defined by the first active region.
In various embodiments, positioning the second active region in the cell includes positioning one or more of the
In some embodiments, positioning the second active region in the cell comprises positioning the first active region within a protrusion of a cell boundary. In various embodiments, positioning the second active region in the cell includes positioning the second active region within one of the protrusions 200P1, 200P2, or 200P3 discussed above with reference to FIG. 2 or one or more of the protrusions 300P1, 300P2, 300P3, or 300P4 discussed above with reference to FIG. 3.
In some embodiments, positioning the second active region in the cell includes positioning the second active region to not overlap a boundary groove of the cell. In various embodiments, positioning the second active region in the cell includes positioning the second active region to be non-overlapping with one or more of the boundary grooves 200R1, 200R2, or 200R3 discussed above with reference to fig. 2, or one or more of the boundary grooves 300R1, 300R2, 300R3, or 300R4 discussed above with reference to fig. 3.
In some embodiments, positioning the second active region includes modifying an IC layout.
Fig. 5A is a schematic representation of an
The
The first source/drain terminals of the transistors P1, P2, N1, and N2 are electrically connected to each other. A second source/drain terminal of transistor P1 is electrically connected to a second source/drain terminal of transistor N1, and a second source/drain terminal of transistor P2 is electrically connected to a second source/drain terminal of transistor N2.
Fig. 5B1, 5C1, 5D1, 5E1, 5F1, 5G1, and 5H1 illustrate respective IC layouts 500B1, 500C1, 500D1, 500E1, 500F1, 500G1, and 500H1, wherein each layout is based on the
Each of fig. 5B 1-
In various embodiments discussed in fig. 5B 1-
Each gate region P1-P5 at least partially defines a gate electrode of a gate structure included in the transistor structure. In various embodiments, one or more of the gate regions P1-P5 at least partially define a gate electrode of a FET, FinFET, or dummy device. In various embodiments, one or more of the gate regions P1-P5 at least partially define a gate electrode comprising a polysilicon layer, a metal layer, a work function layer, or another material suitable for controlling a channel of a transistor.
The gate regions P1-P5 are positioned at locations corresponding to a subset of the tracks T1-T6 discussed above with reference to fig. 2 and 3.
Each conductive region MD1-MD5 at least partially defines a segment of the conductive layer that is electrically connected to the underlying active region. In some embodiments, one or more of the conductive regions MD1-MD5 are referred to as metal diffusion regions. In various embodiments, one or more of conductive regions MD1-MD5 at least partially define a section of a conductive layer that includes copper or another metal suitable for forming an electrical connection to an underlying active region.
The conductive regions MD1-MD5 are positioned at locations parallel to and separated from the locations where the gate regions P1-P5 are positioned.
Each conductive region M1 and M2 at least partially defines a segment of a conductive layer underlying other additional elements of the IC device. In some embodiments, the conductive regions M1 and M2 define sections of the
Each conductive region M01-M07B at least partially defines a conductive layer segment that underlies the segment defined by conductive regions MD1-MD5, underlies the gate electrode defined by gate regions P1-P5, and underlies the segment defined by conductive regions M1 and M2. In some embodiments, the conductive regions M01-M07B define sections of a metal zero layer of the IC device. In various embodiments, one or more of the conductive regions M01-M07B at least partially define a conductive structure comprising copper or another metal suitable for forming an electrical connection to an IC device.
The cut polymer regions CP at least partially define regions that prevent formation of one or more gate electrodes defined by the gate regions P1-P5, such that the gate regions P1-P5 intersected by the cut polymer regions CP are divided into independently controllable gate electrodes.
Each via V0 (only one labeled for clarity) is a conductive region that at least partially defines a conductive layer segment between the segment defined by conductive region M01-M07B and the underlying segment defined by conductive region MD1-MD5, or between the segment defined by conductive region M01-M07B and the underlying gate electrode defined by gate region P1-P5. In various embodiments, one or more of the vias V0 at least partially define a conductive layer segment comprising copper or another metal suitable for forming an electrical connection in an IC device.
Each via V1 (only one labeled for clarity) is a conductive region that at least partially defines a conductive layer segment, wherein the conductive layer segment is interposed between the segment defined by conductive region M1 or M2 and the underlying segment defined by conductive regions M01-M07B. In various embodiments, one or more of the vias V1 define, at least in part, a conductive via comprising copper or another metal suitable for forming an electrical connection to an IC device.
Fig. 5B1 shows an IC layout 500B1 that includes a cut polymer region CP that separates the gate region P2 into gate terminals a1 and B2 and the gate region P3 into gate terminals B1 and a 2. The gate terminal a1 is electrically connected to a gate terminal a2 through conductive regions M01, MD4, and M05B, and four vias V0. The gate terminal B1 is electrically connected to the gate terminal B2 through the conductive region M03, the gate region P5, the conductive region M07, and the four vias V0.
Fig. 5B2 shows an IC layout 500B2 that includes a cut polymer region CP that separates the gate region P2 into gate terminals a1 and B2 and the gate region P3 into gate terminals B1 and a 2. The gate terminal a1 is electrically connected to a gate terminal a2 through conductive regions M01, MD4, and M07 and four vias V0. The gate terminal B1 is electrically connected to the gate terminal B2 through the conductive region M03B, the gate region P5, the conductive region M05, and the four vias V0.
Fig. 5C1 shows an IC layout 500C1 that includes a cut polymer region CP that separates the gate region P2 into gate terminals a1 and B2 and the gate region P3 into gate terminals B1 and a 2. The gate terminal a1 is electrically connected to the gate terminal a2 through the conductive region M01, the gate region P5, and the conductive region M05 and four vias V0. The gate terminal B1 is electrically connected to a gate terminal B2 through conductive regions M03, MD4, and M07 and four vias V0.
Fig. 5C2 shows an IC layout 500C2 that includes a cut polymer region CP that separates the gate region P2 into gate terminals a1 and B2 and the gate region P3 into gate terminals B1 and a 2. The gate terminal a1 is electrically connected to the gate terminal a2 through the conductive region M01, the gate region P5, and the conductive region M07 and four vias V0. The gate terminal B1 is electrically connected to a gate terminal B2 through conductive regions M03B, MD4, and M05 and four vias V0.
Fig. 5D1 shows an IC layout 500D1 that includes a cut polymer region CP that separates the gate region P2 into gate terminals a1 and B2 and the gate region P3 into gate terminals B1 and a 2. The gate terminal a1 is electrically connected to a gate terminal a2 through conductive regions M01, M1, M05, two vias V0 and two vias V1. The gate terminal B1 is electrically connected to a gate terminal B2 through conductive regions M03, M2, and M07, two vias V0, and two vias V1.
Fig. 5D2 shows an IC layout 500D2 that includes a cut polymer region CP separating the gate region P2 into gate terminals a1 and B2 and the gate region P3 into gate terminals B1 and a 2. The gate terminal a1 is electrically connected to a gate terminal a2 through conductive regions M01, M1, M07, two vias V0 and two vias V1. The gate terminal B1 is electrically connected to a gate terminal B2 through conductive regions M03, M2, M05, two vias V0 and two vias V1.
Fig. 5E1 shows an IC layout 500E1 that includes a cut polymer region CP that separates a gate region P2 into gate terminals a1 and B2, with the gate region P3 corresponding to the gate terminal a2 and the gate region P4 corresponding to the gate terminal B1. The gate terminal a1 is electrically connected to the gate terminal a2 through the conductive region M01 and the two vias V0. The gate terminal B1 is electrically connected to the gate terminal B2 through the conductive region M07 and the two vias V0.
Fig. 5E2 shows an IC layout 500E2 that includes a cut polymer region CP that separates a gate region P2 into gate terminals a1 and B2, a gate region P3 corresponding to the gate terminal B1, and a gate region P4 corresponding to the gate terminal a 2. The gate terminal a1 is electrically connected to the gate terminal a2 through the conductive region M01 and the two vias V0. The gate terminal B1 is electrically connected to the gate terminal B2 through the conductive region M05 and the two vias V0.
Fig. 5F1 and 5F2 show respective IC layouts 500F1 and 500F2, neither of which includes a cut polymer region CP. In each of the IC layout diagrams 500F1 and 500F2, the gate region P3 corresponds to the gate terminals a1 and a2 and the gate region P4 corresponds to the gate terminals B1 and B2.
Fig. 5G1 and 5G2 show respective IC layouts 500G1 and 500G2, neither of which includes a cut polymer region CP. In each of the IC layout diagrams 500G1 and 500G2, the gate region P2 corresponds to the gate terminals a1 and a2 and the gate region P3 corresponds to the gate terminals B1 and B2.
Fig. 5H1 and 5H2 show respective IC layouts 500H1 and 500H2, neither of which includes a cut polymer region CP. In each of the IC layout diagrams 500H1 and 500H2, the gate region P2 corresponds to the gate terminals a1 and a2, and the gate region P3 corresponds to the gate terminals B1 and B2.
At
Positioning the one or more gate regions includes positioning at least one gate region to intersect at least two active regions of the cell, a third active region of the cell being positioned between the at least two active regions. The active region is considered to intersect the gate region by extending through and away from the gate region in both the second direction and the third direction.
The at least one gate region being located across the at least two active regions comprises the third active region extending away from the at least one gate region in only one of the second direction or the third direction. In some embodiments, the gate region of the at least one gate region overlaps an edge of the third active region. In various embodiments, the gate region of the at least one gate region includes a polymer on an OD (active area) edge (PODE) or a continuous PODE (cpode) region that overlaps an edge of the third active area. In some embodiments, no gate region in the at least one gate region overlaps an edge of the third active region.
In various embodiments, positioning one or more gate regions includes positioning one or more of gate regions P2-P4, as shown in the non-limiting examples discussed in fig. 5B 1-
In various embodiments, the one or more gate region positioning units include therein one or more gate regions positioned in addition to at least one gate region corresponding to a third active region extending away from the at least one gate region in only one of the second direction or the third direction. In various embodiments, positioning the one or more additional gate regions includes positioning the one or more additional gate regions to intersect the third active region or have a combination of the configurations discussed above.
In some embodiments, positioning one or more gate regions includes positioning one or more dicing poly regions. Positioning the one or more cut poly regions includes dividing the one or more gate regions into two or more portions. In various embodiments, as described in the non-limiting example shown in fig. 5B 1-
In some embodiments, positioning one or more gate regions includes positioning at least one gate region at a location corresponding to a gate track. In various embodiments, the positioning of the at least one gate region at a location corresponding to a gate track includes positioning the at least one gate region at a location corresponding to at least one of the tracks T1-T6 discussed above with reference to fig. 2 and 3.
In some embodiments, positioning one or more gate regions in the cell includes positioning at least one gate region to extend into a boundary recess of the cell. In various embodiments, positioning the at least one gate region to extend into the boundary groove includes positioning the at least one gate region to extend into one or both of the boundary grooves 200R1 or 200R2, or the boundary groove 200R3, discussed above with reference to fig. 2. In various embodiments, positioning the at least one gate region to extend into the boundary groove includes positioning the at least one gate region to extend into one or both of the boundary grooves 300R1 or 300R2 or one or both of the boundary grooves 300R3 or 300R4 discussed above with reference to fig. 3.
In some embodiments, positioning the one or more gate regions in the cell comprises positioning at least one gate region within a boundary projection of the cell. In various embodiments, the positioning of the at least one gate region within the boundary protrusion includes positioning the at least one gate region within the boundary protrusion 200P1 or within one or both of the boundary protrusions 200P2 or 200P3 discussed above with reference to fig. 2. In various embodiments, the positioning of the at least one gate region within the boundary protrusion includes positioning the at least one gate region within one or both of the boundary protrusions 300P1 or 300P2 or within one or both of the boundary protrusions 300P3 or 300P4 discussed above with reference to fig. 3.
In some embodiments, modifying the IC layout is included in one or more gate region positioning units.
At
In various embodiments, positioning the one or more conductive regions includes positioning the one or more conductive regions along the first direction and/or along the second direction and the third direction. In various embodiments, positioning one or more conductive regions includes positioning one or more regions to at least partially define one or more of a metal diffusion region, a source/drain contact, a metal zero region, a
In various embodiments, as described in the non-limiting examples discussed in fig. 5B 1-
In some embodiments, positioning the one or more conductive regions comprises positioning at least one of the one or more conductive regions within a protrusion of the cell boundary. In various embodiments, the positioning of the one or more conductive regions in the cell includes positioning at least one of the one or more conductive regions in one of the protrusions 200P1, 200P2, or 200P3 discussed above with reference to FIG. 2, or one or more of the protrusions 300P1, 300P2, 300P3, or 300P4 discussed above with reference to FIG. 3.
In some embodiments, positioning the one or more conductive regions in the cell includes positioning at least one of the one or more conductive regions to not overlap a boundary groove of the cell. In various embodiments, positioning the one or more conductive regions in the cell includes positioning at least one of the one or more conductive regions to be non-overlapping with one or more of the boundary grooves 200R1, 200R2, or 200R3 discussed above with reference to fig. 2 or to be non-overlapping with one or more of the boundary grooves 300R1, 300R2, 300R3, or 300R4 discussed above with reference to fig. 3.
In some embodiments, positioning one or more conductive regions in a cell includes modifying an IC layout.
At
At
At
By performing some or all of the operations of
Fig. 6 is a flow diagram of a
In some embodiments, some or all of the operations of
Some or all of the operations of
In some embodiments, some or all of
In some embodiments, the operations of
In some embodiments, fig. 7-10 illustrate a non-limiting example of a corresponding IC layout diagram 700-1000 generated by performing one or more operations of the
Fig. 7 illustrates an
Fig. 8 illustrates an
Fig. 9 illustrates an
Fig. 10 illustrates an IC layout diagram 1000 according to some embodiments.
Each of
The gate tracks T1-T7 and the gate pitch GP correspond to the gate tracks T1-T6 with the gate pitch GP discussed above with reference to fig. 2 and 3. The gate regions P1-P7 correspond to the gate regions P1-P6 discussed above with reference to fig. 5B 1-
Each of placement and routing boundaries PR1 and PR2 is a closed boundary that defines an area within which a set of electrical connections are routed from individual components outside of the area defined by the closed boundary to individual components within the closed boundary and/or from individual components within the closed boundary to individual components outside of the area defined by the closed boundary in one or more routing operations. In some embodiments, the one or more routing operations are part of an APR method.
In various embodiments, one or more of the IC layout diagrams 700 and 1000 include one or more cells (not shown) in addition to two or more of the
In the IC layout diagram 700 shown in FIG. 7,
The
Each of the gate regions P4 and P5 is aligned along the Y direction at a position corresponding to the respective gate tracks TR4 and TR5 and is included in both of the
The gate regions P4 also intersect the active regions 220-1 and 230-1 and thus can be used in one or more transistors having one or more of the protruding members 200P 1-1. The gate region P5 also intersects the active regions 210-2 and 240-2 and can thus be used in one or more transistors having one or more of one or both of the tabs 200P2-2 or 200P 3-2.
Because each of adjacent gate regions P4 and P5 is included in both
In the IC layout diagram 800 shown in FIG. 8,
The
Each of the gate regions P4 and P5 is aligned along the Y direction at a location corresponding to the respective gate tracks TR4 and TR5 and is included in both
The gate region P4 also intersects the active regions 220-1 and 240-1 and can thus be used in one or more transistors having one or more of the one or both of the projections 300P1-1 or 300P 2-1. The gate region P5 also intersects the active regions 210-2 and 230-2 and can be used in one or more transistors having one or more of the protrusions 300P3-2 or 300P4-2 or both.
Because each of the adjacent gate regions P4 and P5 is included in both
In the
In the embodiment shown in FIG. 9,
In the
In the embodiment shown in FIG. 10,
At
In some embodiments, receiving the layouts of the first and second cells comprises receiving one or more IC layouts by performing some or all of the operations of
In various embodiments, receiving the layout of the first cell and the second cell includes receiving one or more electronic files and/or receiving the layout of the first cell and the second cell from a cell library. In some embodiments, receiving the layout of the first cell and the second cell includes receiving the layout of the first cell and the second cell over a network. In some embodiments, receiving the layout maps of the first cell and the second cell includes receiving the layout maps of the first cell and the second cell through a
In some embodiments, receiving the layout maps of the first cell and the second cell includes receiving one or
Receiving the layout of the first and second cells includes receiving the layout of the first cell including at least one boundary protrusion and the layout of the second cell including at least one boundary groove.
In some embodiments, receiving the layout of the first cell and the second cell includes receiving the layout of the first cell and the second cell having the same gate pitch. In some embodiments, receiving the layout of the first cell and the second cell includes receiving the layout of the first cell and the second cell with different gate pitches.
In some embodiments, receiving the layout of the first and second cells includes receiving the layout of the first and second cells with a plurality of gate pitches, one of which is a multiple of the other gate pitch. In some embodiments, receiving the layout maps of the first cell and the second cell includes modifying one or more gate pitches such that the layout maps of the first cell and the second cell have the same gate pitch.
In some embodiments, receiving the layout of the first cell and the second cell includes receiving at least one of the layout of the first cell or the second cell including one or more conductive regions positioned therein. In various embodiments, the one or more conductive regions include one or more conductive regions exemplified by conductive regions MD1-MD5, M1, M2, M01-M07B, via V0, or via V1 discussed above with reference to fig. 5B-
In operation 620, the first cell is adjoined to the second cell by the boundary protrusion of the first cell fitting within the boundary recess of the second cell and having the first gate region of the IC layout intersecting the boundary protrusion and intersecting the first active region of the second cell.
In some embodiments, the mating of the boundary protrusion of the first cell within the boundary groove of the second cell comprises the mating of the boundary protrusion of the first cell with the boundary groove of the second cell. In some embodiments, the mating of the boundary protrusion of the first cell within the boundary groove of the second cell comprises retaining one or more gaps between the boundary protrusion of the first cell and the boundary groove of the second cell.
In some embodiments, the mating of the boundary projection of the first unit within the boundary groove of the second unit comprises mating more than one boundary projection of the first unit within more than one boundary groove of the second unit. In some embodiments, the mating of the boundary projections of the first unit within the boundary recesses of the second unit comprises mating one or more boundary projections of the second unit within one or more boundary recesses of the first unit.
In various embodiments, the first unit abutting the second unit comprises abutting the first unit with one or more units other than the second unit by one or more of fitting the one or more boundary protrusions of the first unit within the one or more boundary grooves of the second unit and/or the additional unit, or fitting the one or more boundary protrusions of the second unit and/or the additional unit within the one or more boundary grooves of the first unit.
In various embodiments, the first cell abutting the second cell includes abutting one or more of the
In some embodiments, the first gate region intersecting the boundary protrusion and the first active region includes forming the first gate region by merging the gate region of the first cell with the gate region of the second cell. In various embodiments, the crossing of the first gate region with the boundary protrusion and the first active region includes crossing the first gate region of the first cell with the first active region of the second cell or crossing the first gate region of the second cell with the boundary protrusion of the first cell.
In various embodiments, the first gate region intersecting the boundary projections and the first active region includes one or both of intersecting the first gate region with one or more additional boundary projections of the first cell or intersecting the first gate region with one or more additional active regions of the second cell.
In various embodiments, the first gate region and the boundary projections and the first active region include one or both of intersecting the first gate region with the one or more boundary projections of the one or more additional cells or intersecting the first gate region with the one or more active regions of the one or more additional cells.
In various embodiments, the first gate region intersecting the boundary projections includes intersecting one or more of the gate regions P1-P7 discussed above with reference to fig. 7 and 8 with one or more of the boundary projections 200P1-1 to 200P3-2 or 300P-1 to 300P 4-2. In various embodiments, the first gate region intersecting the first active region includes intersecting one or more of the gate regions P1-P7 discussed above with reference to fig. 7 and 8 with one or more of the active regions 210-1 through 240-2.
In some embodiments, the first gate region intersecting the boundary protrusion and the first active region includes aligning the first cell and the second cell based on the gate track. In some embodiments, aligning the first cell and the second cell based on the gate tracks includes aligning the first cell and the second cell based on one or more of the gate tracks T1-T7 discussed above with reference to fig. 2, 3, 7, and 8.
In some embodiments, the first cell abutting the second cell includes modifying an IC layout.
At
In some embodiments, the positioning of the first cell and the second cell within the placement and routing boundary includes forming one or more legible regions within the placement and routing boundary corresponding to one or more boundary grooves of one or both of the first cell or the second cell.
In some embodiments, positioning the first cell and the second cell within the placement and routing boundary includes modifying an IC layout.
At
In some embodiments, routing the electrical connector includes routing the electrical connector as part of an APR method. In some embodiments, routing the electrical connectors is performed by an APR system, for example, a system included in an
Routing the one or more electrical connections includes positioning one or more conductive regions within an IC layout. Positioning the conductive region includes defining at least a region of the conductive layer, such as a
In various embodiments, the positioning of the one or more conductive regions within the IC layout includes positioning one or more conductive regions exemplified by conductive regions MD1-MD5, M1, M2, M01-M07B, via V0, or via V1, discussed above with reference to fig. 5B-
In some embodiments, routing the electrical connections of the first cell and the second cell includes modifying an IC layout.
At
At
At
By performing some or all of the operations of
Fig. 11 is a diagram of an
Fig. 12 is a diagram of an
The depiction of the
The
The
In the embodiment shown in fig. 11, the
According to the
In various embodiments, one or more of gate structure G1 and
In the embodiment shown in fig. 12,
According to
In various embodiments, one or more of gate structure G3 and
In various embodiments, one or both of the
In various embodiments, one or more of the
In various embodiments, gate structure G1 is divided into two portions by a cut portion G1CP, gate structure G2 is divided into two portions by a cut portion G2CP, gate structure G3 is divided into two portions by a cut portion G3CP or gate structure G4 is divided into one or more of two portions by a cut portion G4CP, according to one or more cut poly regions exemplified by a cut poly region CP discussed below with reference to fig. 5B 1-
In various embodiments, in addition to the
In various embodiments, in addition to
By performing some or all of the operations of the
Fig. 13 is a block diagram of an
In some embodiments, the
In some embodiments, the
The
In one or more embodiments, the computer-
In some embodiments, the
The
The
The
In some embodiments, some or all of the operations of the proposed processes and/or methods are implemented as stand-alone software applications for execution by a processor. In some embodiments, some or all of the operations of the proposed processes and/or methods are implemented as software applications that are part of additional software applications. In some embodiments, some or all of the operations of the proposed processes and/or methods are implemented as plug-ins to software applications. In some embodiments, part or all of the operations of the proposed process and/or method are implemented as software applications that are part of an EDA tool. In some embodiments, some or all of the operations of the proposed processes and/or methods are implemented as software applications used by the
In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer-readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage units or memory units, for example, one or more of an optical disk such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as a ROM, a RAM, a memory card, and the like.
Fig. 14 is a block diagram of an Integrated Circuit (IC)
In fig. 14, the
The design room (or design team) 1420 generates an
In some embodiments,
In some embodiments, the
In some embodiments,
It should be appreciated that the above description of
After
The
Details regarding Integrated Circuit (IC) manufacturing systems (e.g.,
In some embodiments, a method of generating a layout of Integrated Circuit (IC) cells, the layout stored on a non-volatile computer-readable medium, the method comprising: a boundary groove defining a boundary of the cell by: a first portion of the boundary extending along a first direction; a second portion of the boundary extending away from the first portion in a second direction perpendicular to the first direction, the second portion being continuous with the first portion; and a third portion of the boundary extending away from the first portion in the second direction, the third portion being continuous with the first portion. An active region is positioned in the cell by the active region extending away from the first portion in a third direction opposite the second direction. In some embodiments, the method further comprises: based on the layout, at least one of: one or more semiconductor masks; or at least one component in a semiconductor IC layer. In an embodiment, the active region is a first active region of a plurality of active regions in the cell; and the method further comprises positioning a second active region of the plurality of active regions by the second active region extending away from the first portion in the third direction. In an embodiment, positioning the first active region of the plurality of active regions comprises: the first active region comprising the plurality of active regions in a PMOS device; and positioning the second active region of the plurality of active regions comprises: the second active region of the plurality of active regions is included in an NMOS device. In an embodiment, the active region is a first active region of a plurality of active regions in the cell, each active region of the plurality of active regions extending in the third direction, and the method further comprises positioning a second active region of the plurality of active regions and a third active region of the plurality of active regions by aligning the second active region, the third active region, the second portion, and the third portion along the first direction. In an embodiment, positioning the second active region of the plurality of active regions comprises: the second active region comprising the plurality of active regions in a PMOS device; and positioning the third active region of the plurality of active regions comprises: the third active region of the plurality of active regions is included in an NMOS device. In an embodiment, the boundary recess defining the boundary of the cell comprises a boundary protrusion defining the boundary by: a fourth portion of the boundary extends in the first direction; a fifth portion of the boundary extending away from the fourth portion in the second direction, the fifth portion being continuous with the fourth portion; and a sixth portion extending away from the fourth portion in a second direction, the sixth portion being continuous with the fourth portion; wherein the active region is located between the first portion and the fourth portion. In an embodiment, the active region is a first active region of a plurality of active regions in the cell, each active region of the plurality of active regions extending in the third direction, the boundary groove defining a boundary of the cell further comprising: a seventh portion of the boundary extending in the second direction, the seventh portion being discontinuous from the fourth portion and parallel to the fifth portion and the sixth portion, and the method further comprising: positioning the second active region of the plurality of active regions by aligning the first active region of the plurality of active regions, a second active region of the plurality of active regions, the fifth portion, the sixth portion, and the seventh portion in the first direction. In an embodiment, one of positioning the first active region of the plurality of active regions or positioning the second active region of the plurality of active regions comprises: including one of the first active region of the plurality of active regions or the second active region of the plurality of active regions in a PMOS device, and positioning the other of the first active region of the plurality of active regions or the second active region of the plurality of active regions comprises: the NMOS device includes the other of the first active region of the plurality of active regions or the second active region of the plurality of active regions.
In an embodiment, the method further comprises: based on the integrated circuit layout, at least one of: one or more semiconductor masks; or at least one component in a semiconductor integrated circuit layer.
In an embodiment, the active region is a first active region of a plurality of active regions in the cell; and the method further comprises positioning a second active region of the plurality of active regions by the second active region extending away from the first portion in the third direction.
In an embodiment, positioning the first active region of the plurality of active regions comprises: the first active region comprising the plurality of active regions in a PMOS device; and positioning the second active region of the plurality of active regions comprises: the second active region of the plurality of active regions is included in an NMOS device.
In an embodiment, the active region is a first active region of a plurality of active regions in the cell, each active region of the plurality of active regions extending in the third direction, and the method further comprises positioning a second active region of the plurality of active regions and a third active region of the plurality of active regions by aligning the second active region, the third active region, the second portion, and the third portion along the first direction.
In an embodiment, positioning the second active region of the plurality of active regions comprises: the second active region comprising the plurality of active regions in a PMOS device; and positioning the third active region of the plurality of active regions comprises: the third active region of the plurality of active regions is included in an NMOS device.
In an embodiment, the boundary recess defining the boundary of the cell comprises a boundary protrusion defining the boundary by: a fourth portion of the boundary extends in the first direction; a fifth portion of the boundary extending away from the fourth portion in the second direction, the fifth portion being continuous with the fourth portion; and a sixth portion extending away from the fourth portion in a second direction, the sixth portion being continuous with the fourth portion; wherein the active region is located between the first portion and the fourth portion.
In an embodiment, the active region is a first active region of a plurality of active regions in the cell, each active region of the plurality of active regions extending in the third direction, the boundary groove defining a boundary of the cell further comprising: a seventh portion of the boundary extending in the second direction, the seventh portion being discontinuous from the fourth portion and parallel to the fifth portion and the sixth portion, and the method further comprising: positioning the second active region of the plurality of active regions by aligning the first active region of the plurality of active regions, a second active region of the plurality of active regions, the fifth portion, the sixth portion, and the seventh portion in the first direction.
In an embodiment, one of positioning the first active region of the plurality of active regions or positioning the second active region of the plurality of active regions comprises: including one of the first active region of the plurality of active regions or the second active region of the plurality of active regions in a PMOS device, and positioning the other of the first active region of the plurality of active regions or the second active region of the plurality of active regions comprises: the NMOS device includes the other of the first active region of the plurality of active regions or the second active region of the plurality of active regions.
In an embodiment, a method of generating a layout of an Integrated Circuit (IC), the layout stored on a non-volatile computer-readable medium, the method comprising: abutting a first cell to a second cell in the IC layout by: the boundary protrusion of the first cell fits within the boundary recess of the second cell, and the first gate region of the IC layout is made to intersect the boundary protrusion and intersect the first active region of the second cell. In an embodiment, the method further comprises: performing one or more lithographic exposures based on the IC layout. In an embodiment, the first gate region crossing the boundary protrusion and the first active region includes aligning the first cell and the second cell based on a gate track. In an embodiment, the first gate region of the IC layout intersects the boundary protrusion and intersects the first active region includes intersecting the first gate region with a second active region of the second cell. In an embodiment, the boundary protrusion of the first cell is a first boundary protrusion of a plurality of boundary protrusions of the first cell, and the first gate area of the IC layout intersecting the boundary protrusion and the first active area comprises intersecting the first gate area with a second boundary protrusion of the plurality of boundary protrusions. In an embodiment, the method further comprises positioning the first cell and the second cell within a placement and routing boundary.
In an embodiment, the method further comprises: performing one or more lithographic exposures based on the integrated circuit layout.
In an embodiment, the first gate region crossing the boundary protrusion and the first active region includes aligning the first cell and the second cell based on a gate track.
In an embodiment, the first gate region of the integrated circuit layout intersects the boundary protrusion and intersects the first active region includes intersecting the first gate region with a second active region of the second cell.
In an embodiment, the boundary protrusion of the first cell is a first boundary protrusion of a plurality of boundary protrusions of the first cell, and the first gate region of the integrated circuit layout intersecting the boundary protrusion and the first active region comprises intersecting the first gate region with a second boundary protrusion of the plurality of boundary protrusions.
In an embodiment, the method further comprises positioning the first cell and the second cell within a placement and routing boundary.
In an embodiment, an Integrated Circuit (IC) device includes: a plurality of active regions, each of the plurality of active regions extending in a first direction; and a first gate structure extending in a second direction perpendicular to the first direction, the first gate structure being located over each of the plurality of active regions; wherein a first active region of the plurality of active regions is located between the plurality of active region second active regions and a third active region of the plurality of active regions, the first gate structure is located over an edge of the first active region of the plurality of active regions, and each of the second active region of the plurality of active regions and the third active region of the plurality of active regions extends through the first gate structure. In an embodiment, the IC device further comprises: a second gate structure extending in the second direction, the second gate structure being located over each of the plurality of active regions, wherein the second gate structure is located over an edge of the second one of the plurality of active regions and over an edge of the third one of the plurality of active regions, and the first one of the plurality of active regions extends through the second gate structure. In an embodiment, a fourth active region of the plurality of active regions is located between the second active region of the plurality of active regions and the third active region of the plurality of active regions, and the first gate structure is located over an edge of the fourth active region of the plurality of active regions. In an embodiment, the third active region of the plurality of active regions is located between the first active region of the plurality of active regions and a fourth active region of the plurality of active regions, and the first gate structure is located over an edge of the fourth active region of the plurality of active regions. In an embodiment, a first portion of the first gate structure is located over the second active region of the plurality of active regions; a second portion of the first gate structure is over the third active region of the plurality of active regions; and the first portion of the first gate structure and the second portion of the first gate structure are independently controlled.
In an embodiment, the integrated circuit device further comprises: a second gate structure extending in the second direction, the second gate structure being located over each of the plurality of active regions, wherein the second gate structure is located over an edge of the second one of the plurality of active regions and over an edge of the third one of the plurality of active regions, and the first one of the plurality of active regions extends through the second gate structure.
In an embodiment, a fourth active region of the plurality of active regions is located between the second active region of the plurality of active regions and the third active region of the plurality of active regions, and the first gate structure is located over an edge of the fourth active region of the plurality of active regions.
In an embodiment, the third active region of the plurality of active regions is located between the first active region of the plurality of active regions and a fourth active region of the plurality of active regions, and the first gate structure is located over an edge of the fourth active region of the plurality of active regions.
In an embodiment, a first portion of the first gate structure is located over the second active region of the plurality of active regions; a second portion of the first gate structure is over the third active region of the plurality of active regions; and the first portion of the first gate structure and the second portion of the first gate structure are independently controlled.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
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