阅读说明：本技术 相移器 (Phase shifter ) 是由 林纪贤 陈和祥 廖显原 叶子祯 吕盈达 于 2019-06-28 设计创作，主要内容包括：一种相移器,包含主动区、第一栅极组、第二栅极组和接触物组。主动区在第一方向上延伸且定位在第一层级。第一栅极组在第二方向上延伸,其与主动区重叠且定位在第二层级。接触物组在第二方向上延伸,其在主动区的上方并定位在第三层级,且设置在至少第二栅极组之间。(A phase shifter includes an active region, a first gate group, a second gate group, and a contact group. The active region extends in a first direction and is positioned at a first level. The first gate group extends in a second direction, overlaps the active region, and is positioned at a second level. The contact set extends in a second direction, is above the active region and positioned at a third level, and is disposed between at least the second gate set.)

1. A phase shifter, comprising:

an active region extending in a first direction and located at a first level;

a first gate group extending in a second direction different from the first direction, the first gate group overlapping the active region and located at a second level different from the first level, and each gate in the first gate group being separated from another gate in the first direction;

a second set of gates extending in the second direction, the second set of gates overlapping the active region and located at the second level and disposed along opposite edges of the active region and configured to receive a first voltage, the second set of gates being part of a first transistor configured to adjust a first capacitance value of the phase shifter in response to the first voltage; and

and a contact group extending in the second direction, the contact group being located above the active region and at a third level different from the first level, and being disposed between at least the second gate group.

Technical Field

The present disclosure relates to a phase shifter.

Background

Phase shifters are classified based on some operating characteristics. Recent trends in the scaling of Integrated Circuits (ICs) may result in smaller devices, and such devices may consume lower power and may provide more functionality at higher speeds than previously possible. As speed or frequency increases, the scaling of phase shift circuits also leads to more stringent design and manufacturing specifications.

Disclosure of Invention

According to one aspect of the present disclosure, a phase shifter includes an active region, a first gate set, a second gate set, and a contact set. The active region extends in a first direction and is located at a first level. The first gate group extends in a second direction different from the first direction, overlaps the active region and is located at a second level different from the first level, and each gate in the first gate group is separated from another gate in the first direction. The second gate group extends in a second direction, overlaps the active region, is at a second level, is disposed along an opposite edge of the active region, and is configured to receive a first voltage. The second set of gates is part of a first transistor configured to adjust a first capacitance value of the phase shifter in response to the first voltage. The contact group extends in the second direction, is positioned above the active region and positioned at a third level different from the first level, and is arranged between at least the second gate group.

Drawings

For a more complete understanding of the embodiments and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a phase shift circuit according to some embodiments;

FIG. 2A is a circuit diagram of a phase shift circuit according to some embodiments;

FIG. 2B is a circuit diagram of a phase shift circuit according to some embodiments;

FIG. 3 is a schematic diagram of a layout design in accordance with some embodiments;

FIGS. 4A and 4B are schematic diagrams of phase shift circuits according to some embodiments;

FIG. 5A is a circuit diagram of a phase shift circuit according to some embodiments;

FIG. 5B is a circuit diagram of a phase shift circuit according to some embodiments;

FIG. 6A is a circuit diagram of a phase shift circuit according to some embodiments;

FIG. 6B is a circuit diagram of a phase shift circuit according to some embodiments;

FIG. 7 is a top view of a phase shift circuit according to some embodiments;

FIG. 8A is a circuit diagram of a phase shift circuit according to some embodiments;

FIG. 8B is a circuit diagram of a phase shift circuit according to some embodiments;

FIG. 9 is a schematic top view of a phase shift circuit according to some embodiments;

10A-10D illustrate corresponding schematic diagrams of phase differences that may be used in the phase shift circuits of FIGS. 2A-2B according to some embodiments;

FIG. 11 is a flow diagram of a method of forming or fabricating a phase shift circuit according to some embodiments;

FIG. 12 is a flow diagram of a method of generating a layout design for a phase shift circuit according to some embodiments;

FIG. 13 is a schematic diagram of a system for designing and manufacturing an integrated circuit layout design in accordance with some embodiments; and

FIG. 14 is a block diagram of an integrated circuit manufacturing system and an integrated circuit manufacturing flow associated with the integrated circuit manufacturing system in accordance with some embodiments.

[ notation ] to show

100. 200A, 200B, 400, 500A, 500B, 600A, 600B, 700, 800A, 800B, 900 phase shift circuit

201. 401 well region

202a, 202b, 204a, 204b, 602a, 602b, 604a, 604b, 802a, 802b, 804a, 804b transistor

300 layout design

302 active region layout pattern group

302a active region layout pattern

304. 306 grid layout pattern group

304 a-304 d, 306a, 306b gate layout pattern

308 metal group over diffusion layout pattern

308 a-308 e metal over diffusion layout pattern

320a, 320b, 420a, 420b edges

402 active region

402 a-402 e implant region

404. 406 grid group

404 a-404 d, 406a, 406b gates

408. 708, 908 contact set

408 a-408 e, 708 a-708 e, 908b, 908d

430. 432 insulating block group

430 a-430 d, 432a, 432b insulating regions

Curves 1002a to 1002d, 1010a to 1010d, 1020a to 1020d, and 1030a to 1030c

1100. 1200 method

1102. 1104, 1202, 1204, 1206, 1208 operations

1300 system

1302 processor

1304 memory

1306 instruction

1308 bus

1310 input/output interface

1312 network interface

1314 network

1316 layout design

1318 user interface

1320 manufacturing unit

1400 integrated circuit manufacturing system

1420 design Chamber

1422 Integrated Circuit design

1430 light shield chamber

1432 data preparation

1434 photomask production

1440 ic foundry

1442 wafer

1460 Integrated Circuit device

C1-C4 capacitor

D drain region

GND ground terminal

IN input terminal

OUT output terminal

R1, R2 resistance

S source region

VG, VPODE voltage

Vin input signal

Vout output signal

X, Y, Z direction

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc., are described below to simplify the present disclosure. Of course, these are merely examples and are not limiting. Other elements, materials, values, steps, configurations, etc. are also contemplated. For example, in the following description, forming a first feature "on" or "over" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. Such reuse is for purposes of brevity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below" …, "below," lower, "above," upper, "and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures for ease of illustration. Such spatially relative terms are intended to encompass additional orientations of the device in different uses or operations in addition to the orientation depicted in the figures. In addition, the device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative terms used herein may be interpreted in a similar manner.

According to some embodiments, a phase shift circuit includes an active region, a first gate set, a second gate set, and a contact set. The active region extends in a first direction and is positioned at a first level. The first gate group extends in a second direction, overlaps the active region, and is positioned at a second level. The contact set extends in a second direction, is above the active region and positioned at a third level, and is disposed between at least the second gate set.

The second gate group extends in a second direction, overlaps the active region and is positioned at a second level. The second gate set is disposed along an opposite edge of the active region and configured to receive a first voltage. The second gate set is part of a first transistor configured to adjust a first capacitance value of the phase shifter in response to the first voltage. In some embodiments, the first capacitance value of the phase shift circuit is adjusted by adjusting the first voltage.

The first gate set is configured to receive a second voltage. The first gate group is a portion of the second transistor configured to adjust a second capacitance value or a resistance value of the phase shifter in response to the second voltage. In some embodiments, the second capacitance or resistance value of the phase shift circuit is adjusted by adjusting the second voltage.

In some embodiments, a second set of gates are positioned along opposite ends of the active region to cover and protect the ends of the active region or the cell region of the phase shift circuit during fabrication or processing, thereby providing additional reliability during processing. In some embodiments, by configuring the second set of gates to be functional (functional) or operational (operational), as part of the first transistor, the phase shift circuit is configured to have multiple phase adjustment mechanisms compared to other embodiments having a single adjustment mechanism. In some embodiments, the phase shift circuit has multiple adjustment mechanisms or control schemes, so that the precision (resolution) and the adjustable range are better than those of other embodiments.

Phase shift circuit

Fig. 1 is a circuit diagram of a phase shift circuit 100 according to some embodiments.

The phase shift circuit 100 includes a resistor R1 and a capacitor C1 coupled in series. The phase shift circuit 100 has an input terminal IN configured to receive an input signal Vin and an output terminal OUT configured to output an output signal Vout. The phase shift circuit 100 is a low pass filter. The phase shift circuit 100 is a 1-order RC phase shifter. Other orders are within the intended scope of the disclosure.

The phase shift circuit 100 is configured to shift the phase of the output signal Vout with respect to the input signal Vin by a phase shift or phase difference Δ θ 1 (expressed by equation 1 below). In some embodiments, the input signal Vin and the output signal Vout are Radio Frequency (RF) signals.

A first terminal of the resistor R1 is coupled to the input terminal IN. A second terminal of the resistor R1 is coupled to the output terminal OUT and a first terminal of the capacitor C1. The second terminal of the capacitor C1 is coupled to the reference voltage supply terminal VSS.

The output signal Vout of the phase shift circuit 100 has a phase shift or difference Δ θ 1 relative to the input signal Vin, which is represented by equation 1:

Δθ1＝-tan^-1(2πFRC) (1)

where R is the resistance of the resistor R1, C is the capacitance of the capacitor C1, and F is the cut-off frequency of the phase shift circuit 100.

Fig. 2A is a circuit diagram of a phase shift circuit 200A according to some embodiments.

The phase shift circuit 200A is an embodiment of the phase shift circuit 100 of fig. 1. Phase shift circuit 200A includes transistors 202a, 204 a.

The transistor 202a is an embodiment of the resistor R1 in fig. 1, and similar detailed descriptions are omitted. The transistor 204a is an embodiment of the capacitor C1 in fig. 1, and similar detailed descriptions are omitted.

The transistors 202a, 204a are NMOS transistors. In some embodiments, at least one of the transistors 202a or 204a is a P-type metal oxide semiconductor (PMOS) transistor.

The gate terminal of transistor 202a is configured to receive signal VG. The drain terminal of the transistor 202a is coupled to the input terminal IN. The source terminal of the transistor 202a is coupled to the output terminal OUT and the source terminal of the transistor 204 a. In some embodiments, transistor 202a is configured as resistor R1 of fig. 1.

The gate terminal of the transistor 204a is configured to receive the signal VPODE. In some embodiments, the transistor 204a is configured as the capacitor C1 of fig. 1. The transistor 204a does not include a drain terminal. In some embodiments, the transistor 204a includes a drain terminal (not shown), but the drain terminal is electrically floating.

Other types or numbers of transistors in phase shift circuit 200A are within the intended scope of the present disclosure.

Fig. 2B is a circuit diagram of a phase shift circuit 200B according to some embodiments.

The phase shift circuit 200B is a variation of the phase shift circuit 200A of fig. 2A, and similar detailed description is therefore omitted. In contrast to phase shift circuit 200A, phase shift circuit 200B includes PMOS transistors (e.g., transistors 202B, 204B).

The phase shift circuit 200B is an embodiment of the phase shift circuit 100 of fig. 1. Phase shift circuit 200B includes transistors 202B, 204B.

The transistor 202b is an embodiment of the resistor R1 in fig. 1, and a detailed description thereof is omitted. The transistor 204b is an embodiment of the capacitor C1 in fig. 1, and similar detailed descriptions are omitted.

The transistors 202b, 204b are PMOS transistors. In some embodiments, at least one of the transistors 202b or 204b is an nmos transistor.

The gate terminal of transistor 202b is configured to receive signal VG. The drain terminal of the transistor 202b is coupled to the input terminal IN. The source terminal of the transistor 202b is coupled to the output terminal OUT and the source terminal of the transistor 204 b. In some embodiments, transistor 202b is configured as resistor R1 of fig. 1.

The gate terminal of the transistor 204b is configured to receive the signal VPODE. In some embodiments, the transistor 204b is configured as the capacitor C1 of fig. 1. The transistor 204b does not include a drain terminal. In some embodiments, the transistor 204b includes a drain terminal (not shown), but the drain terminal is electrically floating. In some embodiments, the transistor 204a or 204b is implemented as a polysilicon on oxide diffusion edge (PODE).

In some embodiments, at least one of the transistors 202a, 202b, 204a, or 204b is a Fin Field Effect Transistor (FinFET). Other types or numbers of transistors in phase shift circuit 200B are within the intended scope of the present disclosure.

Layout design of phase shift circuit

FIG. 3 is a schematic diagram of a layout design 300 according to some embodiments. Layout design 300 is a layout diagram of phase shift circuit 200A of fig. 2A or phase shift circuit 200B of fig. 2B.

Layout design 300 may be used to fabricate one or more of phase shift circuits 200A, 200B, phase shift circuit 400 of fig. 4A, 4B, phase shift circuits 500A, 500B corresponding to fig. 5A, 5B, phase shift circuits 600A, 600B corresponding to fig. 6A, 6B, phase shift circuit 700 of fig. 7, phase shift circuits 800A, 800B corresponding to fig. 8A, 8B, or phase shift circuit 900 of fig. 9. In some embodiments, the layout design 300 of fig. 3 includes additional layers or layouts (e.g., fin layout patterns, over metal layout patterns, via layout patterns, or the like), which are not shown for simplicity.

The layout design 300 includes an active region layout pattern group 302 extending in a first direction X. The active area layout pattern group 302 includes active area layout patterns 302 a. The set of active area layout patterns 302 may be used to fabricate a corresponding set of active areas 402 (fig. 4A, 4B, 7, and 9) of the integrated circuits 400, 700, 900. In some embodiments, the active area layout pattern group 302 is positioned on a first layout level. In some embodiments, the set of active area layout patterns 302 are referred to as Oxide Diffusion (OD) layout patterns. In some embodiments, the first layout level is an active level or an oxide diffusion level of the layout design 300. The arrangement or number of other active area layout patterns in the active area layout pattern group 302 is within the scope of the present disclosure.

The layout design 300 further includes a set of gate layout patterns 304 extending in a second direction Y different from the first direction X. The set of gate layout patterns 304 may be used to fabricate a corresponding set of gates 404 of the integrated circuits 400, 700, 900 (fig. 4A, 4B, 7, and 9). The gate layout pattern group 304 includes one or more of the gate layout patterns 304a, 304b, 304c, or 304 d. The gate layout pattern 304A, 304B, 304c, or 304d of the set of gate layout patterns 304 may be used to fabricate a corresponding gate 404A, 404B, 404c, or 404d in the set of gates 404 (fig. 4A, 4B, 7, and 9) of the integrated circuit 400, 700, 900. Each gate layout pattern of the gate layout pattern group 304 is separated from each gate layout pattern of the gate layout pattern group 304 by a first pitch (not labeled) in the first direction X.

The gate layout pattern set 304 overlaps the active region layout pattern set 302 and is positioned at a second layout level different from the first layout level. In some embodiments, the second layout level is a polysilicon level.

Layout design 300 also includes a set of gate layout patterns 306 extending in second direction Y. The set of gate layout patterns 306 may be used to fabricate a corresponding set of gates 406 of the integrated circuits 400, 700, 900 (fig. 4A, 4B, 7, 9). The gate layout pattern group 306 includes one or more of the gate layout patterns 306a or 306 b. The gate layout patterns 306a, 306B of the gate layout pattern group 306 may be used to fabricate corresponding gates 406a, 406B of the gate group 406 of the integrated circuits 400, 700, 900 (fig. 4A, 4B, 7, 9).

The gate layout patterns 306a of the gate layout pattern group 306 are separated from the gate layout patterns 306b of the gate layout pattern group 306 in the first direction X. In some embodiments, the gate layout patterns 306a, 306b of the gate layout pattern group 306 are separated from the corresponding gate layout patterns 304a, 304d of the gate layout pattern group 304 by a first pitch (not labeled) in the first direction X.

The gate layout pattern group 306 overlaps the active region layout pattern group 302 and is positioned at the second layout level.

The gate layout pattern group 306 is disposed along the opposite edges of the active layout pattern 302a or covers the opposite edges of the active layout pattern 302 a. The gate layout patterns 306a of the gate layout pattern group 306 are disposed along the edge 320a of the active area layout pattern 302a or cover the edge 320a of the active area layout pattern 302 a. The gate layout patterns 306b of the gate layout pattern group 306 are disposed along the edge 320b of the active area layout pattern 302a or cover the edge 320b of the active area layout pattern 302 a. In some embodiments, edges 320a, 320b correspond to edges of standard cells (standard cells) of layout design 300. The active region layout pattern group 302 is below the gate layout pattern groups 304, 306. In some embodiments, the gate layout pattern group 306 is a poly-silicon cross-oxide diffusion edge layout pattern. In some embodiments, the gate layout pattern 306 is referred to as a dummy gate layout pattern, which may be used to fabricate the gates 406a, 406 b. However, the gates 406a, 406B are functional gates (described in fig. 4A, 4B) rather than dummy gates.

The gate layout pattern 304b of the gate layout pattern group 304 is between the gate layout patterns 304a, 304c of the gate layout pattern group 304. The gate layout pattern 304c of the gate layout pattern group 304 is between the gate layout patterns 304b, 304d of the gate layout pattern group 304. The gate layout pattern 304a of the gate layout pattern group 304 is between the gate layout pattern 306a of the gate layout pattern group 306 and the gate layout pattern 304b of the gate layout pattern group 304. The gate layout patterns 304d of the gate layout pattern group 304 are located between the gate layout patterns 306b of the gate layout pattern group 306 and the gate layout patterns 304d of the gate layout pattern group 304. The arrangement or number of other gate layout patterns in the gate layout pattern group 304 or 306 is within the scope of the present disclosure.

The layout design 300 also includes a metal group 308 over the diffusion layout pattern, which extends in the second direction Y. The metal group 308 above the diffusion layout pattern may be used to fabricate a corresponding contact group 408 (fig. 4A, 4B, 7, 9) of the integrated circuit 400, 700, 900.

The metal group 308 over the diffusion layout pattern includes one or more of the metals 308a, 308b, 308c, 308d, or 308e over the diffusion layout pattern. The metals 308a, 308B, 308c, 308d, 308e in the metal set 308 above the diffusion layout pattern may be used to fabricate the corresponding contacts 408a, 408B, 408c, 408d, 408e of the contact set 408 (fig. 4A, 4B, 7, 9) of the integrated circuit 400, 700, 900.

In some embodiments, the metal 308A, 308c, or 308e in the metal group 308 above the diffusion layout pattern at least above the diffusion layout pattern is a source region layout pattern that may be used to fabricate the source terminal of the transistor 202A, 202B, 602A, 602B, 802A, 802B (fig. 2A, 2B, 6A, 6B, 8A, 8B) or 204a, 204B, 604a, 604B, 804a, 804B (fig. 2A, 2B, 6A, 6B, 8A, 8B).

In some embodiments, at least the metal 308B or 308d above the diffusion layout pattern in the metal group 308 above the diffusion layout pattern is a drain region layout pattern that can be used to fabricate the drain terminal of the transistor 202A, 202B, 602A, 602B, 802A, 802B (fig. 2A, 2B, 6A, 6B, 8A, 8B) or 204a, 204B, 604a, 604B, 804a, 804B (fig. 2A, 2B, 6A, 6B, 8A, 8B).

The metal group 308 above the diffusion layout pattern overlaps the active region layout pattern group 302 and is positioned at a third layout level different from the first layout level and the second layout level. In some embodiments, the second layout level is a metal over diffusion (MD) level.

The metal group 308 above the diffusion layout pattern is located between the gate layout pattern groups 306. Each layout pattern of the metal group 308 above the diffusion layout pattern is separated from an adjacent layout pattern of the metal group 308 above the diffusion layout pattern in the first direction X.

The metal 308a above the diffusion layout pattern in the metal group 308 above the diffusion layout pattern is located between the gate layout pattern 306a of the gate layout pattern group 306 and the gate layout pattern 304a of the gate layout pattern group 304. The metal 308b above the diffusion layout pattern in the metal group 308 above the diffusion layout pattern is located between the gate layout pattern 304b of the gate layout pattern group 304 and the gate layout pattern 304a of the gate layout pattern group 304. The metal 308c above the diffusion layout pattern in the metal group 308 above the diffusion layout pattern is located between the gate layout pattern 304b of the gate layout pattern group 304 and the gate layout pattern 304c of the gate layout pattern group 304. The metal 308d above the diffusion layout pattern in the metal group 308 above the diffusion layout pattern is located between the gate layout pattern 304c of the gate layout pattern group 304 and the gate layout pattern 304d of the gate layout pattern group 304. In the metal group 308 above the diffusion layout pattern, the metal 308e above the diffusion layout pattern is located in the gate layout pattern 306b of the gate layout pattern group 306 and the gate layout pattern 304d of the gate layout pattern group 304. Other arrangements or numbers of metal groups 308 above the diffusion layout pattern are within the scope of the present disclosure.

Top view of phase shift circuit

Fig. 4A and 4B are schematic diagrams of a phase shift circuit 400 according to some embodiments.

Fig. 4A is a top view of a phase shift circuit 400 according to some embodiments. Fig. 4B is a cross-sectional view, such as a-a', of phase shift circuit 400 according to some embodiments.

The phase shift circuit 400 is an embodiment of the phase shift circuit 200A or 200B of fig. 2A or 2B, which is shown in the above view.

In one or more of fig. 1, 2A, 2B, 4A, 4B, 5A, 5B, 6A, 6B, 7, 8A, 8B and 9 (shown below), the same or similar elements are given the same reference numerals and a similar detailed description is thus omitted.

The phase shift circuits 400, 700 (fig. 7), 900 (fig. 9) are fabricated by the layout design 300. The structural relationships and configurations of phase shift circuits 400, 700, 900, including alignment, length, width, are similar to those of layout design 300 of fig. 3 and will not be described in each of fig. 4A, 4B, 7, 9 for brevity.

The phase shift circuit 400 includes an input terminal IN configured to receive an input signal Vin and an output terminal OUT configured to output an output signal Vout. The output signal Vout of the phase shift circuit 400 has a phase difference Δ θ 1 with respect to the input signal Vin, which is represented by equation 1.

The phase shift circuit 400 also includes one or more implants 402a, 402b, 402c, 402d, or 402e within the well 401. The well 401 comprises a first doping type. The first doping type is a p-type doping impurity. In some embodiments, the first doping type is an n-type doping impurity. Well 401 is in a substrate (not shown). The well 401 extends in a second direction Y. Other arrangements or quantities of wells 401 are within the intended scope of the present disclosure.

Each of the implant regions 402a, 402b, 402c, 402d, 402e extends in the second direction Y and is separated from each other in the first direction X. Each of the implanted regions 402a, 402b, 402c, 402d, 402e has a second doping type different from the first doping type. The second doping type is an n-type doping impurity. In some embodiments, the second doping type is a p-type doping impurity. In some embodiments, the implanted regions 402a, 402c, 402e are source regions of the transistors 202a, 204a or 202b, 204 b. In some embodiments, the implanted regions 402b, 402d are drain regions of the transistors 202a, 204a or the transistors 202b, 204 b. Other configurations or amounts of the implant regions 402a, 402b, 402c, 402d, 402e are within the intended scope of the present disclosure.

In some embodiments, the implanted regions 402a, 402b, 402c, 402d, 402e and the upper portion of the well region 401 are referred to as an active region group 402 (hereinafter referred to as "active region 402") of the phase shift circuit 400. The active region 402 extends in the first direction X and is positioned at a first level of the phase shift circuit 400. In some embodiments, the first level is an active level or an oxide diffusion level. Other configurations or amounts of active regions 402 are within the intended scope of the present disclosure.

The phase shift circuit 400 also includes a set of gates 404 extending in the second direction Y that overlap the active region 402 and are positioned at a second level different from the first level. In some embodiments, the second level is a polysilicon level. Gate set 404 includes one or more of gates 404a, 404b, 404c, or 404 d. In some embodiments, each gate of the gate set 404 is separated from another gate of the gate set 404 by a first pitch (not labeled) in the first direction X. In some embodiments, one or more gates of the gate set 404 are metal gate structures.

In some embodiments, the gate set 404 corresponds to the gates of the transistors 202A of fig. 2A or the gates of the transistors 202B of fig. 2B. In some embodiments, the gate set 404 is configured to receive a voltage VG. In some embodiments, the transistor 202a or 202b is configured to adjust a resistance value of a resistor R1 (shown in fig. 1) of the phase shift circuit 400 in response to the voltage VG. In some embodiments, the gates 404a, 404b, 404c, 404d of the gate set 404 are coupled to each other and configured to receive the voltage VG and are part of the transistors 202a or 202 b. Other configurations or amounts of gate stack 404 are within the intended scope of the present disclosure.

The phase shift circuit 400 also includes a set of gates 406 extending in the second direction Y, overlapping the set of active regions 402 and positioned at a second level.

Gate set 406 includes one or more of gates 406a or 406 b. In some embodiments, each gate of the gate set 406 is separated from another gate of the gate set 406 in the first direction X. In some embodiments, one or more gates in the gate set 406 are polysilicon gate structures. The set of gates 406 is disposed along opposite edges 420a, 420b of the cell defined by the active region 402 and is therefore referred to as a polysilicon on oxide diffusion edge (PODE).

In some embodiments, the gates 404a, 404b, 404c, 404d of the gate set 404 are referred to as the functional or operational gate structure of the phase shift circuit 400. In some embodiments, phase shift circuit 400 defines a cell region produced by a standard cell layout (e.g., layout design 300), and the cell region is adjacent to an additional cell (similar to the cell region of phase shift circuit 400).

In some embodiments, the gates 406a, 406b of the gate set 406 are configured to cover and protect the ends of the active region 402 or the cell region of the phase shift circuit 400 during manufacturing or processing, thereby providing additional reliability during processing. In some embodiments, gates similar to gates 406a, 406b are referred to as "dummy gates" and are not functional or operational due to being turned off due to being susceptible to process variations. In such embodiments, the dummy gates are not electrically coupled to the gates of the transistors and are not electrically functional. However, in some embodiments, the gates 406a, 406B of the gate set 406 are configured to be functional or operational, such as a portion of the transistor 204a of fig. 2A or the gate of the transistor 204B of fig. 2B. For example, in some embodiments, the gate set 406 corresponds to the gate of the transistor 204a of fig. 2A or the gate of the transistor 204B of fig. 2B. In some embodiments, the gate set 406 is configured to receive the voltage VPODE. In some embodiments, the transistors 204a or 204b are configured to adjust the capacitance value of the capacitor C1 (shown in fig. 1) of the phase shift circuit 400 in response to the voltage VPODE. In some embodiments, the gates 406a, 406b of the gate set 406 are coupled to each other and configured to receive the voltage VPODE, and are part of the transistors 204a or 204 b.

In some embodiments, the capacitance of the capacitor C1 of the phase shift circuit 400 is adjusted by adjusting the voltage VPODE received by the gates 406a, 406b, thereby causing an adjustment or change in the phase PHIOUT of the output signal OUT as compared to the phase PHIIN of the input signal Vin. In some embodiments, the phase PHIOUT of the output signal varies by a first phase difference Δ PHI1 relative to the phase PHIIN of the input signal Vin. In some embodiments, the first phase difference Δ PHI1 is about 0 degrees to 360 degrees.

Similarly, in some embodiments, the resistance of the resistor R1 of the phase shift circuit 400 is adjusted by adjusting the voltage VG received by the gates 408a, 408b, 408c, 408d, thereby causing the phase PHIOUT of the output signal OUT to be adjusted or changed compared to the phase PHIIN of the input signal Vin. IN some embodiments, the phase PHIOUT of the output signal varies by a second phase difference Δ PHI2 relative to the phase PHIIN of the input signal IN. In some embodiments, the second phase difference Δ PHI2 is approximately 0 degrees to 360 degrees.

In some embodiments, the first phase difference Δ PHI1 is referred to as a coarse adjustment of the phase PHIIN of the input signal Vin. In some embodiments, the second phase difference Δ PHI2 is referred to as a fine tuning of the phase PHIIN of the input signal Vin. In some embodiments, the ratio of the second phase difference Δ PHI2 to the first phase difference Δ PHI1 is about 1/5 to 1/2. In some embodiments, the ratio of fine to coarse tuning of the phase shift circuit 400a is approximately 1/5 to 1/2.

In some embodiments, the first phase difference Δ PHI1 is greater than the second phase difference Δ PHI 2. In some embodiments, the sum of the coarse (e.g., first phase difference Δ PHI1) and fine (e.g., second phase difference Δ PHI2) is equal to the phase shift or phase difference Δ θ 1 represented by equation 1.

Other configurations or amounts of gate stack 406 are within the intended scope of the present disclosure.

The phase shift circuit 400 further includes a set of contacts 408 extending in the second direction Y over the active region 402 and disposed between at least the gates 406a, 406b of the set of gates 406. The set of contacts 408 is positioned at a third level different from the first level and the second level. In some embodiments, the third level of the phase shift circuit 400 is a metal-on-metal diffusion level.

Contact set 408 includes one or more of contacts 408a, 408b, 408c, 408d, or 408 e. The contact 408a is disposed between the gate 406a of the gate set 406 and the gate 404a of the gate set 404. The contact 408b is disposed between the gate 404b of the gate set 404 and the gate 404a of the gate set 404. A contact 408c is disposed between the gate 404b of the gate set 404 and the gate 404c of the gate set 404. A contact 408d is disposed between the gate 404c of the gate set 404 and the gate 404d of the gate set 404. Contact 408e is disposed between gate 406b of gate set 406 and gate 404d of gate set 404.

In some embodiments, at least the contact 408A, 408c, or 408e of the set of contacts 408 is a source contact corresponding to the source terminal of the transistor 202A, 202B, 602A, 602B, 802A, 802B (fig. 2A, 2B, 6A, 6B, 8A, 8B) or 204a, 204B, 604a, 604B, 804a, 804B (fig. 2A, 2B, 6A, 6B, 8A, 8B).

In some embodiments, at least contact 408B or 408d of contact set 408 is a drain contact that corresponds to a drain terminal of transistor 202A, 202B, 602A, 602B, 802A, 802B (fig. 2A, 2B, 6A, 6B, 8A, 8B) or 204a, 204B, 604a, 604B, 804a, 804B (fig. 2A, 2B, 6A, 6B, 8A, 8B).

IN some embodiments, the contacts 408b, 408d are mutually coupled to the input terminal IN and configured to receive the input signal Vin. In some embodiments, the contacts 408a, 408c, 408e are mutually coupled to the output terminal OUT and configured to output the output signal Vout.

In some embodiments, the active region 402 includes a first source region coupled to a contact 408a (e.g., implant region 402a), a second source region coupled to a contact 408c (e.g., implant region 402c), a third source region coupled to a contact 408e (e.g., implant region 402e), a first drain region coupled to a contact 408b (e.g., implant region 402b), and a second drain region coupled to a contact 408d (e.g., implant region 402 d). Other configurations or amounts of contact sets 408 are within the intended scope of the present disclosure.

Phase shift circuit 400 also includes insulating block groups 430, 432. The insulating region groups 430, 432 extend in the second direction Y and over the active region 402.

An insulating block group 430 is disposed between the gate group 404 and the active region 402. The insulating region group 430 includes one or more of the insulating regions 430a, 430b, 430c, or 430 d. The insulating region 430a, 430b, 430c, or 430d of the insulating region group 430 is below the gate 404a, 404b, 404c, or 404d of the corresponding gate group 404. In some embodiments, the insulating region 430a, 430b, 430c, or 430d of the insulating region group 430 is configured to electrically isolate the corresponding gate 404a, 404b, 404c, or 404d of the gate group 404 from the active region 402. In some embodiments, each insulating region of the insulating region group 430 is separated from another insulating region of the insulating region group 430 by a first pitch (not labeled) in the first direction X.

An insulating region group 432 is disposed between the gate group 406 and the active region 402. The insulating zone set 432 includes one or more of insulating zones 432a or 432 b. An insulating region 432a or 432b of insulating region group 432 is below a corresponding gate 406a or 406b of gate group 406. In some embodiments, an insulating region 432a or 432b of insulating regions 432 is configured to electrically isolate a corresponding gate 406a or 406b of gate set 406 from active region 402. In some embodiments, one or more of the insulating regions of insulating region group 430 or 432 includes at least a dielectric material, a gate oxide, a high-K dielectric (high-K dielectric), or the like. Other configurations or amounts of the insulating zone groups 430 or 432 are within the contemplated scope of the present disclosure.

In some embodiments, the phase shift circuit 400 includes a set of gates 406 positioned along opposite ends of the active region 402 to cover and protect the ends of the active region 402 or the cell regions of the phase shift circuit 400 during manufacturing or processing, thereby providing additional reliability during processing. In some embodiments, by configuring the set of gates 406 to be functional or operational, such as a portion of the transistor 204a of fig. 2A or the gate of the transistor 204B of fig. 2B, the transistor 204 is configured as a variable capacitor having a capacitance value of C1, and provides additional regulation functionality of the phase shift circuit 400 and regulation functionality provided by the resistor R1 (e.g., the transistor 202A or 202B) as compared to other embodiments having a single regulation mechanism.

In some embodiments, the phase of the phase shift circuit 400 is adjusted by multiple controls, and the phase shift circuit 400 has better precision and wider adjustable range than other embodiments.

In some embodiments, by utilizing the set of gates 406 as a functional or operative portion of the transistors in the phase shift circuit 400, the phase shift circuit 400 is easier to implement and occupies less area than other embodiments in which the dummy gates are not operative and occupy additional space. In some embodiments, phase shift circuit 400 is not an active phase shifter and therefore has less power consumption than other embodiments.

In some embodiments, each of the advantages of the phase shift circuit 400 can also be applied to at least one of the phase shift circuits 100 (fig. 1), 200A, 200B (fig. 2A, 2B), 500A, 500B (fig. 5A, 5B), 600A, 600B (fig. 6A, 6B), 700 (fig. 7), 800A, 800B (fig. 8A, 8B), or 900 (fig. 9), but are not described herein for brevity.

Fig. 5A is a circuit diagram of a phase shift circuit 500A according to some embodiments.

The phase shift circuit 500A is a variation of the phase shift circuit 100 of fig. 1, and similar detailed description is therefore omitted. For example, the phase shift circuit 500A illustrates an example in which a variable capacitor (e.g., C2) is coupled in parallel with a variable resistor (e.g., R2).

Compared to the phase shift circuit 100 of fig. 1, the capacitor C2 and the resistor R2 of the phase shift circuit 500A replace the capacitor C1, and similar detailed descriptions are omitted.

Each of the second terminal of the resistor R1, the first terminal of the capacitor C2, the first terminal of the resistor R2, and the output terminal OUT are coupled to each other. The second terminal of the capacitor C2 and the second terminal of the resistor R2 are coupled to the reference voltage supply terminal VSS. Other orders, resistances, or capacitances in the phase shift circuit 500A are within the intended scope of the present disclosure.

Fig. 5B is a circuit diagram of a phase shift circuit 500B according to some embodiments.

The phase shift circuit 500B is a variation of the phase shift circuit 100 of fig. 1 or the phase shift circuit 500A of fig. 5A, and similar detailed description is omitted. For example, the phase shift circuit 500B illustrates an example in which a variable capacitor (e.g., C3) is coupled in parallel with other variable capacitors (e.g., C4).

Compared to the phase shift circuit 500A of fig. 5A, the capacitor C3 of the phase shift circuit 500B replaces the capacitor C2, the capacitor C4 of the phase shift circuit 500B replaces the resistor R2, and similar detailed descriptions are omitted.

Each of the second terminal of the resistor R1, the first terminal of the capacitor C3, the first terminal of the capacitor C4, and the output terminal OUT are coupled to each other. The second terminal of the capacitor C3 and the second terminal of the capacitor C4 are coupled to the reference voltage supply terminal VSS. Other orders, resistances, or capacitances in phase shift circuit 500B are within the intended scope of the present disclosure.

Fig. 6A is a circuit diagram of a phase shift circuit 600A according to some embodiments.

Phase shift circuit 600A is an embodiment of phase shift circuit 500A of fig. 5A or phase shift circuit 100 of fig. 1.

Phase shift circuit 600A includes resistor R1 coupled to transistors 602a, 604 a. The transistor 602a is an embodiment of the resistor R2 of fig. 5A, the transistor 604a is an embodiment of the capacitor C2 of fig. 5A, and similar detailed descriptions are omitted.

The phase shift circuit 600A is also a variation of the phase shift circuit 200A of fig. 2A, and similar detailed descriptions are omitted. For example, the transistor 602A is a variation of the transistor 202A of fig. 2A, the transistor 604a is a variation of the transistor 204a of fig. 2A, and similar detailed descriptions are omitted.

The transistors 602a, 604a are nmos transistors. In some embodiments, at least one of the transistors 602a or 604a is a PMOS transistor.

Phase shift circuit 600A is coupled to a first terminal of resistor R1 and is configured to receive input signal Vin. The output terminal OUT of the phase shift circuit 600A is configured to output the output signal Vout. The second terminal of resistor R1, the output terminal of phase shift circuit 600A, the source terminal of transistor 602A, and the source terminal of transistor 604A are each coupled together.

The gate terminal of transistor 602a is configured to receive signal VG. The drain terminal of the transistor 602a is coupled to the reference voltage supply terminal VSS. In some embodiments, transistor 602a is configured as variable resistor R2 of fig. 5A.

The gate terminal of transistor 604a is configured to receive the signal VPODE. In some embodiments, the transistor 604a is configured as the variable capacitance C2 of fig. 5A. The transistor 604a does not include a drain terminal. In some embodiments, the transistor 604a includes a drain terminal (not shown), but the drain terminal is electrically floating.

Other types or numbers of transistors in the phase shift circuit 600A are within the intended scope of the present disclosure.

Fig. 6B is a circuit diagram of a phase shift circuit 600B according to some embodiments.

Phase shift circuit 600B is a variation of phase shift circuit 600A of fig. 6A, and similar detailed description is therefore omitted. Phase shift circuit 600B includes pmos transistors (e.g., transistors 602B, 604B) as compared to phase shift circuit 600A. For example, compared to the phase shift circuit 600A, the transistor 602B of the phase shift circuit 600B replaces the transistor 602a, the transistor 604B of the phase shift circuit 600B replaces the transistor 604a, and similar detailed descriptions are omitted.

Phase shift circuit 600B is an embodiment of phase shift circuit 500A of fig. 5A or phase shift circuit 100 of fig. 1.

The transistors 602b, 604b are PMOS transistors. In some embodiments, at least one of the transistors 602b or 604b is an nmos transistor.

In some embodiments, at least the transistor 602a, 602b, 604a, or 604b is a fin field effect transistor. Other types or numbers of transistors in phase shift circuit 600B are within the intended scope of the present disclosure.

Other types or numbers of transistors in phase shift circuit 600B are within the intended scope of the present disclosure.

Top view of phase shift circuit

Fig. 7 is a top view of a phase shift circuit 700 according to some embodiments.

In some embodiments, the cross-sectional view of phase shift circuit 700 of fig. 7 or phase shift circuit 900 of fig. 9 is similar to the cross-sectional view of phase shift circuit 400 in fig. 4B, and similar detailed descriptions and descriptions are not provided to simplify the description.

Phase shift circuit 700 is an embodiment of phase shift circuit 600A or 600B of fig. 6A or 6B, shown in a top view.

The phase shift circuit 700 is a variation of the phase shift circuit 400 of fig. 4A, 4B, and similar detailed description is omitted. In contrast to the phase shift circuit 400 of fig. 4A and 4B, the contact set 708 of the phase shift circuit 700 replaces the contact set 408, and similar detailed descriptions are omitted.

Set of contacts 708 includes one or more of contacts 708a, 708b, 708c, 708d, or 708 e. In some embodiments, the arrangement of contacts 708a, 708B, 708c, 708d, or 708e of the set of contacts 708 is similar to the corresponding contacts of the set of contacts 408 of fig. 4A, 4B, and similar detailed descriptions are therefore omitted to simplify the description.

In some embodiments, at least one contact 708A, 708c, or 708e of the set of contacts 708 is a source contact corresponding to a source terminal of the transistor 602A, 602B, 802A, 802B (fig. 2A, 2B, 6A, 6B, 8A, 8B) or 604a, 604B, 804a, 804B (fig. 2A, 2B, 6A, 6B, 8A, 8B).

In some embodiments, at least contact 708B or 708d of the set of contacts 708 is a drain contact that corresponds to a drain terminal of the transistor 602A, 602B, 802A, 802B (fig. 2A, 2B, 6A, 6B, 8A, 8B) or 604a, 604B, 804a, 804B (fig. 2A, 2B, 6A, 6B, 8A, 8B).

IN contrast to the phase shift circuit 400 of fig. 4A and 4B, the contacts 708B and 708d are not coupled to the input terminal IN. In some embodiments, the contacts 708b, 708d are coupled to a reference voltage supply terminal VSS (e.g., ground terminal GND).

In contrast to the phase shift circuit 400 of fig. 4A and 4B, the contacts 708a, 708c, 708e and the output OUT are coupled to each other and further coupled to a resistor R1 (not shown). In some embodiments, the top view of the resistor R1 is similar to the top view of the transistor 202a or 202b of fig. 4A, and similar detailed description is omitted accordingly.

In some embodiments, the active region 402 includes a first source region (e.g., implant region 402a) coupled to contact 708a, a second source region (e.g., implant region 402c) coupled to contact 708c, a third source region (e.g., implant region 402e) coupled to contact 708e, a first source region (e.g., implant region 402b) coupled to contact 708b, and a second source region (e.g., implant region 402d) coupled to contact 708 d. Other configurations and amounts of contact sets 708 are within the intended scope of the present disclosure.

In some embodiments, the set of gates 404 of the phase shift circuit 700 of fig. 7 corresponds to the gates of the transistors 602a of fig. 6A or the gates of the transistors 602B of fig. 6B. In some embodiments, the transistor 602a or 602b is configured to adjust a resistance value of a resistor R2 (fig. 5A) of the phase shift circuit 700 in response to the voltage VG. In some embodiments, the gates 404a, 404b, 404c, 404d of the gate set 404 of fig. 7 are coupled to each other, configured to receive a voltage VG, and are part of the transistors 602a or 602 b. Other configurations and amounts of the gate set 404 of fig. 7 are within the intended scope of the present disclosure.

In some embodiments, gates 406A and 406B of gate set 406 of phase shift circuit 700 of fig. 7 are configured to be functional or operational, such as a portion of transistor 604a of fig. 6A or a gate of transistor 604B of fig. 6B. For example, in some embodiments, the gate set 406 of fig. 7 corresponds to the gate of the transistor 604a of fig. 6A or the gate of the transistor 604B of fig. 6B. In some embodiments, the gate set 406 of fig. 7 is configured to receive the voltage VPODE. In some embodiments, the transistors 604a or 604b are configured to adjust the capacitance value of the capacitance C2 (fig. 5A) of the phase shift circuit 700 in response to the voltage VPODE. In some embodiments, the gates 406a, 406b of the gate set 406 of fig. 7 are coupled to each other, configured to receive the voltage VPODE, and are part of the transistors 604a or 604 b.

In some embodiments, the capacitance value of the capacitor C2 of the phase shift circuit 700 is adjusted by adjusting the voltage VPODE received by the gates 406a, 406b of the phase shift circuit 700 of fig. 7, thereby causing an adjustment or change in the phase PHIOUT of the output signal OUT of the phase shift circuit 700 as compared to the phase PHIIN of the input signal Vin. IN some embodiments, the phase PHIOUT of the output signal of phase shift circuit 700 changes by a third phase difference Δ PHI3 relative to the phase PHIIN of the input signal IN. In some embodiments, the third phase difference Δ PHI3 is about 0 degrees to 360 degrees.

Similarly, in some embodiments, the resistance of the resistor R2 of the phase shift circuit 700 is adjusted by adjusting the voltage VG received by the gates 404a, 404b, 404c, 404d of the phase shift circuit 700 of fig. 7, thereby causing the phase PHIOUT of the output signal OUT of the phase shift circuit 700 to adjust or change compared to the phase PHIIN of the input signal Vin. IN some embodiments, the phase PHIOUT of the output signal of phase shift circuit 700 changes by a fourth phase difference Δ PHI4 relative to the phase PHIIN of the input signal IN. In some embodiments, the fourth phase difference Δ PHI4 is about 0 degrees to 360 degrees.

In some embodiments, the third phase difference Δ PHI3 is referred to as a coarse adjustment of the phase PHIIN of the input signal Vin of the phase shift circuit 700. In some embodiments, the fourth phase difference Δ PHI4 is referred to as a fine tuning of the phase PHIIN of the input signal Vin of the phase shift circuit 700. In some embodiments, the ratio of the fourth phase difference Δ PHI4 to the third phase difference Δ PHI3 is about 1/5 to 1/2. In some embodiments, the ratio of the fine to coarse tuning of the phase shift circuit 700 is approximately 1/5 to 1/2.

In some embodiments, the third phase difference Δ PHI3 is greater than the fourth phase difference Δ PHI 4. In some embodiments, the third phase difference Δ PHI3 is less than the fourth phase difference Δ PHI 4. In some embodiments, the sum of the coarse (e.g., third phase difference Δ PHI3) and fine (e.g., fourth phase difference Δ PHI4) phases is equal to the phase shift or phase difference Δ θ 1 represented by equation 1.

Other configurations or amounts of the gate stack 406 of fig. 7 are within the intended scope of the present disclosure.

Fig. 8A is a circuit diagram of a phase shift circuit 800A according to some embodiments.

Phase shift circuit 800A is an embodiment of phase shift circuit 500B of fig. 5B or phase shift circuit 100 of fig. 1.

Phase shift circuit 800A includes resistor R1 coupled to transistors 802a, 804 a. The transistor 802a is an embodiment of the capacitor C4 of fig. 5B, the transistor 804a is an embodiment of the capacitor C3 of fig. 5B, and similar detailed descriptions are omitted.

Phase shift circuit 800A is a variation of phase shift circuit 600A of fig. 6A and similar detailed description is omitted. Compared to the phase shift circuit 600A, the transistor 802a replaces the transistor 602a, the transistor 804a replaces the transistor 604a, and similar detailed description is omitted.

In contrast to phase shift circuit 600A, the source of transistor 802a of phase shift circuit 800A is electrically floating and not coupled to the reference voltage supply terminal VSS. By configuring the drain of the transistor 802a to be electrically floating, the transistor 802a is configured as the capacitor C4 of fig. 5B, which has a variable resistance value in response to the voltage VG. In some embodiments, the transistor 804a is configured as the capacitor C3 of fig. 5B, which has a variable resistance value in response to the voltage VPODE. In some embodiments, the capacitance value of the capacitor C4 is greater than the capacitance value of the capacitor C3. In some embodiments, the capacitance value of the capacitor C4 is less than the capacitance value of the capacitor C3.

Phase shift circuit 800A is a variation of phase shift circuit 200A of fig. 2A and similar detailed description is omitted. For example, the transistor 802A is a variation of the transistor 202A of fig. 2A, the transistor 804a is a variation of the transistor 204a of fig. 2A, and similar detailed descriptions are omitted.

The transistors 802a, 804a are nmos transistors. In some embodiments, at least one of the transistors 802a or 804a is a PMOS transistor.

Other types or numbers of transistors in phase shift circuit 800A are within the intended scope of the present disclosure.

Fig. 8B is a circuit diagram of a phase shift circuit 800B according to some embodiments.

Phase shift circuit 800B is an embodiment of phase shift circuit 500B of fig. 5B or phase shift circuit 100 of fig. 1.

Phase shift circuit 800B is a variation of phase shift circuit 800A of fig. 8A, and similar detailed description is therefore omitted. Phase shift circuit 800B includes pmos transistors (e.g., transistors 802B, 804B) as compared to phase shift circuit 800A. For example, compared to the phase shift circuit 800A, the transistor 802a is replaced by the transistor 802B of the phase shift circuit 800B, the transistor 804a is replaced by the transistor 804B of the phase shift circuit 800B, and similar detailed descriptions are omitted.

The transistors 802b, 804b are PMOS transistors. In some embodiments, at least one of the transistors 802b or 804b is an nmos transistor.

In some embodiments, at least one of the transistors 802a, 802b, 804a, or 804b is a fin field effect transistor.

Other types or numbers of transistors in phase shift circuit 800B are within the intended scope of the present disclosure.

Top view of phase shift circuit

Fig. 9 is a top view of a phase shift circuit 900 according to some embodiments.

Phase shift circuit 900 an embodiment of a phase shift circuit 800A or 800B of fig. 8A or 8B is shown in a top view. The phase shift circuit 900 is a variation of the phase shift circuit 400 of fig. 4A, 4B and the phase shift circuit 700 of fig. 7, and similar detailed description is therefore omitted. In contrast to the phase shift circuit 700 of fig. 7, the contact set 908 of the phase shift circuit 900 replaces the contact set 708, and similar detailed description is omitted.

Contact set 908 includes one or more of contacts 708a, 908b, 708c, 908d, or 708 e. In some embodiments, the arrangement of the contacts 708a, 908B, 708c, 908d, or 708e of the set of contacts 908 is similar to the corresponding contacts of the set of contacts 408 of fig. 4A, 4B, and similar detailed descriptions are therefore omitted to simplify the description.

In some embodiments, at least the contact 908B or 908d of the set of contacts 908 is a source contact, which corresponds to a drain terminal of the transistor 802a, 802B (fig. 8A, 8B) or 804a, 804B (fig. 8A, 8B).

In contrast to the phase shift circuit 700 of fig. 7, the contacts 908b, 908d of the phase shift circuit 900 are electrically floating and are not coupled to the reference voltage supply terminal VSS (e.g., ground).

In some embodiments, the active region 402 includes a first source region (e.g., implant region 402a) coupled to contact 708a, a second source region (e.g., implant region 402c) coupled to contact 708c, a third source region (e.g., implant region 402e) coupled to contact 708e, a first drain region (e.g., implant region 402b) coupled to contact 908b, and a second drain region (e.g., implant region 402d) coupled to contact 908 d. Other arrangements or amounts of contact set 908 are within the intended scope of the present disclosure.

In some embodiments, the set of gates 404 of the phase shift circuit 900 of fig. 9 corresponds to the gates of the transistors 802a of fig. 8A or the gates of the transistors 802B of fig. 8B. In some embodiments, the transistors 802a or 802B are configured to adjust the capacitance value of the capacitor C4 (fig. 5B) of the phase shift circuit 900 in response to the voltage VG. In some embodiments, the gates 404a, 404b, 404c, 404d of the gate set 404 of fig. 9 are coupled to each other, configured to receive the voltage VG and are part of the transistors 802a or 802 b. Other configurations or amounts of the gate set 404 of fig. 9 are within the intended scope of the present disclosure.

In some embodiments, the gates 406a, 406B of the gate set 406 of the phase shift circuit 900 of fig. 9 are configured to be functional or operational, such as a portion of the transistor 804a of fig. 8A or the gate of the transistor 804B of fig. 8B. For example, in some embodiments, the gate set 406 of fig. 9 corresponds to the gate of the transistor 804a of fig. 8A or the gate of the transistor 804B of fig. 8B. In some embodiments, the gate set 406 of fig. 9 is configured to receive the voltage VPODE. In some embodiments, the transistor 804a or 804B is configured to adjust a capacitance value of the capacitor C3 (fig. 5B) of the phase shift circuit 900 in response to the voltage VPODE. In some embodiments, the gates 406a, 406b of the gate set 406 of fig. 9 are coupled to each other, configured to receive the voltage VPODE, and are part of the transistors 804a or 804 b.

In some embodiments, the capacitance value of the capacitor C3 of the phase shift circuit 900 is adjusted by adjusting the voltage VPODE received by the gates 406a, 406b of the phase shift circuit 900 of fig. 9, thereby causing an adjustment or change in the phase PHIOUT of the output signal OUT of the phase shift circuit 900 compared to the phase PHIIN of the input signal Vin. IN some embodiments, the phase PHIOUT of the output signal of phase shift circuit 900 varies by a fifth phase difference Δ PHI5 relative to the phase PHIIN of the input signal IN. In some embodiments, the fifth phase difference Δ PHI5 is about 0 degrees to 360 degrees.

Similarly, in some embodiments, the capacitance value of the capacitor C4 of the phase shift circuit 900 is adjusted by adjusting the voltage VG received by the gates 404a, 404b, 404C, 404d of the phase shift circuit 900 of fig. 9, thereby causing an adjustment or change in the phase PHIOUT of the output signal OUT of the phase shift circuit 900 compared to the phase PHIIN of the input signal Vin. IN some embodiments, the phase PHIOUT of the output signal of phase shift circuit 900 is changed by a sixth phase difference Δ PHI6 relative to the phase PHIIN of the input signal IN. In some embodiments, sixth phase difference Δ PHI6 is approximately 0 degrees to 360 degrees.

In some embodiments, the fifth phase difference Δ PHI5 is referred to as a fine tuning of the phase PHIIN of the input signal Vin of the phase shift circuit 900. In some embodiments, the sixth phase difference Δ PHI6 is referred to as a coarse adjustment of the phase PHIIN of the input signal Vin of the phase shift circuit 900. In some embodiments, the ratio of the sixth phase difference Δ PHI6 to the fifth phase difference Δ PHI5 is about 1/5 to 1/2. In some embodiments, the ratio of the fine to coarse tuning of the phase shift circuit 900 is approximately 1/5 to 1/2.

In some embodiments, the fifth phase difference Δ PHI5 is less than the sixth phase difference Δ PHI 6. In some embodiments, the fifth phase difference Δ PHI5 is greater than the sixth phase difference Δ PHI 6. In some embodiments, the sum of the fine (e.g., fifth phase difference Δ PHI5) and coarse (e.g., sixth phase difference Δ PHI6) is equal to the phase shift or phase difference Δ θ 1 represented by equation 1.

Other configurations or amounts of the gate stack 406 of fig. 9 are within the intended scope of the present disclosure.

In some embodiments, the phase shift circuit 400 may also include other structures or layers (e.g., fin structures, overlying metal layers, vias, or the like), which are not depicted for simplicity.

10A-10D illustrate corresponding schematic diagrams 1000A-1000D of phase differences that may be used in the phase shift circuits of FIGS. 2A, 2B, according to some embodiments.

The schematic diagrams 1000A-1000D corresponding to FIGS. 10A-10D include a horizontal axis and a vertical axis. As shown in fig. 10A to 10D, the horizontal axis shows the frequency range of the input signal Vin applied to the phase shift circuit 200A, 200B, or 400, and the vertical axis shows the range of the phase difference (for example, the phase difference Δ θ 1 represented by equation 1) of the phase shift circuit 200A, 200B, or 400.

As shown in fig. 10A to 10D, the corresponding diagrams 1000A-1000D show the phase characteristics of the voltage VG supplied to the gate of the transistor 202a or 202b in the range of the voltage VPODE supplied to the gate of the transistor 204a or 204b and the frequency range of the input signal Vin.

In fig. 10A, the diagram 1000A includes curves 1002a, 1002b, 1002c, 1002d corresponding to a voltage VG equal to 0.6 volts. Curve 1002a corresponds to voltage VPODE equal to 0.2 volts, curve 1002b corresponds to voltage VPODE equal to 0.4 volts, curve 1002c corresponds to voltage VPODE equal to 0.6 volts, and curve 1002d corresponds to voltage VPODE equal to 0.8 volts. As shown in fig. 10A, for a given frequency of the input signal Vin, the phase difference Δ θ 1 increases as the voltage VPODE increases.

In FIG. 10B, the graph 1000B includes curves 1010a, 1010B, 1010c, 1010d corresponding to a voltage VG equal to 0.8 volts. Curve 1010a corresponds to a voltage VPODE equal to 0.2 volts, curve 1010b corresponds to a voltage VPODE equal to 0.4 volts, curve 1010c corresponds to a voltage VPODE equal to 0.6 volts, and curve 1010d corresponds to a voltage VPODE equal to 0.8 volts. As shown in fig. 10B, for a given frequency of the input signal Vin, the phase difference Δ θ 1 increases as the voltage VPODE increases.

In fig. 10C, the diagram 1000C includes curves 1020a, 1020b, 1020C, 1020d corresponding to a voltage VG equal to 1.0 volt. Curve 1020a corresponds to voltage VPODE equal to 0.2 volts, curve 1020b corresponds to voltage VPODE equal to 0.4 volts, curve 1020c corresponds to voltage VPODE equal to 0.6 volts, and curve 1020d corresponds to voltage VPODE equal to 0.8 volts. As shown in fig. 10C, for a given frequency of the input signal Vin, the phase difference Δ θ 1 increases as the voltage VPODE increases.

In fig. 10D, the diagram 1000D includes curves 1030a, 1030b, 1030c corresponding to voltages VG equal to 0.8 volts. Curve 1030a corresponds to a voltage VPODE equal to-1.0 volts, curve 1030b corresponds to a voltage VPODE equal to 0.0 volts, and curve 1030c corresponds to a voltage VPODE equal to 1.0 volts. As shown in fig. 10D, for a given frequency of the input signal Vin, the phase difference Δ θ 1 increases as the voltage VPODE increases.

Method of producing a composite material

Fig. 11 is a flow diagram of a method 1100 of forming or fabricating a phase shift circuit in accordance with some embodiments. It is to be appreciated that additional operations can be performed before, during, and/or after the method 1100 described in fig. 11, and that some of the other operations can be described only briefly herein. In some embodiments, method 1100 may be used to form a phase shift circuit, such as phase shift circuit 100 (fig. 1), 200A, 200B (fig. 2A, 2B), 400 (fig. 4A, 4B), 500A, 500B (fig. 5A, 5B), 600A, 600B (fig. 6A, 6B), 700 (fig. 7), 800A, 800B (fig. 8A, 8B), or 900 (fig. 9). In some embodiments, method 1100 may be used to form a phase shift circuit having a similar structural relationship or pattern as layout design 300 (FIG. 3).

In operation 1102 of method 1100, a layout design 300 of a phase shift circuit (e.g., phase shift circuit 100, 200A, 200B, 400, 500A, 500B, 600A, 600B, 700, 800A, 800B, or 900) is generated. Operation 1102 is performed by a processing device (e.g., processor 1302 of fig. 13) configured to execute instructions to generate layout design 300. In some embodiments, layout design 300 is in a graphic database system II (GDSII) file format.

In operation 1104 of method 1100, a phase shift circuit (e.g., phase shift circuit 100, 200A, 200B, 400, 500A, 500B, 600A, 600B, 700, 800A, 800B, or 900) is fabricated based on layout design 300. In some embodiments, operation 1104 of method 1100 includes fabricating at least one reticle based on layout design 300 and fabricating a phase shift circuit (e.g., phase shift circuit 100, 200A, 200B, 400, 500A, 500B, 600A, 600B, 700, 800A, 800B, or 900) based on the at least one reticle.

FIG. 12 is a flow diagram of a method 1200 of generating a layout design for a phase shift circuit according to some embodiments. It is to be appreciated that additional operations may be performed before, during, and/or after the method 1200 described in fig. 11, and that some of the other operations may be described only briefly herein. In some embodiments, the method 1200 may be used to generate a layout pattern for a layout design 300 (fig. 3) of one or more phase shift circuits, such as the phase shift circuits 100, 200A, 200B, 400, 500A, 500B, 600A, 600B, 700, 800A, 800B, or 900.

In operation 1202 of the method 1200, an active area layout pattern 302 is generated or placed on the layout design 300. In some embodiments, the active area layout pattern 302 corresponds to the active area 402 fabricated at the first level. In some embodiments, the first level is an oxide diffusion level or an active level.

In operation 1204 of the method 1200, a first set of gate layout patterns 304 is generated or placed on the layout design 300. In some embodiments, the first gate layout pattern group 304 corresponds to the first gate group 404. In some embodiments, the first set of gate layout patterns 304 is disposed on a second level (e.g., polysilicon).

In some embodiments, operation 1204 includes generating or placing first gate layout pattern 304a, second gate layout pattern 304b, third gate layout pattern 304c, and fourth gate layout pattern 304 d.

In operation 1206 of the method 1200, a second set of gate layout patterns 306 is generated or placed on the layout design 300. In some embodiments, the second gate layout pattern group 306 corresponds to the fabrication of the second gate group 406. In some embodiments, the second set of gate layout patterns 306 is disposed on a second level (e.g., polysilicon). In some embodiments, operation 1206 includes generating or placing first gate layout pattern 306a and second gate layout pattern 306 b.

In operation 1208 of the method 1200, the metal group 308 is generated or placed on the layout design 300 over the diffusion layout pattern. In some embodiments, the set of metals 308 above the diffusion layout pattern corresponds to the set of manufacturing contacts 408, 708, or 908. In some embodiments, the metal group 308 above the diffusion layout pattern is placed on a third level (e.g., a metal-on-metal diffusion).

In some embodiments, operation 1208 includes generating or disposing the first source region layout pattern 308a, the first drain region layout pattern 308b, the second source region layout pattern 308c, and the second drain region layout pattern 308d and generating the third source region layout pattern 308 e.

In some embodiments, one or more of the layout designs of one or more of the operations of method 1200 are placed in a manner similar to the arrangement shown in layout design 300, and similar detailed descriptions are thus omitted. In some embodiments, one or more of operations 1202, 1204, 1206, or 1208 are not performed.

One or more of the operations of the methods 1100, 1200 are performed by a processing device to execute instructions to fabricate a phase shift circuit, such as the phase shift circuit 100, 200A, 200B, 400, 500A, 500B, 600A, 600B, 700, 800A, 800B, or 900. In some embodiments, one or more operations of the methods 1100, 1200 are performed using the same processing device as used for a different one or more operations of the methods 1100, 1200. In some embodiments, one or more operations of the methods 1100, 1200 are performed using a different processing device than that used for one or more operations of the methods 1100, 1200.

Fig. 13 is a schematic diagram of a system 1300 for designing and manufacturing an integrated circuit layout design in accordance with some embodiments. In some embodiments, system 1300 generates or otherwise places one or more integrated circuit layout designs described herein. In some embodiments, system 1300 manufactures one or more integrated circuits based on one or more integrated circuit layout designs described herein. The system 1300 includes a hardware processor 1302 and a non-transitory computer-readable storage medium 1304 encoded with (i.e., stored by) computer program code 1306 (i.e., a set of executable instructions). The computer readable storage medium 1304 is configured to interact with a manufacturing machine to produce an integrated circuit. The processor 1302 is electrically coupled to the computer-readable storage medium 1304 via the bus 1308. The processor 1302 is also electrically connected to an input/output (I/O) interface 1310 via a bus 1308. The network interface 1312 is also electrically connected to the processor 1302 via the bus 1308. The network interface 1312 couples to the network 1314 such that the processor 1302 and the computer-readable storage medium 1304 may be coupled to external elements via the network 1314. The processor 1302 is configured to execute computer program code 1306 encoded in a computer-readable storage medium 1304 in order to make the system 1300 available to perform some or all of the operations described in the methods 1100 or 1200.

In some embodiments, processor 1302 is a Central Processing Unit (CPU), a multiprocessor, a decentralized processing system, an Application Specific Integrated Circuit (ASIC), and/or a suitable processing unit.

In some embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system, apparatus, or device. The computer-readable storage medium 1304 includes, for example, semiconductor or solid state memory, magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and/or an optical disk. In some embodiments using optical disks, the computer-readable storage medium 1304 includes compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W), and/or Digital Video Disk (DVD).

In some embodiments, the computer readable storage medium 1304 stores computer program code 1306, the computer program code 1306 being configured to cause the system 1200 to perform the method 1100 or the method 1200. In some embodiments, the computer-readable storage medium 1304 also stores information required to perform the method 1100 or the method 1200 and information generated during the performance of the method 1100 or the method 1200, such as the layout design 1316, the user interface 1318, the manufacturing unit 1320, and/or a set of executable instructions to perform the operations of the method 1100 or the method 1200. In some embodiments, layout design 1316 includes one or more of the layout patterns of layout design 300.

In some embodiments, the computer-readable storage medium 1304 stores instructions (e.g., a computer program code 1306) for interfacing with a manufacturing machine. Such instructions (e.g., computer program code 1306) cause the processor 1302 to generate manufacturing instructions readable by a manufacturing machine to efficiently implement the method 1100 or the method 1200 during a manufacturing process.

The system 1300 includes an input/output (I/O) interface 1310 coupled to external circuitry. In some embodiments, the input/output interface 1310 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, and/or cursor direction keys for communicating information and commands to the processor 1302.

The system 1300 also includes a network interface 1312 coupled to the processor 1302. The network interface 1312 allows the system 1300 to communicate with a network 1314 of one or more other computer systems. The network interface 1312 includes a wireless network interface such as Bluetooth, WiFi, WiMAX, GPRS or WCDMA, or a wired network interface such as Ethernet (Ethernet), USB or IEEE-1394. In some embodiments, the methods 1100 or 1200 are implemented in two or more systems 1300, and information such as layout design, user interface, and manufacturing unit is exchanged between the different systems 1300 over a network 1314.

The system 1300 is configured to receive information regarding the layout design via the input/output interface 1310 or the network interface 1312. This information is communicated over bus 1308 to processor 1302 to determine the layout design for producing an integrated circuit, such as phase shift circuit 100, 200A, 200B, 400, 500A, 500B, 600A, 600B, 700, 800A, 800B, or 900. The layout design is then used as layout design 1316, which is stored in computer-readable storage medium 1304. The system 1300 is configured to receive information regarding a user interface via the input/output interface 1310 or the network interface 1312. This information serves as a user interface 1318, which is stored on the computer-readable storage medium 1304. The system 1300 is configured to receive information about the manufacturing unit via the input/output interface 1310 or the network interface 1312. This information is provided as a manufacturing unit 1320, which is stored in the computer readable storage medium 1304. In some embodiments, the manufacturing unit 1320 contains manufacturing information utilized by the system 1300.

In some embodiments, some or all of the methods 1100 or 1200 are implemented as stand-alone application software for execution by a processor. In some embodiments, part or all of method 1100 or 1200 is implemented as application software that is part of additional application software. In some embodiments, method 1100 or 1200 is implemented as a plug-in (plug-in) to an application. In some embodiments, the method 1100 or 1200 is implemented as application software that is part of an Electronic Design Automation (EDA) tool. In some embodiments, method 1100 or 1200 is implemented as application software used by an electronic design automation tool. In some embodiments, an electronic design automation tool is used to generate a layout design for an integrated circuit device. In some embodiments, the layout design is stored in a non-transitory computer readable storage medium. In some embodiments, the layout design uses a layout design such as available from Kaidens design systems, Inc. (CADENCE DESIGN SYSTEMS, Inc.)

A tool or other suitable layout generation tool. In some embodiments, the layout design is generated based on a netlist (netlist) that is created based on the schematic design. In some embodiments, the method 1100 or 1200 is implemented by a fabrication device that uses a reticle set generated by the system 1300 to fabricate an integrated circuit. In some embodiments, system 1300 is a manufacturing deviceIntegrated circuits are fabricated using a mask fabricated based on one or more layout designs of the present disclosure. In some embodiments, the system 1300 of FIG. 13 produces a layout design for an integrated circuit that is smaller than other implementations. In some embodiments, the system 1300 of FIG. 13 produces a layout design for an integrated circuit structure that occupies less area than other embodiments. In some embodiments, the integrated circuit or integrated circuit structure of fig. 13 includes the phase shift circuit 100, 200A, 200B, 400, 500A, 500B, 600A, 600B, 700, 800A, 800B, or 900 of the present description.

FIG. 14 is a block diagram of an integrated circuit manufacturing system 1400 and an integrated circuit manufacturing process flow associated with the integrated circuit manufacturing system 1400 in accordance with at least one embodiment of the present disclosure.

In fig. 14, an integrated circuit fabrication system 1400 includes a plurality of entities, such as a design house 1420, a mask house 1430, and an IC manufacturer/distributor factory 1440, which interact with one another in connection with the design, development, fabrication cycles, and/or servicing of a manufactured integrated circuit device 1460. The entities are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as a private intranet (private intranet) and/or the Internet, and may include wired and/or wireless communication channels. Each entity may interact with other entities and may provide services to and/or receive services from other entities. In some embodiments, two or more of the design chamber 1420, the mask chamber 1430, and the integrated circuit fabrication plant 1440 may be owned by a single large company. In some embodiments, two or more of the design chamber 1420, the mask chamber 1430, and the integrated circuit fabrication plant 1440 coexist and use common resources in a common facility (common facility).

Design room (or design team) 1420 generates an integrated circuit design layout 1422. The integrated circuit design layout 1422 includes a plurality of geometric patterns (layouts) designed for the integrated circuit device 1460. The geometric pattern corresponds to the pattern of a metal layer, an oxide layer, or a semiconductor layer that make up the various components to be fabricated in the integrated circuit device 1460. Such various layers combine to form various integrated circuit features. For example, a portion of the integrated circuit layout 1422 includes various integrated circuit features, such as active regions, gates, sources, and drains formed in a semiconductor substrate (e.g., a silicon wafer) and disposed in various material layers on the semiconductor substrate, metal lines or vias for inter-layer connections (interconnects), and openings (openings) for bond pads (bonding pads). The design chamber 1420 performs the appropriate design steps to form the integrated circuit design layout 1422. The designing step includes one or more of logic design, physical design, or placement and routing. The integrated circuit design layout 1422 is represented in one or more data file files with geometric pattern information. For example, the target layout 1422 may be represented in a GDSII file format or a DFII file format.

The mask chamber 1430 contains data preparation 1432 and mask production 1434. The mask chamber 1430 produces one or more masks using the integrated circuit design layout 1422 for producing the various layers of the integrated circuit device 1460 according to the integrated circuit design layout 1422. The mask chamber 1430 performs mask data preparation 1432 in which the integrated circuit design layout 1422 is translated into a Representative Data File (RDF). Mask data preparation 1432 provides a representative data file to mask production 1434. Mask production 1434 includes a mask writer (mask writer). The mask writer converts the representative data file into an image on a substrate, such as a reticle (reticle) or a semiconductor wafer. The design layout is trimmed via reticle data preparation 1432 to comply with the specific features of the reticle writer and/or the requirements of the integrated circuit fab 1440. In fig. 14, mask data preparation 1432 and mask production 1434 are depicted as separate elements. In some embodiments, the reticle data preparation 1432 and the reticle production 1434 may be collectively referred to as reticle data preparation.

In some embodiments, mask data preparation 1432 includes Optical Proximity Correction (OPC) that uses lithography enhancement techniques to compensate for image errors that may be caused by diffraction (diffraction), interference, other process effects, or the like, for example. The optical proximity correction adjusts the integrated circuit design layout 1422. In some embodiments, the mask data preparation 1432 also includes Resolution Enhancement Techniques (RET), such as off-axis illumination (off-axis illumination), sub-resolution assist features (sub-resolution assist features), phase-shifting masks (phase-shifting masks), other suitable techniques, and the like, or combinations thereof. In some embodiments, Inverse Lithography Technology (ILT) is also used to treat optical proximity correction as an inverse imaging problem.

In some embodiments, mask data preparation 1432 includes a Mask Rule Checker (MRC) that includes a set of mask creation rules for specific geometric constraints and/or connectivity constraints to check the integrated circuit design layout after each process in the optical proximity correction has been performed to ensure that there is sufficient margin (margin) to account for variability in the semiconductor manufacturing process (variability), etc. In some embodiments, the reticle rules checker modifies the integrated circuit design layout to compensate for constraints during reticle production 1434 that may remove a portion of the modifications performed by the optical proximity correction to satisfy the reticle creation rules.

In some embodiments, mask data preparation 1432 includes Lithography Process Checking (LPC) that simulates the process to be performed by the IC fab 1440 to fabricate the IC device 1460. The photolithography process inspection simulates the process based on the integrated circuit design layout 1422 to create a simulated fabrication device, such as the integrated circuit device 1460. The process parameters in the lithography process inspection simulation may include parameters associated with various processes of the integrated circuit manufacturing cycle, parameters associated with tools used to manufacture the integrated circuit, and/or other aspects of the manufacturing process. The lithography process inspection takes into account various factors such as aerial image contrast (aerial image contrast), depth of focus (DOF), Mask Error Enhancement Factor (MEEF), other suitable factors, and the like or combinations thereof. In some embodiments, after the simulated fabricated devices have been formed by lithography process inspection, if the simulated devices are not sufficiently close in shape to meet the design rules, the OPC and/or reticle rule inspection is repeated to further improve the integrated circuit design layout 1422.

It should be understood that the description of the mask data preparation 1432 described above has been simplified for clarity. In some embodiments, the mask data preparation 1432 includes additional features such as Logic Operations (LOP) to modify the integrated circuit design layout according to manufacturing rules. In addition, during data preparation 1432, the processes applied to the integrated circuit design layout 1422 may be performed in a variety of different orders.

After reticle data preparation 1432 and during reticle production 1434, a reticle or reticle group is produced based on the modified integrated circuit design layout. In some embodiments, an electron-beam (e-beam) or multiple electron-beam mechanism is used to form a pattern on a reticle (reticle or reticle) based on a modified integrated circuit design layout. The mask may be formed by various techniques. In some embodiments, the mask is formed using binary technology (binary technology). In some embodiments, the mask pattern includes a cloth transparent region and a transparent region. A radiation beam (e.g., an Ultraviolet (UV) beam) is used to expose an image sensitive material layer (e.g., photoresist) that has been coated on the wafer, which is blocked by the opaque regions and passes through the transparent regions. In one example, a binary mask comprises a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in an opaque region of the mask. In another example, the mask is formed using a phase shift technique. In a Phase Shift Mask (PSM), features in a pattern formed on the mask are configured to have an appropriate phase difference (phase difference) to enhance resolution and imaging quality. In various embodiments, the phase shift mask may be an attenuated PSM (attenuated PSM) or an alternating PSM (alternating PSM). The mask resulting from mask production 1434 is used in various processes. For example, the mask may be used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and/or in other suitable processes.

Integrated circuit fabrication facility 1440 is an integrated circuit fabrication entity that includes one or more fabrication facilities for fabricating a variety of different integrated circuit products. In some embodiments, the IC foundry 1440 is a semiconductor foundry (foundry). For example, there may be a first fabrication facility for front-end-of-line (FEOL) fabrication of a plurality of integrated circuit products, while a second fabrication facility may provide back-end-of-line (BEOL) fabrication for interconnect and packaging of the integrated circuit products, and a third fabrication facility may provide other wafer foundry physical services.

The integrated circuit fab 1440 uses the mask (or masks) produced by the mask chamber 1430 to fabricate the integrated circuit device 1460. Thus, the integrated circuit fab 1440 at least indirectly manufactures the integrated circuit device 1460 using the integrated circuit design layout 1422. In some embodiments, semiconductor wafer 1442 is fabricated by an integrated circuit fab 1440 using a mask (or multiple masks) to form an integrated circuit device 1460. Semiconductor wafer 1442 comprises a silicon substrate or other suitable substrate having a material layer formed thereon. Semiconductor wafer 1442 also includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent fabrication steps).

The integrated circuit fabrication system 1400 is shown with a design chamber 1420, a mask chamber 1430, or an integrated circuit fabrication plant 1440 as separate elements or entities. However, it is understood that one or more of the design chamber 1420, the mask chamber 1430, or the integrated circuit fabrication plant 1440 are part of the same element or entity.

Details regarding integrated circuit manufacturing systems, such as the integrated circuit manufacturing system 1400 of fig. 14, and the integrated circuit manufacturing flows associated therewith, may be found, for example, in U.S. patent No. 9,256,709, issued on 9/2/2016, U.S. pre-authorization publication No. 20150278429, issued on 1/10/2015, U.S. pre-authorization publication No. 20140040838, issued on 6/2/2014, and U.S. patent No. 7,260,442, issued on 21/8/2007, each of which is incorporated herein by reference in its entirety.

One of ordinary skill in the art will immediately appreciate that one or more embodiments of the present disclosure achieve one or more of the above advantages. After reading the foregoing specification, one of ordinary skill in the art can make various changes and substitutions that are appropriate and contemplated in a broad manner. Accordingly, the scope of the present disclosure should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

One aspect of the present disclosure relates to a phase shifter circuit. In some embodiments, an active region, a first gate set, a second gate set, and a contact set are included. In some embodiments, the active region extends in a first direction and is positioned at a first level. In some embodiments. The first gate group extends in a second direction different from the first direction, overlaps the active region, and is positioned at a second level different from the first level. In some embodiments, each gate of the first gate group is separated from other gates of the first gate group in the first direction. In some embodiments, the second set of gates extends in a second direction, overlaps the active region and is positioned at a second level, is disposed along an opposite edge of the active region and is configured to receive a first voltage, and is part of the first transistor. In some embodiments, the first transistor is configured to adjust a first capacitance value of the phase shifter in response to the first voltage. In some embodiments, the set of contacts extends in a second direction, is over the active region and is positioned at a third level different from the first level, and is disposed between at least the second set of gates. In some embodiments, the set of contacts includes a first source contact, a first drain contact, a second source contact, a second drain contact, and a third source contact. In some embodiments, the first source contact extends in a second direction, is over the active region and is positioned at the third level, and is disposed between the first gates of the first gate set and the first gates of the second gate set. In some embodiments, the first drain contact extends in a second direction, is over the active region and is positioned at the third level, and is disposed between the first gate of the first gate set and the second gate of the first gate set. In some embodiments, a second source contact extends in a second direction, is over the active region and positioned at a third level, and is disposed between the second gate of the first gate set and the third gate of the first gate set. In some embodiments, a second drain contact extends in a second direction, is over the active region and positioned at a third level, and is disposed between the third gate of the first gate set and the fourth gate of the first gate set. In some embodiments, a third source contact extends in the second direction, is over the active region and positioned at the third level, and is disposed between the fourth gate of the first gate set and the second gate of the second gate set. In some embodiments, the active region includes a first source region coupled to the first source contact, a second source region coupled to the second source contact, a third source region coupled to the third source contact, a first drain region coupled to the first drain contact, and a second drain region coupled to the second drain contact. In some embodiments, the phase shifter further comprises an input configured to receive an input signal. In some embodiments, the first drain region, the second drain region, and the input are coupled to each other. In some embodiments, the phase shifter further comprises an output configured to output the output signal. In some embodiments, the first source region, the second source region, the third source region, and the output terminal are father-coupled. In some embodiments, the phase shifter further comprises an input configured to receive an input signal having a first phase, an output configured to output an output signal having a second phase different from the first phase, and a resistor having a first side coupled to the input. In some embodiments, the first source terminal, the second source terminal, the third source terminal and the second side of the resistor are coupled to each other. In some embodiments, the first drain terminal and the second drain terminal are coupled to each other and further coupled to a reference voltage supply terminal. In some embodiments, the first drain terminal and the second drain terminal are electrically floating. In some embodiments, the first gate group includes a first gate, a second gate, a third gate, and a fourth gate. In some embodiments, the first gate, the second gate, the third gate, and the fourth gate of the first gate group are coupled to each other, configured to receive the second voltage, and are part of the second transistor. In some embodiments, the second transistor is configured to adjust at least one of a resistance value or a second capacitance value of the phase shifter in response to the second voltage. In some embodiments, the phase shifter further comprises a variable capacitance. In some embodiments, the variable capacitance includes a first gate group. In some embodiments, the first gate set is configured to receive a second voltage. In some embodiments, the variable capacitance has a variable capacitance value configured to adjust in response to the second voltage.

Another aspect of the present disclosure relates to a phase shifter circuit. In some embodiments, the phase shifter includes a first transistor and a second transistor. In some embodiments, the first transistor includes a first gate terminal configured to receive a first voltage. In some embodiments, the first transistor is configured to adjust at least one of a resistance value or a first capacitance value of the phase shifter in response to the first voltage. In some embodiments, the second transistor is coupled to the first transistor. In some embodiments, the second transistor includes a second gate terminal configured to receive a second voltage. In some embodiments, the second transistor is configured to adjust a second capacitance value of the phase shifter in response to the second voltage. In some embodiments, the second gate terminal includes a first polysilicon portion and a second polysilicon portion extending in the first direction. In some embodiments, the first and second polysilicon portions are disposed along opposite edges of active regions of the first and second transistors. In some embodiments, the first transistor and the second transistor are fin field effect transistors of a first type. In some embodiments, the first transistor further comprises a first drain terminal and a first source terminal configured as the input of the phase shifter. In some embodiments, the second transistor further comprises a second source terminal, wherein the first source terminal of the first transistor and the second source terminal of the second transistor are configured as the output terminal of the phase shifter, and the first gate terminal of the first transistor is configured to adjust the resistance value of the phase shifter in response to the first voltage. In some embodiments, the phase shifter further comprises an input configured to receive an input signal having a first phase, an output configured to output an output signal having a second phase different from the first phase, and a resistor having a first end coupled to the input of the phase shifter. In some embodiments, the first transistor further comprises a first drain terminal and a first source terminal. In some embodiments, the second transistor further comprises a second source terminal. In some embodiments, the first source terminal of the first transistor, the second source terminal of the second transistor, and the second terminal of the resistor are coupled to the output terminal of the phase shifter. In some embodiments, a first drain terminal of the first transistor and a second drain terminal of the second transistor are coupled to the reference voltage supply terminal VSS. In some embodiments, the first gate terminal of the first transistor is configured to adjust a resistance value of the phase shifter in response to the first voltage. In some embodiments, the phase shifter further comprises an input configured to receive an input signal having a first phase, an output configured to output an output signal having a second phase different from the first phase, and a resistor having a first end coupled to the input of the phase shifter. In some embodiments, the first transistor further comprises a first drain region and a first source region. In some embodiments, the second transistor further comprises a second source terminal. In some embodiments, the first source terminal of the first transistor, the second source terminal of the second transistor, and the second terminal of the resistor are coupled to the output terminal of the phase shifter. In some embodiments, the first drain terminal of the first transistor and the second drain terminal of the second transistor are electrically floating. In some embodiments, the first gate terminal of the first transistor is configured to adjust the first capacitance value of the phase shifter in response to the first voltage. In some embodiments, the first type is n-type. In some embodiments, the first type is p-type.

Yet another aspect of the present disclosure relates to a method of forming a phase shifter. In some embodiments, the method includes generating, by a processor, a layout design for a phase shifter, and manufacturing the phase shifter based on the layout design. In some embodiments, generating the layout design includes generating a first active region layout pattern corresponding to fabricating the first active region, generating a first set of gate layout patterns corresponding to fabricating the first set of gates, generating a second set of gate layout patterns corresponding to fabricating the second set of gates, and generating a set of metals above the diffusion layout pattern corresponding to fabricating the set of contacts, wherein at least one of the layout patterns is divided by a non-transitory computer readable storage medium and at least one of the operations is performed by a hardware processor. In some embodiments, the first active region layout pattern extends in a first direction and is positioned at a first level. In some embodiments, the first gate layout pattern group extends in a second direction different from the first direction, overlaps the first active region layout pattern and is positioned at a second level different from the first level. In some embodiments, each gate layout pattern of the first gate layout pattern group is separated from other gate layout patterns of the first gate layout pattern group in the first direction. In some embodiments, the second gate layout pattern group extends in a second direction, overlaps the first active region layout pattern, is positioned at a second level, and is disposed along opposite sides of the first active region layout pattern. In some embodiments, the second set of gates is part of a first transistor configured to adjust a first capacitance value of the phase shifter in response to the first voltage. In some embodiments, the metal group above the diffusion layout pattern extends in the second direction, overlaps the first active region layout pattern and is positioned at a third level different from the first level, and is disposed between the second gate layout pattern group. In some embodiments, creating the metal set over the diffusion layout pattern includes creating a first source region layout pattern corresponding to making a first source contact, creating a first drain region layout pattern corresponding to making a first drain contact, creating a second source region layout pattern corresponding to making a second source contact, creating a second drain region layout pattern corresponding to making a second drain contact, and creating a third source region layout pattern corresponding to making a third source contact. In some embodiments, the first source region layout pattern extends in the second direction, overlaps the first active region layout pattern and is positioned at the third level, and is disposed between the first gate layout pattern of the first gate layout pattern group and the first gate layout pattern of the second gate layout pattern group. In some embodiments, the first drain region layout pattern extends in the second direction, overlaps the first active region layout pattern and is positioned at the third level, and is disposed between the first gate layout pattern of the first gate layout pattern group and the second gate layout pattern of the first gate layout pattern group. In some embodiments, the second source region layout pattern extends in the second direction, overlaps the first active region layout pattern and is positioned at a third level, and is disposed between the second gate layout pattern of the first gate layout pattern group and the third gate layout pattern of the first gate layout pattern group. In some embodiments, the second gate region layout pattern extends in the second direction, overlaps the first active region layout pattern and is positioned at a third level, and is disposed between the third gate layout pattern of the first gate layout pattern group and the fourth gate layout pattern of the first gate layout pattern group. In some embodiments, the third source region layout design extends in the second direction, overlaps the first active region layout pattern and is positioned at the third level, and is disposed between the fourth gate layout pattern of the first gate layout pattern group and the second gate layout pattern of the second gate layout pattern group. In some embodiments, generating the second gate layout pattern group includes generating a first gate layout pattern corresponding to the first gate and generating a second gate layout pattern corresponding to the second gate. In some embodiments, the first gate layout pattern extends in a second direction, overlaps the first active region layout pattern and is positioned at a second level, and overlaps a first edge of the first active region layout pattern. In some embodiments, the second gate layout pattern extends in a second direction, extends in the second direction and overlaps with the first active region layout pattern, and is positioned at a second level and overlaps with a second edge of the first active region layout pattern opposite to the first edge. The first gate and the second gate are part of a first transistor. In some embodiments, generating the first gate layout pattern group includes generating a first gate layout pattern corresponding to fabricating the first gate, generating a second gate layout pattern corresponding to fabricating the second gate, generating a third gate layout pattern corresponding to fabricating the third gate, and generating a fourth gate layout pattern corresponding to fabricating the fourth gate. In some embodiments, the first gate layout pattern extends in a second direction, overlaps the first active region layout pattern, and is positioned at a second level. In some embodiments, the second gate layout pattern extends in a second direction, overlaps the first active region layout pattern, and is positioned at a second level. In some embodiments, the third gate layout pattern extends in the second direction, overlaps the first active region layout pattern, and is positioned at the second level. In some embodiments, the fourth gate layout pattern extends in the second direction, overlaps the first active region layout pattern, and is positioned at the second level. In some embodiments, the first gate, the second gate, the third gate, and the fourth gate are part of a second transistor configured to adjust a second capacitance value or a resistance value of the phase shifter in response to the second voltage. In some embodiments, each of the first, second, third, and fourth gate layout patterns is separated from each other in the first direction. In some embodiments, the second gate layout pattern is between the first gate layout pattern and the third gate layout pattern. In some embodiments, the third gate layout pattern is between the second gate layout pattern and the fourth gate layout pattern.

The foregoing outlines features of some embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.