阅读说明：本技术 具有分层电极的磁性存储器器件和制造方法
(Magnetic memory device with layered electrodes and method of manufacture
) 是由 J.布罗克曼
C.普尔斯
S.吴
C.韦甘德
T.拉曼
D.奥埃莱特
A.史密斯
P. 于 2019-05-29 设计创作，主要内容包括：公开了具有分层电极的磁性存储器器件和制造方法。一种存储器器件制造方法,所述存储器器件包括第一电极,所述第一电极具有包括钛和氮的第一导电层,以及在第一导电层上的包括钽和氮的第二导电层。所述存储器器件此外在第一电极上包括磁性隧道结(MTJ)。在一些实施例中,第一导电层的邻近于与第二导电层的界面的至少一部分包括氧。(Magnetic memory devices having layered electrodes and methods of manufacture are disclosed. A memory device manufacturing method includes a first electrode having a first conductive layer including titanium and nitrogen, and a second conductive layer including tantalum and nitrogen over the first conductive layer. The memory device further includes a Magnetic Tunnel Junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer adjacent to the interface with the second conductive layer comprises oxygen.)
1. A memory device, comprising:
a first electrode, the first electrode comprising:
a first conductive layer comprising titanium and nitrogen; and
a second conductive layer over the first conductive layer, wherein the second conductive layer comprises tantalum and nitrogen;
a second electrode; and
a Magnetic Tunnel Junction (MTJ) between first and second electrodes, the MTJ comprising:
a fixed magnet;
a free magnet; and
a tunnel barrier between the fixed and free magnets.
2. The memory device of claim 1, wherein at least a portion of the first conductive layer adjacent to an interface with the second conductive layer further comprises oxygen.
3. The memory device of any of claims 1-2, wherein at least a portion of the second conductive layer adjacent to an interface with the MTJ layer further comprises oxygen.
4. The memory device of any of claims 1-3, wherein the first conductive layer has a multi-directional cubic crystal lattice texture and a columnar grain structure.
5. The memory device of any one of claims 1-4, wherein a plurality of columnar grain structures across a width of the first conductive layer have substantially coplanar uppermost surfaces.
6. The memory device of any of claims 1-5, wherein the first conductive layer has a first sidewall and an opposing second sidewall separated by a first width, the second conductive layer has a third sidewall and an opposing fourth sidewall separated by a second width, wherein the first sidewall extends laterally beyond the third sidewall and the second sidewall extends laterally beyond the fourth sidewall.
7. The memory device of any of claims 1-6, wherein the first conductive layer has a thickness between 10nm and 30nm, and the second conductive layer has a thickness between 1nm and 5 nm.
8. The memory device of any of claims 1-7, wherein the second conductive layer is on a first portion of the first conductive layer, and the memory device further comprises an encapsulation layer on a second portion of the first conductive layer adjacent a sidewall of the second conductive layer and adjacent a sidewall of the MTJ.
9. The memory device of any of claims 1-8, wherein an encapsulation layer is on the second electrode and over an interface between the second electrode and the MTJ.
10. The memory device of any of claims 1-9, further comprising a third conductive layer below the first conductive layer, wherein the third conductive layer has a width greater than the first width.
11. An integrated circuit structure, comprising:
a first zone, the first zone comprising:
a transistor;
a first conductive interconnect coupled with a terminal of the transistor; and
an etch stop layer over the first conductive interconnect;
a second region adjacent to the first region, the second region comprising:
a second conductive interconnect;
an etch stop layer over the second conductive interconnect;
a conductive cap on the second conductive interconnect adjacent the etch stop layer; and
a first electrode on the conductive cap, the first electrode comprising:
a first conductive layer comprising titanium and nitrogen; and
a second conductive layer over the first conductive layer, wherein the second conductive layer comprises tantalum and nitrogen;
a second electrode; and
a Magnetic Tunnel Junction (MTJ) between first and second electrodes, the MTJ comprising:
a fixed magnet;
a free magnet; and
a tunnel barrier between the fixed and free magnets.
12. The integrated circuit structure of claim 11, wherein the etch stop layer is continuous between the first and second regions.
13. The integrated circuit structure of any of claims 11-12, further comprising a third conductive interconnect on the first conductive interconnect, wherein a portion of the third conductive is adjacent to the etch stop layer.
14. The integrated circuit structure of any of claims 11-13, wherein the first conductive layer has a multi-oriented cubic crystal lattice texture and a columnar grain structure, and wherein the plurality of columnar grain structures have substantially coplanar uppermost surfaces.
15. A method for fabricating a Magnetic Tunnel Junction (MTJ) device, the method comprising:
forming a first conductive layer comprising titanium and nitrogen over the first conductive interconnect structure;
forming a second conductive layer including tantalum and nitrogen over the first conductive layer;
forming a material layer stack of the MTJ device on the second conductive layer;
etching the material layer stack to form an MTJ device;
etching the second conductive layer, wherein the etching does not remove the first conductive layer; and is
The first conductive layer is etched.
16. The method of claim 15, wherein forming the first conductive layer comprises planarizing an upper portion of the first conductive layer, and wherein forming the second conductive layer introduces oxygen proximate to an interface between the first conductive layer and the second conductive layer.
17. The method of any of claims 15-16, wherein after etching the second conductive layer, the method further comprises forming an encapsulation layer on sidewalls and on an uppermost surface of the MTJ device, and on the first conductive layer.
18. The method according to any of claims 15-17, further comprising:
forming a mask on a sidewall of the MTJ device and over a portion of the encapsulation layer on the uppermost surface;
etching a portion of the encapsulation layer; and
the package is used as a mask and the first conductive layer is etched.
19. The method of any of claims 15-18, wherein etching removes the first conductive layer and the encapsulation over the second conductive interconnect structure.
Background
Feature size reduction has been an important focus for industrial scale semiconductor process development over the past decades. Scaling to smaller sizes enables higher densities of functional elements per chip, smaller chips, and also reduced costs. However, as the industry approaches the physical limits of traditional scaling, it is becoming increasingly important to find non-traditional types of devices that can provide new functionality. One such example is a perpendicular Magnetic Random Access Memory (MRAM) device based on a Magnetic Tunnel Junction (MTJ).
Embedded vertical MRAM can provide improved energy and computational efficiency, as well as memory non-volatility. However, assembling a high-yield MRAM array that is fully integrated with surrounding logic circuitry is a difficult technical challenge.
Drawings
The materials described herein are illustrated by way of example, and not by way of limitation, in the figures. For simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Moreover, for clarity of discussion, various physical features may be represented in their simplified "ideal" forms and geometries, but nonetheless it will be understood that an actual implementation may only approximate the ideal illustrated. For example, the intersection of smooth surfaces and squares can be drawn regardless of the limited roughness, corner rounding, and imperfect angular intersection characteristics of structures formed by nano-fabrication techniques. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.
Fig. 1A illustrates a cross-sectional view of a memory device in accordance with an embodiment of the present disclosure.
Fig. 1B illustrates a cross-sectional view depicting a magnetization direction in a free magnet that is anti-parallel to a magnetization direction in a fixed magnet, in accordance with an embodiment of the present disclosure.
Fig. 1C illustrates a cross-sectional view depicting a magnetization direction in a free magnet that is parallel to a magnetization direction in a fixed magnet, in accordance with an embodiment of the present disclosure.
Fig. 2 illustrates a cross-sectional view of a memory device coupled with a transistor in a memory region and a logic transistor coupled with a plurality of conductive interconnects in a logic region, in accordance with an embodiment of the present disclosure.
Fig. 3A illustrates a cross-sectional view of: a first conductive interconnect adjacent the dielectric layer in the memory region, and a second conductive interconnect adjacent the dielectric layer in the second substrate region, and an etch stop layer over the first and second conductive interconnects.
Figure 3B illustrates a cross-sectional view in the structure of figure 3A after an opening is formed in the etch stop layer over the first conductive interconnect in the memory region.
Fig. 3C illustrates a cross-sectional view of the structure in fig. 3B after a conductive capping layer is formed in the opening over the first conductive interconnect.
Figure 3D illustrates the structure of figure 3C after planarization from the conductive capping layer over the etch stop layer and formation of a conductive cap over the first conductive interconnect.
Figure 3E illustrates the structure of figure 3D after forming a conductive layer over the conductive cap and over the etch stop layer.
Figure 3F illustrates the structure of figure 3E after planarization of the conductive layer in the memory and in the second region.
Figure 3G illustrates the structure of figure 3H after forming a second conductive tantalum-and-nitrogen-containing layer on the planarized surface of the first conductive titanium-and-nitrogen-containing layer.
FIG. 3H illustrates the structure of FIG. 3G after formation of a stack of MTJ material layers over the substrate.
Fig. 3I illustrates the structure of fig. 3H after a photolithographic mask is formed to define the location for the MTJ in the memory region.
Fig. 3J illustrates the structure of fig. 3I after patterning and etching of the MTJ material layer stack.
Fig. 3K illustrates the structure of fig. 3J after an encapsulation layer is formed over the MTJ and on the first conductive layer.
Figure 3L illustrates the structure of figure 3K after etching a conductive layer into the patterned conductive layer and removing the sacrificial hardmask material used to perform the patterning.
Figure 3M illustrates the structure of figure 3L after deposition of a dielectric material on the etch stop layer, followed by formation of a mask.
Figure 3N illustrates the structure of figure 3M after a process for etching dielectric material to form an opening in the dielectric material in a second region over the second conductive interconnect.
Figure 3O illustrates the structure of figure 3N after a process of forming a third conductive interconnect in the opening in the dielectric material in the second region.
Fig. 4 illustrates a memory device coupled to a transistor.
Fig. 5 illustrates a computing device in accordance with an embodiment of the present disclosure.
Fig. 6 illustrates an Integrated Circuit (IC) structure including one or more embodiments of the present disclosure.
Detailed Description
Magnetic tunnel junction (MTF) based memory devices with layered electrodes and methods of fabricating the same are described. The disclosure described herein presents new solutions to the following specific challenges: magnetic Random Access Memory (MRAM) arrays including magnetic tunnel junctions are integrated into surrounding logic circuitry by using layered bottom electrode contact structures that facilitate desirable device yield and performance characteristics, while still allowing for clean removal of the layered bottom electrode contact structures from selected regions of a semiconductor wafer. In the following description, numerous specific details are set forth, such as novel structural arrangements and detailed manufacturing methods, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memories, are described in less detail so as not to unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Certain terminology may also be used in the following description for the purpose of reference only, and thus is not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," and "side" describe the orientation and/or position of portions of the assembly within a consistent but arbitrary frame of reference as may be ascertained by reference to the text and associated drawings describing the assembly in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.
In some instances, well-known methods and apparatus are shown in block diagram form, rather than in detail, in the following description in order to avoid obscuring the present disclosure. Reference throughout this specification to "one embodiment" or "an embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrase "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment wherever particular features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.
As used in the specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, and/or electrical contact with each other. "coupled" may be used to indicate that two or more elements are in physical or electrical contact with each other, either directly or indirectly (with other intervening elements between them), and/or that two or more elements are in cooperation or interaction with each other (e.g., as an effect relationship in origin).
The terms "above," "below," "between," and "on" as used herein refer to the relative positioning of one component or material with respect to other components or materials, where such physical relationships are significant. For example, in the context of materials, a material or materials disposed above or below another material may be in direct contact, or may have one or more intervening materials. Further, a material disposed between two materials may directly contact the two layers, or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with the second material/material. Similar distinctions will be made in the context of assembly of components. As used throughout this specification and in the claims, a list of items linked by the term "at least one of" or "one or more of" may mean any combination of the listed items.
As used throughout this specification and in the claims, a list of items linked by the term "at least one of" or "one or more of" may mean any combination of the listed items.
The terms "substantially equal," "about equal," and "approximately equal" mean that there is only incidental variation between the two so described, unless otherwise specified in the explicit context of their use. In the art, such variations are typically no more than +/-10% of a predetermined target value.
The MTJ device acts as a memory device, wherein the resistance of the MTJ device switches between a high resistance state and a low resistance state. The resistance state of the MTJ device is defined by the relative orientation of magnetization between the free magnet and the fixed magnet separated by the tunnel barrier. When the magnetizations of the free magnet and the fixed magnet have orientations in the same direction, the MTJ device is said to be in a low resistance state. In contrast, when the magnetizations of the free magnet and the fixed magnet each have an orientation in a direction opposite to each other, the MTJ device is said to be in a high-resistance state.
As MTJ devices scale, the need for smaller memory elements to fit the scaled cell size has driven the industry in the perpendicular MTJ (pmtj) direction. pMTJ-based memory devices have a fixed magnet and a free magnet that each have perpendicular magnetic anisotropy with respect to a plane of the free magnet. Resistance switching is induced in a pMTJ device by: a critical amount of spin-polarized current is passed through the pMTJ device such that the magnetization orientation of the free magnet is affected to align with the magnetization of the fixed magnet. The action that affects the magnetization is caused by a phenomenon known as spin torque transfer, in which the torque from the spin-polarized current is imparted to the magnetization of the free magnet. By changing the direction of the current, the magnetization direction in the free magnet can be reversed relative to the magnetization direction in the fixed magnet. Since the free magnet does not require a constant source of spin-polarized current to maintain the magnetization direction, the resistance state of the pMTJ device is preserved even when no current is flowing through the pMTJ device. For this reason, MTJ devices belong to a class of memories known as non-volatile memories.
Embodiments of the present disclosure describe layered bottom electrode contact structures and fabrication methods that simultaneously address several technical challenges necessary for fabricating arrays of pMTJ devices. One such challenge is to select a bottom electrode contact structure and fabrication method that can facilitate the deposition of a fixed magnet with strong FCC <111> crystal structure and strong perpendicular magnetic anisotropy. This is desirable for achieving a high Tunneling Magnetoresistance Ratio (TMR) in the pMTJ devices in the array, and for electrically switching pMTJ devices with low switching voltages and with low Write Error Rates (WER) in high efficiency.
Another challenge is to select a bottom electrode contact structure and fabrication method that reduces the amount of conductive residue material on the sides of the pMTJ device. This is necessary to minimize device sidewall shorting and achieve high pMTJ device array yield. Another challenge is to select a bottom electrode contact structure and fabrication method that allows for clean and damage free removal of the bottom electrode contact structure from the non-memory area of the wafer where the bottom electrode contact structure is not desired and from the memory area to insulate the pMTJ device. It is desirable to remove the bottom electrode contact structure without damage, in order to maintain high yield of existing logic circuits into which the pMTJ device array is being inserted.
In an embodiment of the present disclosure, a memory device includes a layered first electrode structure having a first conductive layer comprising titanium and nitrogen, and a second conductive layer comprising tantalum and nitrogen over the first conductive layer. The first layer of titanium and nitrogen is a conductive material that is readily removed from the substrate by a suitable etching process, and is also a suitable material that acts as an etch stop during formation of the pMTJ device. The second layer of tantalum and nitrogen is a thin layer superior to the first layer for facilitating the subsequent deposition of a pMTJ fixed layer having strong FCC <111> crystal texture and strong perpendicular magnetic anisotropy. For practical reasons, the second layer may have a thickness substantially smaller than the thickness of the first layer. Such considerations allow for etching of the pMTJ device towards the end point when the etching of the first layer is complete. The first layer is selected to be more favorable for reducing device sidewall shorts and for ease of removal from non-memory regions of the wafer, while the second layer is more favorable for promoting a strong FCC <111> crystal structure and strong vertical anisotropy. For practical reasons, the first layer may be relatively thick to ensure that the pMTJ device is etched through its thickness. This consideration allows the pMTJ device etch to be protected from penetrating the first layer and damaging underlying CMOS interconnect layers and circuitry on the wafer in the non-memory region.
The memory device additionally includes a perpendicular magnetic tunnel junction (pMTJ) on the first electrode, where the pMTJ includes a fixed magnet, a free magnet, and a tunnel barrier between the free magnet and the fixed magnet, and a second electrode on the pMTJ. In one embodiment, the first layer may have a cubic crystal structure having a columnar grain structure and a crystalline texture. However, the second conductive layer comprising amorphous material may mask undesirable crystalline texture of the underlying first conductive layer and present a surface that is more compatible with: the bottom-most layer of the pMTJ stack is grown to have FCC <111> crystal texture and strong perpendicular magnetic anisotropy. In an embodiment, at least a portion of the first conductive layer adjacent to the interface with the second conductive layer further comprises oxygen. The presence of oxygen may occur due to the nature of the manufacturing scheme as will be described below.
Fig. 1A illustrates a cross-sectional illustration of a memory device 100 in accordance with an embodiment of the present disclosure. The memory device 100 comprises a bottom electrode 102, said bottom electrode 102 having a first conductive layer 101 comprising titanium and nitrogen, and a second conductive layer 103 comprising tantalum and nitrogen on top of the conductive layer 101. The memory device 100 further includes a Magnetic Tunnel Junction (MTJ) 104 on the bottom electrode 102. In an embodiment, the MTJ104 includes a free magnet 108, a tunnel barrier 110, and a fixed magnet 112, as depicted in generalized form in fig. 1B and 1C. The memory device 100 additionally includes a second electrode, such as a top electrode 120, on the MTJ 104.
In an embodiment, conductive layer 101 comprises a material such as TiN, wherein the TiN has a multi-directional cubic crystal lattice texture and a columnar grain structure. In one embodiment, the TiN has a <001> texture. In other examples, a wide variety of phases in each columnar grain in TiN, such as <110>, <111>, or <221>, are also possible.
In the illustrative embodiment, the plurality of columnar grain structures in the conductive layer 101 have substantially coplanar uppermost surfaces.
In some examples, at least a portion of the conductive layer 101 adjacent to the interface 105 with the second conductive layer 103 includes oxygen. Depending on the embodiment, oxygen may be transferred across width W of electrical layer 101E1Continuously extending. In one embodiment, portions of conductive layer 101 are directly adjacent to conductive layer 103, with no oxygen in between.
In an embodiment, conductive layer 103 comprises a material such as tantalum nitride, which is effective to facilitate high quality FCC of subsequent magnetic pinned layers in a pMTJ stack<111>A crystal structure and a strong perpendicular anisotropy. In some examples, at least a portion of the conductive layer 103 adjacent to the interface 107 with the lowest layer of the MTJ104 includes oxygen. Depending on the embodiment, oxygen may be transferred across width W of electrical layer 101E2Continuously extending. In some embodiments, portions of the conductive layer 103 are directly adjacent to the lowest layer of the MTJ104, with no oxygen in between. In an embodiment, the amount of oxygen in a portion of the conductive layer 103 adjacent to the interface 107 with the lowest layer of the MTJ104 is substantially less than the amount of oxygen in a portion of the conductive layer 101 adjacent to the interface with the second conductive layer 103. Such differences may be caused by the manufacturing nature of the electrodes as will be discussed further below.
In an embodiment, conductive layer 101 has a thickness greater than the thickness of conductive layer 101. The conductive layer 101 has a thickness between 10nm and 30nm, and the conductive layer 103 has a thickness between 1nm and 5 nm. The thickness between 1nm and 5nm is thick enough to mask the cubic <001> crystal texture of the underlying material. In an embodiment, when the conductive layer 103 comprises a material such as TaN, the conductive layer 101 also serves as an etch stop layer.
In the illustrative embodiment, the conductive layer 101 has a first width WE1A separated first side wall 101A and an opposite second side wall 101B, and the conductive layer 103 has a first width WE2A separated first sidewall 103A and an opposite sidewall 103B. As shown, WE2Is less than WE1And sidewall 101A extends laterally beyond sidewall 103A and sidewall 101B extends laterally beyond sidewall 103B. As illustrated, sidewalls 101A and 101B are laterally beyond sidewalls 103A and 103B, respectively, by a width WSAnd is extended. In some embodiments, the width WSIn the range of 20nm to 50 nm.
As shown, conductive layer 103 is on a first portion of conductive layer 101, and memory device 101 further includes an encapsulation layer 150 on second and third portions 101C and 101D, respectively, of first conductive layer 101. The encapsulation layer 150 has a thickness W between 10nm and 30nmEL. In the illustrative embodiment, encapsulation layer 150 has a lowermost portion on conductive layer portion 101C and on conductive layer portion 101D. The lowermost portion of the encapsulation layer 150 has a width WS。WSMay be equal to WELOr greater than WEL。
The encapsulation layer 150 is also adjacent to sidewalls 103A and 103B, adjacent to sidewalls 104A, 104B of the MTJ104, and adjacent to sidewalls of the top electrode 120. As illustrated, a portion of the encapsulation layer 150 is on the top electrode 102 and over the interface 109 between the second electrode 120 and the MTJ 104.
Memory device 100 is on conductive cap 122 under conductive layer 101. The conductive cap 122 has a width WE3. Width WE3May be greater or less than the width W of the conductive layer 101E1. In some embodiments, the conductive cap 122 has a width WE3Said width WE3Is designed to be larger than the width WE1To protect underAnd a conductive interconnect 130. The conductive cap 122 is adjacent to the etch stop layer 124. In an embodiment, the conductive cap 122 comprises a material such as tantalum, tantalum nitride, tungsten, titanium nitride, or titanium. A conductive cap 122. Etch stop layer 124 may comprise a dielectric material such as silicon nitride, silicon carbide, or carbon-doped silicon nitride.
Fig. 1B illustrates a cross-sectional view depicting the free magnet 108 of the MTJ104 having a magnetization direction (indicated by the direction of arrow 156) that is anti-parallel to the magnetization direction (indicated by the direction of arrow 154) in the solid magnet 112. When the magnetization direction 156 in the free magnet 108 is opposite (anti-parallel) to the magnetization direction 154 in the fixed magnet 112, the MTJ104 is said to be in a high resistance state.
In contrast, fig. 1C illustrates a cross-sectional view depicting the free magnet 108 of the MTJ104 having a magnetization direction (indicated by the direction of arrow 156) that is parallel to the magnetization direction (indicated by the direction of arrow 154) in the solid magnet 112. When the magnetization direction 156 in the free magnet 108 is parallel to the magnetization direction 154 in the fixed magnet 112, the MTJ104 is said to be in a low resistance state.
In an embodiment, the free magnet 108 includes a magnetic material, such as Co, Ni, Fe, or alloys of these materials. In an embodiment, the free magnet 108 includes a magnetic material, such as CoB, FeB, CoFe, and CoFeB. In an embodiment, the free magnet 108 of the MTJ104 comprises an alloy such as CoFe, CoFeB, FeB, doped with tungsten, tantalum, or molybdenum, for promoting high perpendicular anisotropy. In an embodiment, the free magnet 108 of the MTJ104 comprises an alloy such as CoFe, CoFeB, FeB, with one or more layers of tungsten, tantalum, or molybdenum to promote high perpendicular anisotropy. In an embodiment, the free magnet 108 has a thickness between 0.9nm-3.0nm for the MTJ device.
In an embodiment, the tunnel barrier 110 is composed of a material suitable for allowing electron current with a majority spin to pass through the tunnel barrier 110, while blocking, at least to some extent, electron current with a minority spin from passing through the tunnel barrier 110. Thus, the tunnel barrier 110 (or spin-filter layer)It may also be referred to as a tunneling layer for a particular spin-oriented electron current. In an embodiment, the tunnel barrier 110 includes a material such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (Al)2O3) The material of (1). In an embodiment, the tunnel barrier 110 comprising MgO has the following crystal orientation: the crystal is oriented (001) and is lattice matched to the free magnet 108 below the tunnel barrier 110 and the fixed magnet above the tunnel barrier 110. In an embodiment, the tunnel barrier 110 is MgO and has a thickness in a range of 1nm to 2 nm. In an embodiment, comprising Co100-x-yFexByIs highly lattice matched to a tunnel barrier 110 comprising MgO. Lattice matching the crystal structure of the free magnet 108 and the tunnel barrier 110 enables a ratio of high Tunneling Magnetoresistance Ratio (TMR) in the MTJ 104.
In an embodiment, the fixed magnet 112 comprises a magnetic material having a substantially perpendicular magnetization. In an embodiment, the fixed magnet 112 of the MTJ104 comprises an alloy such as CoFe, CoFeB, FeB, doped with tungsten, tantalum, or molybdenum, for facilitating high perpendicular anisotropy. In an embodiment, the free magnet 108 of the MTJ104 comprises an alloy such as CoFe, CoFeB, FeB, with one or more layers of tungsten, tantalum, or molybdenum to promote high perpendicular anisotropy. In an embodiment, the fixed magnet 112 has a thickness between 1nm-3 nm. In further embodiments, there are additional layers of highly anisotropic Co/Pt or Co/Ni or Co/Pd multilayers and/or alloys to provide further perpendicular anisotropy enhancement to alloys such as CoFe, CoFeB or FeB. In further embodiments, thin layers of ruthenium and iridium may be used to antiferromagnetically couple Co/Pt or Co/Ni or Co/Pd multilayers and/or alloys for forming a synthetic antiferromagnetic structure that minimizes stray magnetic fields impinging on the free layer 108.
It is to be appreciated that many additional layers of magnetic and non-magnetic inserts are typically used at various locations inside the generalized pMTJ stack for numerous purposes, such as blocking diffusion, enhancing film crystallinity and texture, and ferromagnetically or antiferromagnetically coupling the two magnetic layers together.
Referring again to FIG. 1A, in an embodiment, the top electrode 120 comprises a material such as Ta or W or TiN. In an embodiment, the top electrode 120 has a thickness between 5nm-70 nm.
In an embodiment, the conductive interconnect 130 includes a barrier layer 130, such as tantalum or tantalum nitride, and a fill metal 130B, such as copper, tungsten.
In an embodiment, substrate 160 comprises a suitable semiconductor material such as, but not limited to, monocrystalline silicon, polycrystalline silicon, and silicon-on-insulator (SOI). In another embodiment, substrate 160 comprises other semiconductor materials, such as germanium, silicon germanium, or suitable III-N or III-V compounds. In the illustrative embodiment, the substrate 160 includes a layer of dielectric material over a semiconductor material such as, but not limited to, monocrystalline silicon, polycrystalline silicon, silicon germanium, or a suitable group III-N or group III-V compound. Logic devices such as MOSFET transistors and access transistors may be formed on substrate 160. Logic devices such as access transistors may be integrated with memory devices such as SOT memory devices to form embedded memories. Embedded memories including magnetic memory devices and logic MOSFET transistors may be combined to form functional integrated circuits, such as system-on-a-chip.
Fig. 2 is a cross-sectional illustration of an integrated circuit structure including a first region 200 and a second region 250 adjacent to the first region 200. In an embodiment, the first region 200 includes a plurality of transistors and the second region 250 includes a plurality of memory devices, wherein each memory device is coupled with a single transistor. In the illustrative embodiment, the first region 200 includes a transistor 210, and a conductive interconnect 230 coupled to one terminal of the transistor 210. Other conductive interconnects (not shown) may be coupled with other terminals of transistor 212. Transistor 210 and conductive layer 230 are surrounded by dielectric material 140. The etch stop layer 124 is over the conductive interconnect 230 and the dielectric material 140.
The second region includes the memory device 100 over the conductive interconnect 130. As shown, conductive interconnect 130 is electrically coupled with one terminal of transistor 212. In an embodiment, conductive interconnect 130 is coupled with a drain terminal of transistor 212. Other conductive interconnects (not shown) may be coupled with other remaining terminals, such as the source and gate terminals of transistor 210. The second region further includes an etch stop layer 124 over the conductive interconnect 130 and over the dielectric material 140. The etch stop layer 124 is continuous between the first region 200 and the second region 250. In an embodiment, the dielectric material 140 is also continuous between the first region 200 and the second region 250. In one embodiment, each of the conductive interconnects 230 and 130 has a coplanar or substantially coplanar uppermost portion. In one such embodiment, the etch stop layer 124 is on the same plane in the first and second regions 200 and 250, respectively, as shown.
A conductive cap 122 is on the second conductive interconnect 130 adjacent the etch stop layer 124. A conductive cap, such as conductive cap 122, may or may not be present over conductive interconnect 230 in first region 200.
The first region 200 further comprises a conductive interconnect 240 on the conductive interconnect 230 for forming an interconnect metallization structure. In some embodiments, the conductive interconnect 240 may have a height substantially equal to the combined height of the electrode structure 102, the MTJ104, and the top electrode 120, and the encapsulation layer 150, as shown in fig. 2. In the illustrative embodiment, a portion of the conductive interconnect 240 is adjacent to the etch stop layer 124 over the conductive interconnect 230. The conductive interconnect 240 is surrounded by a dielectric material 220, as shown. Dielectric material 220 may extend continuously between first and second regions 200 and 250, respectively, as illustrated.
The first region 200 may further comprise a further conductive interconnect 245 on the conductive interconnect 240. The memory device 100 may further include a conductive interconnect 270 coupled with the top electrode 120 through the encapsulation layer 150, as shown.
In an embodiment, conductive interconnects 230, 240, 245, and 270 are the same or substantially the same as conductive interconnect 130. In one embodiment, conductive interconnect 230 includes barrier layer 230A and fill metal 230B, conductive interconnect 240 includes barrier layer 240A and fill metal 240B, conductive interconnect 245 includes barrier layer 245A and fill metal 245B, and conductive interconnect 270 includes barrier layer 270A and fill metal 270B, as shown.
Fig. 3A-3O illustrate cross-sectional views representing various operations in a method for fabricating a memory device in the first region 350 and a conductive interconnect adjacent to the memory device in the second region 300.
Fig. 3A illustrates the conductive interconnect 130 surrounded by dielectric material 140 formed over the substrate 160 in the memory region 350, and the conductive interconnect 230 in the second region 300. Fig. 3A further illustrates an etch stop layer 124 over the conductive interconnects 130, 230 and over the dielectric material 140, which extends continuously between the memory region and the second region. In an embodiment, the second region may be one of: in which integrated circuit components such as transistors may be fabricated. In some embodiments, conductive interconnects 130 and 230 are formed in dielectric material 140 extending across both regions 300 and 350 by a damascene (damascone) or dual damascene process. In an embodiment, the conductive interconnects 130, 230 include barrier layers 130A, 230A, respectively, and fill metals 130B, 230B. In some examples, the barrier layers 130A, 230A include a material such as tantalum nitride or ruthenium. In some examples, the fill metals 130B and 230B include a material such as copper or tungsten. In other examples, when materials other than copper are utilized, conductive interconnects 130 and 230 are fabricated using a subtractive etch process. In an embodiment, the dielectric layer 140 includes a material such as, but not limited to, silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. The dielectric layer 140 may have an uppermost surface that is substantially coplanar with the uppermost surfaces of the conductive interconnects 130 and 230, as illustrated. In some embodiments, conductive interconnects 130 and 230 are each electrically connected to a separate circuit element, such as a transistor (not shown).
Figure 3B illustrates a cross-sectional view of the structure in figure 3A after an opening is formed in etch stop layer 124 over conductive interconnect 130 in memory region 350. In an embodiment, a mask (not shown) is formed over the etch stop layer 124. The mask may be lithographically patterned. In an embodiment, the etch stop layer 124 is patterned by using a mask for forming the opening 302. As an example of a patterning process, the etch stop layer 124 may be selectively etched to the conductive interconnect 130 and the dielectric material 140 by a plasma etch process. When the opening 302 has a width that is narrower than the width of the conductive interconnect 130, then the etching process does not expose the dielectric material 140. In the illustrative embodiment, the opening 302 has a width that is wider than the conductive interconnect 130. The opening 302 defines the width of the conductive cap that will be formed in a subsequent operation. In some embodiments, it is advantageous to have an opening that is wider than the width of the conductive interconnect 130 so that the conductive cap to be subsequently formed can act as an etch stop during downstream processing operations.
Fig. 3C illustrates a cross-sectional view of the structure in fig. 3B after forming a conductive capping layer 306 in the opening 302. In some examples, the conductive capping layer 306 is deposited by using a physical vapor deposition process or a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. In an embodiment, a conductive capping layer 306 is blanket deposited in the opening 302 over the conductive interconnect 130 and over portions of the dielectric material 140, as shown. The conductive capping layer 306 may comprise the same or substantially the same material as the conductive cap 122.
Figure 3D illustrates the structure of figure 3C after the conductive capping layer 306 has been planarized in the memory and in the second region from above the etch stop layer 124. In an embodiment, the planarization process includes a chemical mechanical polishing process. In one example, the polishing process removes the conductive capping layer 306 from over the etch stop layer 124 and leaves a portion of the conductive capping layer 306 in the opening 302 to form the conductive cap 122 over the conductive interconnect 130.
Fig. 3E illustrates the structure of fig. 3D after a conductive layer 304 is formed over the conductive cap 122 and over the etch stop layer 124. In an embodiment, conductive layer 304 comprises a material such as TiN having a multi-directional cubic crystal lattice texture and a columnar grain structure. An enhanced cross-sectional view of the region inside the dashed line 306 illustrates columnar grains 304A, 304B in the conductive layer 304 comprising a material such as TiN. The respective uppermost surfaces 304C and 304D of each columnar grain 304A, 304B are not smooth or coplanar, as deposited. In some examples, the conductive layer 304 is deposited by using a physical vapor deposition process or a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.
Fig. 3F illustrates the structure of fig. 3E after planarization of conductive layer 304. In an embodiment, the planarization process includes a chemical mechanical polishing process. In one example, the polishing process removes the uppermost portion of the conductive layer 304. In an embodiment, conductive layer 304 comprises TiN. In one such embodiment, the enhanced cross-sectional view of the region inside the dashed line 303 illustrates the co-planar or substantially co-planar uppermost surfaces 304C and 304D of the columnar grains 304A, 304B, respectively, after planarization. In some embodiments, after the planarization process, the uppermost surface of the conductive layer 304 has a non-uniformity of less than 1 nm. When removed from the vacuum environment after the planarization process, the uppermost surface of the conductive layer 304 may become oxidized due to the presence of the atmospheric oxygen 307.
Fig. 3G illustrates the structure of fig. 3H after forming a conductive layer 305 on the planarized surface of conductive layer 304. In an embodiment, the uppermost surface of the conductive layer 304 is exposed to a pre-deposition clean-up process to remove any oxidized portions of the conductive layer 304. In some embodiments, the oxidized portion of the conductive layer 304 remains. In the illustrative embodiment, the conductive layer 305 comprises a material such as TaN. In one such embodiment, the TaN conductive layer 305 is deposited to a thickness between 1nm and 5nm to mask the adverse crystal texture of the underlying TiN layer. In an embodiment, conductive layer 305 is exposed to a non-vacuum environment. In some such embodiments, the uppermost surface of conductive layer 305 may have portions that become oxidized due to the presence of ambient oxygen 309. In other embodiments, if the MTJ material layer stack is deposited in situ after forming conductive layer 305, the uppermost portion of conductive layer 305 may not become oxidized.
Figure 3H illustrates the structure of figure 3G after forming a pMTJ material layer stack 360 over the substrate 160. In an embodiment, the MTJ material layer stack 306 includes various fixed magnetic layers, a tunnel barrier layer, and a free magnetic structure including one or more free magnetic layers. In an embodiment, the MTJ material layer stack 360 also includes various additional layers of magnetic and non-magnetic interposers, which are typically used at various locations inside the MTJ material layer stack 360 for numerous purposes, such as blocking diffusion, enhancing film crystallinity and texture, and ferromagnetically or antiferromagnetically coupling the two magnetic layers together.
Fig. 3I illustrates the structure of fig. 3H after a mask 362 is formed over the conductive layer 320 in the memory region 350. In some embodiments, mask 362 is formed by a photolithographic process. In other embodiments, mask 362 comprises a dielectric material that has been patterned. Mask 362 defines the size of the MTJ to be subsequently formed.
FIG. 3J illustrates the structure of FIG. 3I after patterning and etching of the MTJ material layer stack 360. In an embodiment, the patterning process first includes etching the conductive layer 320 by a plasma etching process to form the top electrode 120.
In an embodiment, the plasma etching process then continues to pattern the remaining layers of the MTJ material layer stack 360 to form the MTJ 104. In one embodiment, the plasma etching process etches the layers in the MTJ material layer stack 360 to form the free magnet 108, the tunnel barrier 110, and the fixed magnet 112. The plasma etch process is then used to etch the MTJ104 to have a width W equal to that of the MTJ104MTJConductive layer 305 is etched into conductive layer 103 of substantially the same width. Forming the conductive layer 103 exposes the conductive layer 304. In the illustrative embodiment, the conductive layer 304 is used as an etch stop layer. In one embodiment, the MTJ material layer stack 360 and the conductive layer 305 are completely removed from the second region 300. In some embodiments, depending on the etch parameters, the MTJ104 may have sidewalls that become tapered during the etch process, as indicated by the dashed line 325.
Fig. 3K illustrates the structure of fig. 3J after the encapsulation layer 150 is formed. In an embodiment, the encapsulation layer 150 is blanket deposited over the conductive layer 304, over the sidewalls of the MTJ104, and over the uppermost surface and sidewalls of the top electrode 120. The encapsulation layer 150 is designed to protect the layers in the MTJ104 during subsequent processing operations. In some embodiments, encapsulation layer 150 may be conformally deposited. In other embodiments, the portion of the encapsulation layer 150 on the conductive layer 304 and on the uppermost surface of the top electrode 120 has a greater thickness than the portion on the sidewall of the MTJ104 and on the sidewall of the top electrode 120. The encapsulation layer 150 is deposited to a thickness between 10nm and 30 nm.
In some examples, the encapsulation layer 150 is deposited by using a Chemical Vapor Deposition (CVD) process or a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.
Fig. 3L illustrates the structure of fig. 3K after etching the encapsulation layer 150 and etching the conductive layer 304 to form the patterned conductive layer 101. In an embodiment, a sacrificial layer is deposited over the encapsulation layer 150 and a mask is formed over the sacrificial layer over the MTJ104 in the memory region. In an embodiment, portions of the encapsulation layer 150 and the sacrificial layer are etched to form the patterned encapsulation layer 150. In the illustrative embodiment, the laterally extending portions of the patterned encapsulation layer 150 define the width of the conductive layer 101. As shown, the conductive layer 101 is selectively etched relative to the etch stop layer 124 in the logic area 300, and in portions of the memory area 350 not masked by the patterned encapsulation layer 150. When the conductive cap 122 is larger than the MTJ 104WMTJAnd the combined width of the lowest lateral portion of the patterned encapsulation layer 150, the conductive cap 122 acts as an etch stop and protects the underlying conductive interconnect 130. After the etching process, the sacrificial layer and the mask are removed.
Fig. 3M illustrates the structure of fig. 3L after deposition of a dielectric material 340 on the patterned encapsulation layer 150 and on the etch stop layer 124, followed by formation of a mask 366. In the illustrative embodiment, a dielectric material 340 is also deposited on the exposed portions of the conductive cap 122. Dielectric material 340 comprises the same or substantially the same material as dielectric material 140 and may be blanket deposited. In some examples, dielectric material 340 is planarized after deposition to facilitate downstream photolithography processes. In one embodiment, the planarization process does not expose the patterned encapsulation layer 150 above the MTJ 104. In the second region 300, the mask 366 provides an opening 368. In the illustrative embodiment, the opening 368 in the mask 366 is substantially above the conductive interconnect 230.
Figure 3N illustrates the structure of figure 3M after a process for etching the dielectric material 340 to form openings 369 in the dielectric material 340 in the second region. In an embodiment, the etching process utilizes a plasma etching process. The plasma etch process first removes dielectric material 340 and then etches the exposed portions of etch stop layer 124 to form openings 369. In the illustrative embodiment, the plasma etch exposes the uppermost portion of the underlying conductive interconnect 230.
Figure 3O illustrates the structure of figure 3N after a process to form conductive interconnects 370 in openings 369 in the dielectric material 340 in the second region. As shown, a portion of the conductive interconnect 370 is adjacent to the etch stop layer 124 in the second region. Conductive interconnect 370 is also formed on portions of conductive interconnect 230, as shown. In an embodiment, the process for forming the conductive interconnect 370 is the same or substantially the same as the process for forming the conductive interconnect 230.
Fig. 4 illustrates memory device 100 coupled to transistor 400. In an embodiment, memory device 100 includes MTJ104 on electrode 102 described in association with fig. 1A and 2. Memory device 100 may include one or more features of memory device 100 described above in the embodiments associated with fig. 1A-1C and in fig. 2.
In an embodiment, transistor 400 has a source region 404, a drain region 406, and a gate 402. Transistor 400 further includes a gate contact 414 over gate 402 and electrically coupled to gate 402, a source contact 416 over source region 404 and electrically coupled to source region 404, and a drain contact 418 over drain region 406 and electrically coupled to drain region 406, as illustrated in fig. 6. In an illustrative embodiment, the memory device 100 includes a first electrode 102, the first electrode 102 having a first conductive layer 101, the first conductive layer 101 including titanium and nitrogen. The electrode 102 also has a second conductive layer 103, which includes tantalum and nitrogen, over the conductive layer 101. The memory device 100 further includes a Magnetic Tunnel Junction (MTJ) 104 on the electrode 102, wherein the MTJ104 includes a free magnet 108, a fixed magnet 112, and a tunnel barrier 110 between the free magnet 108 and the fixed magnet 112. The memory device 100 additionally includes a second electrode, such as a top electrode 120, on the MTJ 104.
In the illustrative embodiment, memory device 100 further includes an encapsulation layer 150 on portions of conductive layer 101. The encapsulation layer is also adjacent to the sidewall of the MTJ104 and adjacent to the sidewall of the top electrode 120. As illustrated, a portion of the encapsulation layer 150 is on the top electrode 120.
Memory device 100 is on conductive cap 122 under conductive layer 101. Memory device 100 is electrically coupled to drain contact 418 of transistor 400 through conductive cap 122. The MTJ contact 428 is on the top electrode 120 of the MTJ104 and is electrically coupled with the top electrode 120.
In an embodiment, the underlying substrate 401 represents a surface for fabricating an integrated circuit. Suitable substrates 401 include materials such as single crystal silicon, polycrystalline silicon, and silicon-on-insulator (SOI), as well as substrates formed from other semiconductor materials. In some embodiments, substrate 401 is the same or substantially the same as substrate 126. The substrate 401 may also include semiconductor materials, metals, dielectrics, dopants, and other materials typically present in semiconductor substrates.
In an embodiment, the access transistor 400 associated with the substrate 401 is a metal oxide semiconductor field effect transistor (MOSFET or simply MOS transistor) that is fabricated on the substrate 401. In various implementations of the invention, the access transistor 400 may be a planar transistor, a non-planar transistor, or a combination of both. Non-planar transistors include FinFET transistors, such as double-gate transistors and triple-gate transistors, and wrap-around or fully-around gate transistors, such as nanoribbon and nanowire transistors.
In an embodiment, the access transistor 400 of the substrate 401 includes a gate 402. In some embodiments, the gate 402 includes at least two layers, a gate dielectric layer 402A and a gate electrode 402B. The gate dielectric layer 402A may comprise one layer or a stack of layers. The one or more layers may comprise silicon oxide, silicon dioxide ((SiO)2) And/or high-k dielectric materials. The high-k dielectric material may include elements such asElement: hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric layer 402A to improve its quality when high-k materials are used.
The gate electrode 402B of the access transistor 400 of the substrate 401 is formed on the gate dielectric layer 402A and may include at least one P-type work function metal or N-type work function metal depending on whether the transistor is to be a PMOS or NMOS transistor. In some implementations, the gate electrode 402B can include a stack of two or more metal layers, where one or more of the metal layers is a workfunction metal layer and at least one of the metal layers is a conductive fill layer.
For a PMOS transistor, metals that may be used for the gate electrode 402B include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode having a workfunction between about 4.9eV and about 5.2 eV. For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode having a workfunction between about 3.9eV and about 4.2 eV.
In some implementations, the gate electrode can include a "U" shaped structure that includes a bottom portion that is substantially parallel to the substrate surface and two sidewall portions that are substantially perpendicular to the substrate top surface. In another implementation, at least one of the metal layers forming the gate electrode 402B may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may include a combination of a U-shaped structure and a planar, non-U-shaped structure. For example, the gate electrode 402B may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some implementations of the invention, a pair of sidewall spacers 410 are on opposite sides of the gate 402 that comprise the gate stack. Sidewall spacer 410 may be formed from materials such as: silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. The process for forming the sidewall spacers includes deposition and etching process operations. In alternative implementations, multiple pairs of spacers may be used, for example two, three or four pairs of sidewall spacers may be formed on opposite sides of the gate stack. As is well known in the art, a source region 404 and a drain region 406 are formed in the substrate adjacent to the gate stack of each MOS transistor. The source region 404 and the drain region 406 are typically formed by using an implant/diffusion process or an etch/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion implanted into the substrate to form the source region 104 and the drain region 406. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows an ion implantation process. In the latter process, the substrate 401 may first be etched to form recesses at the location of the source and drain regions. An epitaxial deposition process may then be performed to fill the recesses with the material used to fabricate the source region 404 and the drain region 406. In some implementations, the source region 404 and the drain region 406 may be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with a dopant, such as boron, arsenic, or phosphorous. In further embodiments, the source region 404 and the drain region 406 may be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloy may be used to form source region 404 and drain region 406. In the illustrative embodiment, the insulation 408 is adjacent to the source region 404, the drain region 406, and portions of the substrate 401.
In an embodiment, dielectric layer 420 is adjacent to source contact 416, drain contact 418, and gate contact 414. As illustrated, the etch stop layer 124 extends laterally over the dielectric layer 420 and over the gate contact 414, the drain contact 418, and the source contact 416 of the transistor 400.
In the illustrative embodiment, source metallization 424 is coupled with source contact 416, and gate metallization 426 is coupled with gate contact 414. In an embodiment, the transistor further comprises a conductive cap 430 between the source metallization structure 424 and the source contact 416, and a conductive cap 440 between the gate metallization structure 426 and the gate contact 414 coupling.
In the illustrated embodiment, the dielectric layer 450 is adjacent to the gate metallization structure 426, the source metallization structure 424, and the memory device 100.
In an embodiment, the conductive covers 430 and 440 comprise the same or substantially the same material as the conductive cover 122.
In an implementation, the source contact 416, the drain contact 418, and the gate contact 414 each comprise a multi-layer stack. In an embodiment, the multi-layer stack includes two or more different metal layers, such as Ti, Ru, or Al layers, and a conductive cap on the metal layers. The conductive cap may comprise a material such as W or Cu.
The insulating portion 408 and dielectric layers 420 and 450 may comprise any material having sufficient dielectric strength to provide electrical insulation, such as, but not limited to, silicon dioxide, silicon nitride, silicon oxynitride, carbon-doped nitride, and carbon-doped oxide.
Fig. 5 illustrates a computing device 500 in accordance with an embodiment of the disclosure. As shown, computing device 500 houses motherboard 502. Motherboard 502 may include a number of components including, but not limited to, processor 501 and at least one communication chip 505. The processor 501 is physically and electrically coupled to the motherboard 502. In some implementations, the communication chip 505 is also physically and electrically coupled to the motherboard 502. In further implementations, the communication chip 505 is part of the processor 501.
Depending on its applications, computing device 500 may include other components, which may or may not be physically and electrically coupled to motherboard 502. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset 506, an antenna, a display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a Global Positioning System (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, a Compact Disc (CD), a Digital Versatile Disc (DVD), and so forth).
The communication chip 505 enables wireless communication for communicating data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 505 may implement any of a number of wireless standards or protocols including, but not limited to: Wi-Fi (IEEE 802.6 family), WiMAX (IEEE 802.6 family), IEEE 802.10, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and beyond. The computing device 500 may include a plurality of communication chips 504 and 505. For example, the first communication chip 505 may be dedicated to shorter range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 504 may be dedicated to longer range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 501 of the computing device 500 includes an integrated circuit die packaged within the processor 501. In some embodiments, the integrated circuit die of processor 501 includes one or more memory devices, such as memory device 100, which includes MTJ104 on electrode 102 in accordance with embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 505 also includes an integrated circuit die packaged within the communication chip 505. In another embodiment, the integrated circuit die of the communication chips 504, 505 includes a memory array having memory cells that include at least one memory device, such as the memory device 100 including the MTJ104 on the electrode 102.
In various examples, one or more communication chips 504, 505 may also be physically and/or electrically coupled to motherboard 502. In further implementations, the communication chip 504 may be part of the processor 501. Depending on its applications, computing device 500 may include other components, which may or may not be physically and electrically coupled to motherboard 502. These other components may include, but are not limited to, volatile memory (e.g., DRAM) 507, 508, non-memory (e.g., ROM) 510, graphics CPU 512, flash memory, Global Positioning System (GPS) device 513, compass 514, chipset 506, antenna 515, power amplifier 509, touchscreen controller 511, touchscreen display 517, speaker 515, camera 503, and battery 518, as illustrated, as well as other components such as a digital signal processor, a cryptographic processor, an audio codec, a video codec, an accelerometer, a gyroscope, and a mass storage device (such as a hard disk drive, a Solid State Drive (SSD), a Compact Disc (CD), a Digital Versatile Disc (DVD), and so forth). In further embodiments, any of the components housed within the computing device 500 and discussed above may comprise a stand-alone integrated circuit memory die that includes one or more arrays of memory cells including one or more memory devices, such as memory device 100, that includes the MTJ104 on the electrode 102, constructed in accordance with embodiments of the present disclosure.
In various implementations, the computing device 500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, an internet of things (IOT) device, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 500 may be any other electronic device that processes data.
Fig. 6 illustrates an Integrated Circuit (IC) structure 600 including one or more embodiments of the present disclosure. An Integrated Circuit (IC) structure 600 is an intervening substrate used to bridge a first substrate 602 to a second substrate 604. The first substrate 602 may be, for example, an integrated circuit die. The second substrate 604 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the Integrated Circuit (IC) structure 600 is to spread connections to a wider pitch or to reroute connections to different connections. For example, an Integrated Circuit (IC) structure 600 may couple an integrated circuit die to a Ball Grid Array (BGA) 607, which BGA 607 may then be coupled to a second substrate 604. In some embodiments, the first and second substrates 602/604 are attached to opposite sides of an Integrated Circuit (IC) structure 600. In other embodiments, the first and second substrates 602/604 are attached to the same side of the Integrated Circuit (IC) structure 600. And in further embodiments, three or more substrates are interconnected by an Integrated Circuit (IC) structure 600.
The Integrated Circuit (IC) structure 600 may be formed from an epoxy, a fiberglass reinforced epoxy, a ceramic material, or a polymeric material, such as polyimide. In further implementations, the Integrated Circuit (IC) structure may be formed of alternative rigid or flexible materials that may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials.
An Integrated Circuit (IC) structure may include metal interconnects 608 and vias 610, including but not limited to Through Silicon Vias (TSVs) 610. The Integrated Circuit (IC) structure 600 may further include embedded devices 614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, device structures including the above-described transistors, a transistor 400 coupled with at least one memory device, such as memory device 100, including MTJ104 on electrode 102, wherein the electrode includes conductive layer 101 and conductive layer 103 on conductive layer 101, and further wherein at least a portion of conductive layer 101 adjacent to conductive layer 103 includes, for example, oxygen. The Integrated Circuit (IC) structure 600 may further include embedded devices 614, such as one or more resistive random access devices, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as Radio Frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on Integrated Circuit (IC) structure 600. In accordance with embodiments of the present disclosure, the apparatus or processes disclosed herein may be used in the fabrication of an Integrated Circuit (IC) structure 600.
Accordingly, one or more embodiments of the present disclosure generally relate to the fabrication of embedded microelectronic memories. Microelectronic memories may be non-volatile, wherein the memory may retain stored information even when not powered. One or more embodiments of the present disclosure relate to the fabrication of memory devices, such as memory device 100. The memory device 100 may be used in embedded non-volatile memory applications.
Thus, embodiments of the present disclosure include magnetic memory devices having layered electrodes, and methods for fabricating the devices.
Particular embodiments are described herein with respect to a non-volatile memory device that includes a magnetic tunnel junction. It will be appreciated that the embodiments described herein may also be applicable to other non-volatile memory devices. Such non-volatile memory devices may include, but are not limited to, Magnetic Random Access Memory (MRAM) devices, Spin Torque Transfer Memory (STTM) devices, such as in-plane STTM or perpendicular STTM devices.
In a first example, a memory device includes a first electrode including: a first conductive layer comprising titanium and nitrogen, and a second conductive layer over the first conductive layer, wherein the second conductive layer comprises tantalum and nitrogen. The memory device further includes a second electrode and a Magnetic Tunnel Junction (MTJ) between the first and second electrodes, wherein the MTJ includes a fixed magnet, a free magnet, and a tunnel barrier between the fixed and free magnets.
In a second example, for any of the first examples, at least a portion of the first conductive layer adjacent to an interface with the second conductive layer further comprises oxygen.
In a third example, for any of the first through second examples, at least a portion of the second conductive layer adjacent to an interface with the MTJ layer further comprises oxygen.
In a fourth example, for any of the first to third examples, the first conductive layer has a multi-directional cubic crystal lattice texture and a columnar grain structure.
In a fifth example, for any of the fourth examples, wherein the plurality of columnar grain structures across the width of the first conductive layer have substantially coplanar uppermost surfaces.
In a sixth example, for any of the first through fifth examples, the first conductive layer has a first sidewall and an opposing second sidewall separated by a first width, the second conductive layer has a third sidewall and an opposing fourth sidewall separated by a second width, wherein the first sidewall extends laterally beyond the third sidewall and the second sidewall extends laterally beyond the fourth sidewall.
In a seventh example, for any one of the first to sixth examples, the first conductive layer has a thickness between 10nm and 30nm, and the second conductive layer has a thickness between 1nm and 5 nm.
In an eighth example, for any of the first through seventh examples, the second conductive layer is on a first portion of the first conductive layer, and the memory device further includes an encapsulation layer on a second portion of the first conductive layer adjacent a sidewall of the second conductive layer and adjacent a sidewall of the MTJ.
In a ninth example, for any of the first through eighth examples, the encapsulation layer is on the second electrode and over an interface between the second electrode and the MTJ.
In a tenth example, for any of the first through ninth examples, the memory device further includes a third conductive layer below the first conductive layer, wherein the third conductive layer has a width greater than the first width.
In an eleventh example, an integrated circuit structure includes a first region including a transistor, a first conductive interconnect coupled with a terminal of the transistor, and an etch stop layer over the first conductive interconnect. The integrated circuit structure further includes a second region adjacent to the first region, wherein the second region includes a second conductive interconnect, an etch stop layer over the second conductive interconnect, a conductive cap on the second conductive interconnect adjacent to the etch stop layer, and a first electrode on the conductive cap, wherein the electrode structure comprises: a first conductive layer comprising titanium and nitrogen, a second conductive layer on the first conductive layer, wherein the second conductive layer comprises tantalum and nitrogen. The integrated circuit structure further includes a second electrode, and a memory device between the first and second electrodes. The memory device includes a first electrode including: a first conductive layer comprising titanium and nitrogen, and a second conductive layer over the first conductive layer, wherein the second conductive layer comprises tantalum and nitrogen. The memory device further includes a second electrode and a Magnetic Tunnel Junction (MTJ) between the first and second electrodes, wherein the MTJ includes a fixed magnet, a free magnet, and a tunnel barrier between the fixed and free magnets.
In a twelfth example, for any of the eleventh examples, the etch stop layer is continuous between the first and second regions.
In a thirteenth example, for any of the eleventh through thirteenth examples, the integrated circuit structure further includes a third conductive interconnect on the first conductive interconnect, wherein a portion of the third conductive is adjacent to the etch stop layer.
In a fourteenth example, for any of the eleventh through thirteenth examples, the first conductive layer has a multi-oriented cubic crystal lattice texture and a columnar grain structure, and wherein the plurality of columnar grain structures have substantially coplanar uppermost surfaces.
In a fifteenth example, a method for fabricating a Magnetic Tunnel Junction (MTJ) device includes: forming a first conductive layer comprising titanium and nitrogen over the first conductive interconnect structure, forming a second conductive layer comprising tantalum and nitrogen over the first conductive layer, forming a material layer stack of the MTJ device over the second conductive layer, etching the material layer stack to form the MTJ device, etching the second conductive layer, wherein the etching does not clear the first conductive layer and etches the first conductive layer.
In a sixteenth example, for any of the fifteenth examples, forming the first conductive layer includes planarizing an upper portion of the first conductive layer, and wherein forming the second conductive layer introduces oxygen proximate to an interface between the first conductive layer and the second conductive layer.
In a seventeenth example, for any of the fifteenth to sixteenth examples, after etching the second conductive layer, the method further includes forming an encapsulation layer on sidewalls and on an uppermost surface of the MTJ device and on the first conductive layer.
In an eighteenth example, for any of the seventeenth examples, the method for fabricating a Magnetic Tunnel Junction (MTJ) device further comprises forming a mask on a sidewall of the MTJ device and over a portion of the encapsulation layer on the uppermost surface, etching a portion of the encapsulation layer, and using the encapsulation as a mask and etching the first conductive layer.
In a nineteenth example, for any of the fifteenth to sixteenth examples, the etching removes the first conductive layer and the package over the second conductive interconnect structure.
