阅读说明：本技术 具有对称特性的存储器单元及其构成的阵列电路 (Memory cell with symmetrical characteristic and array circuit formed by same ) 是由 李学清 吴珏键 唐文骏 钟宏涛 古明阳 陶云松 刘勇攀 杨华中 于 2019-08-16 设计创作，主要内容包括：本发明提出一种具有对称特性的存储器单元及其构成的阵列结构,涉及存储器技术领域。所述存储器单元的电路结构包括两个晶体管、一个存储器器件、行位线、列位线、行字线和列字线,第一晶体管的栅极、漏极和源极分别与行字线、行位线和存储器器件一端相连,第二晶体管的栅极和漏极分别与列字线和行位线相连,第二晶体管的源极与存储器器件一端、第一晶体管的源极均相连,存储器器件另一端与列位线相连。所述阵列结构为多个所述存储器单元通过对应的字线与位线相连的方式组成的若干行和若干列。本发明通过电路结构的行、列对称性,能够实现逐行操作与逐列操作,并保证了操作的简便与对称性。(The invention provides a memory unit with symmetrical characteristics and an array structure formed by the same, and relates to the technical field of memories. The circuit structure of the memory unit comprises two transistors, a memory device, a row bit line, a column bit line, a row word line and a column word line, wherein a grid electrode, a drain electrode and a source electrode of the first transistor are respectively connected with the row word line, the row bit line and one end of the memory device, a grid electrode and a drain electrode of the second transistor are respectively connected with the column word line and the row bit line, a source electrode of the second transistor is connected with one end of the memory device and one end of the source electrode of the first transistor, and the other end of the memory device is connected with the column bit line. The array structure comprises a plurality of rows and a plurality of columns which are formed by connecting a plurality of memory units with bit lines through corresponding word lines. The invention can realize line-by-line operation and column-by-column operation through the line and column symmetry of the circuit structure, and ensures the simplicity and the symmetry of the operation.)

1. A memory cell having symmetric characteristics, the memory cell having a circuit structure comprising: a first transistor, a second transistor, a memory device having a first end and a second end, a row bit line, a column bit line, a row word line, and a column word line; the grid electrode of the first transistor is connected with the row word line, the drain electrode of the first transistor is connected with the row bit line, and the source electrode of the first transistor is connected with the first end of the memory device; the grid electrode of the second transistor is connected with the column word line, the drain electrode of the second transistor is connected with the row bit line, and the source electrode of the second transistor is connected with the first end of the memory device and the source electrode of the first transistor; a second terminal of the memory device is coupled to the column bit line.

2. The memory cell of claim 1, wherein the memory device has at least two different configuration characteristics, the memory cell storing data via the different configuration characteristics of the memory device; the memory device is a memristor device, a magnetic memory device, or other phase change memory device.

3. An array circuit comprising at least two memory cells as claimed in claim 1 or 2, characterized in that: each memory unit of the array circuit forms a plurality of rows and a plurality of columns in a mode of connecting a word line and a bit line; the row word lines and the row bit lines of the memory cells in the same row are connected, and the column word lines and the column bit lines of the memory cells in the same column are connected.

4. The array circuit of claim 3, wherein: when reading data stored in any memory cell in a certain row, controlling the row word line voltage of the memory cell corresponding to the row to enable the first transistor of the corresponding memory cell to be conducted; identifying data stored by the row of corresponding memory cells by measuring a change in voltage or current on the row of corresponding memory cell column bitlines;

when reading data stored in any memory cell in a certain column, controlling the column word line voltage of the memory cell corresponding to the column to enable the second transistor of the corresponding memory cell to be conducted; identifying the data stored by the column of corresponding memory cells by measuring a change in voltage or current on the row bit line of the column of corresponding memory cells;

when data stored in any memory cell in a certain row are written, the first transistor of the corresponding memory cell is conducted by controlling the row word line voltage of the memory cell corresponding to the row; by controlling the states of the row bit line and the column bit line of the corresponding memory unit in the row, the resistance state characteristics of the corresponding memory unit in the row are consistent with the data to be stored;

when data stored in any memory cell in a certain column is written, the second transistor of the corresponding memory cell is conducted by controlling the column word line voltage of the memory cell corresponding to the column; by controlling the state of the column bit line and the row bit line of the corresponding memory cell in the column, the resistance state characteristics of the corresponding memory cell in the column are consistent with the data to be stored.

Technical Field

The invention belongs to the technical field of low-power-consumption high-performance memory unit design, and particularly relates to a memory unit with symmetrical characteristics and an array circuit formed by the same.

Background

At present, memory has become a power consumption, performance bottleneck in many computing systems; as the amount of memory increases, the cost of memory access increases rapidly. To achieve lower power consumption and shorter delay, several solutions have been proposed. One important class of solutions is to improve the memory device itself by using embedded non-volatile memory (NVM) to avoid static power consumption. For example, a ferroelectric transistor (FeFET), a Memristor (RRAM), a magnetic memory, and the like are used. Such memory devices are not easily integrated with existing mainstream chip technology. The second category of emerging solutions is: a symmetric two-dimensional row-column access scheme is used to avoid unnecessary memory accesses. The symmetric access has obvious application in the aspects of databases, matrix operation, machine learning and the like; in many other applications, access may be required both row-by-row and column-by-column. For example, in matrix calculation, if an N × N matrix is stored in a conventional one-dimensional line memory, acquiring a data column will require accessing the memory N times; if column-by-column access is possible, the number of accesses can be reduced to 1.

Related symmetric memory structures may be based on a variety of volatile and non-volatile devices, and some implementations, such as a Dual-addressing Dynamic Random Access Memory (DRAM) proposed by y.chen and y.liu in Dual-addressing memory architecture for two-dimensional memory access patterns (fig. 1,in this figure, T1 and T2 are respectively a transistor, C is a capacitor, BL and WL are respectively a bit line and a word line), in order to realize column-by-column reading and writing, 1 access functional transistor T2 is added on the basis of the traditional single-tube single-capacitor (1T1C) DRAM implementation, and 1 extra word line WL is added_TAnd 1 bit line BL_T(ii) a The special requirement of the implementation scheme on the capacitor makes the scheme difficult to integrate with the existing mainstream chip technology, which becomes a big disadvantage of the scheme. Seo equals "a 45nm CMOS neural chip with available architecture for learning in networks of spiking neurons" and k.bang equals "14.6 a0.62mw ultra-low-power proportional-neural-network-face-registration processor and a CIS integrated with way-on-ha-face-detector", proposing 8T and 7T symmetric static access memory (SRAM) cells, respectively, as shown in (a), (b) of fig. 2, each cell using 8 or 7 transistors, respectively (corresponding to 8T and 7T structures, respectively), where 8T designs support both read access symmetry and write access symmetry, while 7T designs only have read symmetry; compared with a symmetric DRAM, the symmetric SRAM can be integrated with the existing mainstream chip process, but has the disadvantage of higher area cost, and at least 7 transistors are required to be used in each unit. In addition, S.George is equal to 5T/Cell based Symmetric Memory Cell proposed by symmetry 2-D-Memory Access to Multi-dimensional Data, as shown in FIG. 3. The problem with this solution is that the occupied area is still large, requiring the use of 5 transistors per cell. On the other hand, in a cross-symmetric array structure formed based on the memristor scheme, as shown in fig. 4 and 5, a memristor device is placed at each intersection position of a word line and a bit line which are crossed horizontally and vertically; when the memory is read, the resistance value stored by the memristor and the stored data represented by the resistance value are identified through the influence of the resistance value of the memristor on the voltage or the current of the word line and the bit line. The advantage of this scheme is that the area is small (i.e. density is high), but is limited by the resistance range of memristors, and the scheme drains electricity greatly and can support a smaller memory array scale.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a memory unit with symmetrical characteristics and an array circuit formed by the memory unit.

In order to achieve the purpose, the invention adopts the following technical scheme:

the invention provides a memory cell with symmetric characteristics, which is characterized in that the circuit structure of the memory cell comprises: a first transistor, a second transistor, a memory device having a first end and a second end, a row bit line, a column bit line, a row word line, and a column word line; the grid electrode of the first transistor is connected with the row word line, the drain electrode of the first transistor is connected with the row bit line, and the source electrode of the first transistor is connected with the first end of the memory device; the grid electrode of the second transistor is connected with the column word line, the drain electrode of the second transistor is connected with the row bit line, and the source electrode of the second transistor is connected with the first end of the memory device and the source electrode of the first transistor; a second terminal of the memory device is coupled to the column bit line.

Further, the memory device has at least two different configuration characteristics, and the memory cells store data through the different configuration characteristics of the memory device; the memory device is a memristor device, a magnetic memory device, or other phase change memory device.

The invention also provides an array circuit comprising at least two memory cells as described above, characterized in that: each memory unit of the array circuit forms a plurality of rows and a plurality of columns in a mode of connecting a word line and a bit line; the row word lines and the row bit lines of the memory cells in the same row are connected, and the column word lines and the column bit lines of the memory cells in the same column are connected.

Further, the following steps: when reading data stored in any memory cell in a certain row, controlling the row word line voltage of the memory cell corresponding to the row to enable the first transistor of the corresponding memory cell to be conducted; identifying data stored by the row of corresponding memory cells by measuring a change in voltage or current on the row of corresponding memory cell column bitlines;

when reading data stored in any memory cell in a certain column, controlling the column word line voltage of the memory cell corresponding to the column to enable the second transistor of the corresponding memory cell to be conducted; identifying the data stored by the column of corresponding memory cells by measuring a change in voltage or current on the row bit line of the column of corresponding memory cells;

when data stored in any memory cell in a certain row are written, the first transistor of the corresponding memory cell is conducted by controlling the row word line voltage of the memory cell corresponding to the row; by controlling the states of the row bit line and the column bit line of the corresponding memory unit in the row, the resistance state characteristics of the corresponding memory unit in the row are consistent with the data to be stored;

when data stored in any memory cell in a certain column is written, the second transistor of the corresponding memory cell is conducted by controlling the column word line voltage of the memory cell corresponding to the column; by controlling the state of the column bit line and the row bit line of the corresponding memory cell in the column, the resistance state characteristics of the corresponding memory cell in the column are consistent with the data to be stored.

The invention has the characteristics and beneficial effects that:

the invention designs a high-density and high-reliability nonvolatile memory supporting symmetric access characteristics, which can be based on an RRAM memory device and is also suitable for other memory devices such as a spin transfer torque magnetoresistive random access memory (STT-MRAM), a Phase Change Memory (PCM) and the like. Aiming at RRAM, the circuit of the invention adds two transistors and two word lines on the basis of the cross symmetrical array of the memory device positioned at the intersection point of the word lines and the bit lines as shown in figure 4, thereby relieving the problems of leakage current and array scale limitation in the RRAM cross array read-write operation while keeping the read-write of symmetrical rows and columns, and ensuring that the read-write operation of a certain row or a certain column of circuit units does not influence the normal state of other circuit units which are not desired to be changed. Compared with the existing cross symmetric array, the write-in performance of the invention has lower energy consumption and higher distinguishability, and supports larger storage scale.

Drawings

FIG. 1 is a schematic diagram of a symmetric access DRAM memory cell.

FIGS. 2 (a) and (b) are schematic diagrams of a 7T and 8T symmetric access SRAM memory cell, respectively.

FIG. 3 is a schematic diagram of a FeFET symmetric memory Cell based on 5T/Cell.

Fig. 4 is a schematic diagram of a cross-symmetric array (4 × 4) of RRAM.

FIG. 5 is a schematic flow chart of RRAM cross-symmetric array read-write operation

FIG. 6 is a circuit diagram of a memory cell of the present invention.

FIG. 7 is a schematic diagram of a memory cell read operation (e.g., RRAM row operation) according to the present invention.

FIG. 8 is a diagram of a write operation (e.g., RRAM row operation) for one write step of a memory cell according to the present invention.

FIG. 9 is a diagram of a multi-step writing operation (for example, RRAM row operation) of the memory cell of the present invention, wherein (a) is writing "1" and (b) is writing "0".

FIG. 10 is a schematic diagram of a 4 × 4 array structure of memory cells according to the present invention.

FIG. 11 (a) and (b) are the comparison of the read and write performance indicators of the present invention with other memory cell implementations, respectively.

Detailed Description

The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.