阅读说明：本技术 具有局限单元的自对准3d存储器和制造集成电路的方法 (Self-aligned 3D memory with localized cells and method of fabricating integrated circuits ) 是由 赖二琨 龙翔澜 于 2018-09-17 设计创作，主要内容包括：在交叉点阵列中的多个存储单元,在交叉点阵列中交叉点中的存储单元叠层包括串联的一开关元件、一导电势垒层、及一存储单元,及具有在对应交叉点的交叉点面积中对准的多个侧边。叠层中的存储单元包括多个局限间隔物,位于交叉点面积中。这些局限间隔物包括多个外侧表面,位在叠层的一对相反侧边上。再者,可编程电阻存储材料的一主体局限于这些间隔物的多个内侧表面之间。(A plurality of memory cells in a cross-point array, the memory cell stack in the cross-point array including a switching element, a conductive barrier layer, and a memory cell in series, and having sides aligned in the area of the cross-point corresponding to the cross-point. The memory cells in the stack include a plurality of localized spacers located in the cross-point areas. These confinement spacers include a plurality of outer side surfaces on a pair of opposite sides of the stack. Furthermore, a body of programmable resistive memory material is confined between the inside surfaces of the spacers.)

1. A memory, comprising:

a plurality of first conductors in a first conductor layer having sidewalls extending in a first direction and a plurality of second conductors in a second conductor layer having sidewalls extending in a second direction and crossing the first conductors at a plurality of intersection points having a plurality of intersection point areas defined by a plurality of widths of the first and second conductors; and

an array of a plurality of memory cell stacks disposed in the intersections between the first conductor and the second conductor, each of the memory cell stacks in a corresponding intersection in the array comprising:

a switching element, a conductive barrier layer, and a memory cell in series and having sides aligned in the cross-point area of the corresponding cross-point, the memory cell comprising a plurality of confined spacers located in the cross-point area, the confined spacers having outer surfaces on a first pair of opposing sides of the memory cell stack, and a body of programmable resistive memory material confined between the inner surfaces of the confined spacers.

2. The memory of claim 1, wherein each of the memory cell stacks further includes a confining material layer having a plurality of outer side surfaces on a second pair of opposing sides of the memory cell stack within the cross-point area of the corresponding cross-point.

3. The memory of claim 1, further comprising a layer of the programmable resistance memory material lining the second conductor in the second conductor and contacting the body of the programmable resistance memory material in the memory cell stack, and separating the body of the programmable resistance memory material and the second conductor at the corresponding intersection.

4. The memory of claim 1, wherein the confined spacer has an upper surface and the body of programmable resistive memory material contacts the second conductor at the corresponding intersection at a height that is coplanar with the upper surface of the confined spacer.

5. The memory of claim 1, wherein the programmable resistive memory material comprises a phase change material.

6. The memory as claimed in claim 1, wherein the switching element includes a bidirectional threshold switch (ovonic threshold switch).

7. The memory of claim 1, wherein the confinement spacer comprises silicon nitride.

8. The memory of claim 1, further comprising:

a plurality of third conductors in a third conductor layer, the third conductors having sidewalls extending in the first direction and crossing the second conductors at a plurality of intersection points; and

an array of a plurality of memory cell stacks disposed in the intersection between the second conductor and the third conductor.

9. A memory, comprising:

a plurality of first conductors in a first conductor layer having sidewalls extending in a first direction and a plurality of second conductors in a second conductor layer having sidewalls extending in a second direction and crossing the first conductors at a plurality of intersections; and

an array of a plurality of memory cell stacks disposed in the intersections between the first and second conductors, each of the memory cell stacks in a corresponding intersection in the array comprising:

a series of bidirectional threshold switches (ovonic threshold switches), a conductive barrier layer, and a memory cell, and having a first pair of opposing sides aligned with the sidewalls of the first conductor at the corresponding junctions, and each of the memory cell stacks further comprising a layer of insulating material on a second pair of opposing sides aligned with the sidewalls of the second conductor at the corresponding junctions, the memory cell comprising a plurality of insulating spacers on the first pair of opposing sides and a body of phase change memory material confined between the insulating spacers, the insulating spacers having outer surfaces aligned with the sidewalls of the first conductor at the corresponding junctions.

10. The memory of claim 9, further comprising a layer of the phase change memory material lining the second conductor in the second conductor and contacting the body of the phase change memory material in the memory cell stack and separating the body of the phase change memory material and the second conductor at the corresponding intersection.

11. The memory of claim 9, wherein the insulating spacers comprise silicon nitride.

12. The memory of claim 9, wherein said insulating spacers comprise silicon nitride and said layer of insulating material comprises silicon nitride.

13. The memory of claim 9, further comprising:

a plurality of third conductors in a third conductor layer, the third conductors having sidewalls extending in the first direction and crossing the second conductors at a plurality of intersection points; and

a second array of a plurality of memory cell stacks disposed in the intersection between the second conductor and the third conductor.

Technical Field

The present invention relates to integrated circuit memory technology, including programmable resistive memory material technology using a 3D cross-point structure, the programmable resistive memory material including a phase change material.

Background

Many three-dimensional (3D) memory technologies using phase change materials and other programmable resistance materials have been proposed. For example, Li et al, "Evaluation of SiO" at volume 4, phase 3 of IEEE Transactions on devices and Materials Reliability, 9/2004₂Antifuse in a 3D-OTP Memory ", described for example in Memory cell arrangementPolysilicon diodes and antifuses (antifuses). Sasago et al, entitled "Cross-Point Phase Change Memory with 4F2 cell size drive by Low-Contact-resistance Poly-Si Diode" published in the Technical paper abstracts of the Symphium on VLSI Technology digest Technical Papers, pages 24-25 of the 2009 very Large Scale Integrated Circuit workshop, describe polysilicon diodes and Phase Change elements, e.g., Memory cell arrangements. Kau et al, "a stacked Cross Point Phase Change Memory," published in the 2009 conference on international electronic components (IEDM)09-617, pages 27.1.1-27.1.4, describe a Memory pillar (Memory post) that includes an Ovonic Threshold Switch (OTS) having a Phase Change element as an access device (access device). Further, see "SELF-ALIGNED, PROGRAMMABLE PHASE CHANGE MEMORY" in U.S. Pat. No. 6,579,760 issued on 17.6.2003.

However, the difficulty of fabrication has limited the efficacy of 3D structures for programmable resistance memories, including phase change memories. For example, the cross-point structure defines the dimensions of the memory element based on the widths of the word lines and bit lines that define the cross-sectional area.

While meeting data retention (retention) and endurance requirements, it is desirable to provide memory structures for high density structures that are easier to fabricate.

Disclosure of Invention

In the embodiments described herein, the memory cell stacks in a cross-point configuration have multiple dimensions and include a switching or steering (steering) device. These dimensions are defined by the cross-point area of the word lines and bit lines. The switch or steering device is, for example, an ovonic threshold switch (ovonic threshold switch) in series with a body of programmable resistive memory material, for example, phase change material. The programmable resistive memory material in a memory cell stack in a cross-point configuration is disposed in the stack in a self-aligned, spatially-restricted manner. This space has an area smaller than the area of the intersection.

One aspect of the present technology includes a cross-point memory having a plurality of first conductors in a first patterned layer and a plurality of second conductors in a second patterned layer; and an array of stacked memory cells disposed between the first and second conductors. Each memory cell stack in the array includes a switch electrically connected in series with the programmable resistive memory material. The memory cell stack includes a switching element, a conductive barrier layer, and a memory cell in series, and has sides aligned in cross-point areas corresponding to the cross-points. The memory cell includes a plurality of localized spacers located in the cross-point area. The confinement spacer has a plurality of outer side surfaces on a pair of opposite sides of the stack. Furthermore, a body of programmable resistive memory material is confined between the inner side surfaces of the confined spacer.

In some embodiments, each memory cell stack may include a confinement material layer having a plurality of outer side surfaces on a second pair of opposite sides of the stack in the area of the intersection corresponding to the intersection.

Furthermore, in some embodiments, the programmable resistive memory material of the memory cell lines the second conductor in the second conductor, contacts the body of programmable resistive memory material in the memory cell stack, and separates the body of programmable resistive memory material and the second conductor at corresponding cross points to form a mushroom (mushroom) memory structure.

Furthermore, in some embodiments, the confined spacer has an upper surface, and the body of programmable resistive memory material contacts the second conductor at a height corresponding to the intersection point, the height being coplanar with the upper surface of the confined spacer, thereby forming a confined pillar (pilar) memory structure.

Another aspect of the present technology is a method of manufacturing an integrated circuit including a memory cell as described above.

Other features, aspects, and advantages of the present technology described herein can be understood with reference to the drawings, detailed description, and claims provided below. In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the appended drawings, in which:

drawings

FIG. 1 depicts a perspective view of an embodiment of a memory cell having a localized storage element in a cross-point array.

FIG. 2 depicts a perspective view of another embodiment of a memory cell having localized storage elements in a cross-point array.

3-5 illustrate 3D perspective views of segments of an example process of a 3D cross point memory.

FIGS. 6A-6B illustrate the X-Y layout and X-Z cross-sectional views at a next stage in an exemplary process.

FIGS. 7A-7B illustrate the X-Y layout and X-Z cross-sectional views at a next stage in an exemplary process.

FIGS. 8A-8B illustrate the X-Y layout and X-Z cross-sectional views at a next stage in an exemplary process.

FIGS. 9A-9D illustrate the X-Y layout, Y-Z cross-sectional view, and first and second X-Z cross-sectional views at a next stage in an exemplary process.

FIGS. 10A-10D illustrate the X-Y layout, Y-Z cross-sectional view, and first and second X-Z cross-sectional views at a next stage in an exemplary process.

FIGS. 11A-11D illustrate the X-Y layout, Y-Z cross-sectional view, and first and second X-Z cross-sectional views at a next stage in an exemplary process.

FIGS. 12A-12D illustrate the X-Y layout, Y-Z cross-sectional view, and first and second X-Z cross-sectional views at a next stage in an exemplary process.

FIGS. 13A-13D illustrate the X-Y layout, Y-Z cross-sectional view, and first and second X-Z cross-sectional views at a next stage in an exemplary process.

FIGS. 14A-14D illustrate the X-Y layout, Y-Z cross-sectional view, and first and second X-Z cross-sectional views at a next stage in an exemplary process.

FIGS. 15A-15E illustrate an X-Y layout, a first Y-Z cross-sectional view, a first X-Z cross-sectional view, a second Y-Z cross-sectional view, and a second X-Z cross-sectional view of a sub-assembly at a next stage in an exemplary process.

FIGS. 16A-16E illustrate an X-Y layout, a first Y-Z cross-sectional view, a first X-Z cross-sectional view, a second Y-Z cross-sectional view, and a second X-Z cross-sectional view of a sub-assembly at a next stage in an exemplary process.

Fig. 17A and 17B show Y-Z cross-sectional views, and X-Z cross-sectional views, of a stage of fabrication for an alternative process, corresponding to fig. 16B and 16C of the first process.

FIG. 18 shows a block diagram of an integrated circuit having a 3D memory array as described herein, the 3D memory array having self-aligned 3D memory with localized cells.

[ notation ] to show

101. 111, 1201: first conductor

102. 112, 1222: second conductor

103. 113: bidirectional threshold switch layer

104. 114: diffusion barrier layer

105. 106, 115, 116: confined spacer

107. 117, 280, 1246, 2280, 2281: main body

107A, 107B, 117A, 117B: knot

108: programmable resistive memory material liner

110. 120: layer of confining material

200: bottom layer

201: first conductor layer

202: switching layer

203: conductive barrier layer

204: hard mask layer

208: insulating filler

210. 211: side wall

212. 213: side edge

218. 219: outside surface

220. 245: blanket cover

228: film(s)

228a, 228 b: liner pad

229. 230, 231: insulation limiting pad

235: insulating filler material

240: groove

250. 435, 436, 437: channel

251: film liner

252: insulating filler

261. 262: limiting pad

430. 431, 432, 433, 1202, 1203, 1204, 1208, 1220, 1223, 1224, 1225, 1245, 1248: thread

1216. 1217, and (3) 1217: sidewall confined spacer line

1241. 1242: spacer wire

1247: third conductor

2202. 2203: component

2216. 2217, 2241, 2242: confined spacer

2290. 2291: phase change material

3200: 3D cross point memory array

3201: plane and column decoder

3202: word line

3203: row decoder

3204: bit line

3205. 3207: bus line

3206: square block

3208: bias arrangement supply voltage

3209: control circuit

3211: data input line

3215: data output line

3250: integrated circuit with a plurality of transistors

W1, W2: width of

Detailed Description

Detailed descriptions of various embodiments of programmable resistive memory devices and methods of fabricating these devices can be found in relation to fig. 1-18.

FIG. 1 shows a perspective view of a phase change memory cell suitable for use in a cross-point array. The first conductor 101 may be assembled as a word line and the second conductor 102 may be assembled as a bit line. The memory cell stack is disposed between the first conductor 101 and the second conductor 102 and includes a switch in series with the body 107 of phase change material. The switch includes an ovonic threshold switch layer 103 and a diffusion barrier layer 104. The stack has a first end (upper end in the drawing) and a second end (lower end in the drawing). The first end comprises a body 107 of phase change material in contact with the second conductor 102 for galvanic connection to the second conductor 102. The second terminal comprises an ovonic threshold switch layer 103 in contact with the first conductor 101 for galvanic connection to the first conductor 101.

In another example, the switch and phase change material are inverted such that the phase change material contacts first conductor 101 and ovonic threshold switch layer 103 contacts second conductor 102.

The phase change material may include a chalcogenide as a base material, such as Ga_xSb_yTe_z、Ge_xSb_yTe_z、Ga_wGe_xSb_yTe_z、Ge_wGe_xSb_yTe_z、Ag_wIn_xSb_yTe_z、Sn_wGe_xSb_yTe_z、Se_wGe_xSb_yTe_zAnd S_wGe_xSb_yTe_z. The phase change material includes a first element and a second element. The first element is exemplified by tellurium (Te). The second element is exemplified by antimony (Sb). The phase change material may have additives such as nitrogen, silicon, oxygen, silicon oxide, and silicon nitride. In one embodiment, the phase change material is Ge_xSb_yTe_zThe first element is tellurium and the second element is antimony.

The ovonic threshold switch layer 103 may include a combination of chalcogenides selected to operate with ovonic threshold switching and may include one or more elements selected from the group consisting of arsenic (As), tellurium (Te), antimony (Sb), selenium (Se), germanium (Ge), silicon (Si), oxygen (O), and nitrogen (N). In one example, the ovonic threshold switch layer 103 may have a thickness of about 10nm to about 40nm, preferably about 30 nm. Czuubatyj et al, "Thin-Film Ovonic Threshold Switch", published 2012 in Electronic Materials Letters, volume 8, phase 2, pages 157 and 167: its Operation and Application in model Integrated Circuits "describes the Application and electrical properties of film OTS. In other embodiments, other current steering devices may be used, including diodes, transistors, tunneling dielectric layers, and the like.

The diffusion barrier layer 104 comprises a material or combination of materials selected to provide sufficient adhesion between the ovonic threshold switch layer 103 and the phase change material, and to block the movement of impurities from the threshold switch and vice versa. The diffusion barrier layer 104 may comprise a conductive material having a thickness of about 3 to about 30nm, preferably about 5 nm. Suitable materials for the diffusion barrier layer 104 may include metal nitrides, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), titanium silicon nitride (TiSiN), and titanium aluminum nitride (TiAlN). In addition to metal nitrides, conductive materials may be used for the diffusion barrier layer 104, such as titanium carbide (TiC), tungsten carbide (WC), graphite (C), other forms of carbon (C), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), and titanium Tungsten (TiW).

The materials selected for the first and second conductors 101, 102 may include various metals, metal-like materials, doped semiconductors, and combinations thereof. The first conductor 102 and the second conductor 102 may be implemented using one or more material layers, such as tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), doped polysilicon, cobalt silicide (CoSi), tungsten silicide (WSi), and other materials. In one example, first conductor 101 and second conductor 102 comprise a three-layer structure comprising TiN, W, and TiN.

In the embodiment of fig. 1, the first conductor 101 has a width W1. The width W1 is defined by a patterning technique, such as photolithography, so that it is as small as possible based on the fabrication technology and operating features provided. Likewise, the second conductor 102 has a width W2. The width W2 is defined by the patterning technique so that it is as small as possible. The intersection area is defined at the intersection of the first conductor 101 and the second conductor 102. The memory cell stack is disposed in a pillar region at an intersection between the first and second conductors 101, 102, the cross-section of the intersection being defined by an intersection area (W1x W2) and an etch process aligned through the sides of the first and second conductors. Since no additional alignment techniques are used other than the etching and patterning techniques used to form the first and second conductors 101, 102, the memory cell stack may be self-aligned to the first and second conductors.

The memory cell stack includes a switching element, a conductive barrier layer, and a memory cell in series. The switching element includes an ovonic threshold switching material in an ovonic threshold switching layer 103. The conductive barrier layer comprises a barrier material in the diffusion barrier layer 104.

The memory cell includes confined spacers 105, 106 having inner and outer surfaces. The confined spacers 105, 106 have outer side surfaces aligned in the cross-point area on a first pair of opposite sides (left and right sides in the drawing) of the memory cell stack, and the body of programmable resistive memory material is confined between the inner side surfaces of the confined spacers.

The confinement spacers 105 and 106 and the body 107 of phase change material provide a confined element of programmable resistive memory material having an area of junction 107A in contact with the diffusion barrier layer 104. The area of junction 107A at the corresponding intersection is substantially less than the area of the intersection of the memory cell stack.

In alternative embodiments, additional confined spacers or additional pairs of confined spacers may also be included on the front and back sides to further reduce the confined bulk volume of the phase change material aligned in the memory cell stack.

Further, in this embodiment, the memory cell includes a landing pad on a second pair of opposing sides (on the front and back sides in the figure) of the memory cell stack. The confinement pad comprises a layer of confinement material-the confinement pad comprising only the backside of the confinement material layer 110 is shown as the front side of the confinement pad is removed for the purpose of illustrating the underlying structure. The spacer (e.g., spacer material layer 110) has an inner surface, which in this embodiment is in contact with the body of programmable resistive memory material, and an outer surface, which faces the filler material in the trench between the crossing points. The body of programmable resistive memory material is thus confined by both the confinement spacers 105, 106 and the confinement liner, such as the confinement material layer 110. The landing pads are aligned with the cross-point areas of the memory cell stack.

In this embodiment, the confinement spacers 105, 106 and the layer of confinement material 110 comprise silicon nitride. Other materials may be used depending on the process environment and other factors. Other materials include dielectrics, such as hafnium oxide (HfO)_x) Zirconium oxide (ZrO)_x) Aluminum oxide (AlO)_x)、Silicon oxynitride (SiO)_xN_y) And silicon oxide (SiO)_x). When silicon nitride (SiN) is used instead of silicon oxide (SiO)_x) Performance and reliability tests have shown superior data for use with confined phase change material memory elements.

In this embodiment, the body of phase change material 107 comprises an extension of the pad of programmable resistive memory material 108 of the same or similar material, or the body of phase change material 107 extends from the pad of programmable resistive memory material 108 of the same or similar material. A pad 108 of programmable resistance memory material of the same or similar material underlies the second conductor 102 and separates the second conductor 102 without making direct contact with the confined body 107 of programmable resistance memory material. The memory cells in the memory cell stack create a junction 107B along at least a substantial portion of the length of the second conductor 102 in contact with the second conductor 102 through a pad 108 of programmable resistive memory material. Junction 107B is larger than the area of junction 107A. As such, the memory cells in the memory cell stack in combination with the programmable resistive memory material liner 108 form a "mushroom" type memory element, while the current density in the programmable resistive memory material is greater in a localized region of the body 107 of phase change material during operation of the memory cell. An active region of phase change material may extend into the pad 108 of programmable resistive memory material in the mushroom-shaped form of the memory element. The active region of the phase change material changes the solid phase region when in operation.

FIG. 2 is a schematic diagram of an alternative embodiment utilizing a confined pillar memory cell structure. The first conductor 111 has a width W1. The width W1 is defined by a patterning technique, such as photolithography, so that it is as small as possible based on the fabrication technique provided. Likewise, the second conductor 112 has a width W2. The width W2 is defined by the patterning technique so that it is as small as possible. The intersection area is defined at the intersection of the first conductor 111 and the second conductor 112. The memory cell stack is disposed in a columnar volume at an intersection, the cross-section of which is defined by the intersection area (W1x W2), and is self-aligned as described above with reference to FIG. 1.

The memory cell stack includes a switching element, a conductive barrier layer, and a memory cell in series. The switching element includes an ovonic threshold switching material in an ovonic threshold switching layer 113. The conductive barrier layer includes a barrier material in the diffusion barrier layer 114. The memory cell has sides that are aligned with the cross-point area of the cross-point of the first conductor 111 and the second conductor 112.

The memory cell includes confinement spacers 115, 116 having inner and outer surfaces. The confined spacers 115, 116 have outer side surfaces aligned in the cross-point area on a first pair of opposite sides (left and right sides in the drawing) of the memory cell stack, and the body of programmable resistive memory material is confined between the inner side surfaces of the confined spacers.

The confinement spacers 115 and 116 and the body 117 of phase change material provide a confined element of programmable resistive memory material having a junction 117A area in contact with the diffusion barrier layer 114. The junction 117A area at the corresponding intersection is substantially less than the intersection area of the memory cell stack.

In alternative embodiments, additional localized spacers or additional pairs of localized spacers may also be included on the front and back sides, further reducing the localized body volume of phase change material aligned in the memory cell stack.

Further, in this embodiment, the memory cell includes a landing pad on a second pair of opposing sides (on the front and back sides in the figure) of the memory cell stack. The confinement pad includes a layer of confinement material-the confinement pad including only the backside of the confinement material layer 120 is shown because the front side of the confinement pad is removed for the purpose of illustrating the underlying structure. The spacer (e.g., spacer material layer 120) has an inner surface, which in this embodiment is in contact with the body of programmable resistive memory material, and an outer surface, which faces the filler material in the trench between the crossing points. The body of programmable resistive memory material is thus confined by both the confinement spacers 115, 116 and the confinement liner, such as the confinement material layer 120. The landing pads are aligned with the cross-point areas of the memory cell stack.

In this embodiment, the confinement spacers 115, 116 and the layer of confinement material 120 comprise silicon nitride. Other dielectric materials may be used as described above.

In this embodiment, the body 117 of phase change material comprises a pillar of material that creates a junction 117B with the second conductor at a height that is coplanar with the tops of the confinement spacers 115, 116. Junction 117B has a contact area that may be similar to the area of junction 117A. In this way, the memory cells in the memory cell stack form a "pillar" type of memory device. In a pillar structure, the volume of the active region may be almost the same as the volume of the phase change material.

Fig. 3 through 16E are sequence diagrams illustrating stages in an exemplary process flow for fabricating an array of memory cells, such as the memory cell array of fig. 1. Fig. 3 to 5 show 3D perspective views. The following figures sequentially include 2D layouts and cross-sectional views showing the structures in a simplified manner. Generally, the reference numbers used in the series of figures apply throughout.

Fig. 3 shows a stage in the process after the formation of the first stack of materials. The bottom layer 200 provides an insulating substrate, which may be in the form of a buried oxide or silicon nitride layer on an integrated circuit substrate, or other form of insulating base. In some embodiments, there may be circuitry underneath the bottom layer 200. The process includes depositing a first conductor layer 201 material, depositing a switching element material in a switching layer 202, depositing a conductive barrier layer 203 material, and then depositing a hard mask layer 204.

The material of the first conductive layer 201 may include a multi-layer combination of titanium nitride, tungsten, and titanium nitride as described above. Other combinations of materials may be utilized. These materials may be deposited, for example, using one or more of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD) processes.

The material of the switching layer 202 may include materials for an ovonic threshold switching element, such as those described above. In embodiments where the switching element material comprises a phase change material, for example, argon (Ar), nitrogen (N) are utilized₂) And/or helium (He) at a pressure of 1mTorr to 100mTorr, by PVD, sputtering, or magnetron sputtering, the switching layer 202 can be deposited. Alternatively, the switching layer may beFormed by CVD and ALD.

The material of the conductive barrier layer 203 may include a variety of barrier materials, selected according to the programmable resistive memory element. For a phase change memory element, a suitable barrier material may be titanium nitride. Alternative embodiments may include multiple carbon species (variations), including carbon nanotubes and graphene. Further, materials such as silicon carbide and other conductive barrier materials may be utilized.

The material of the hard mask layer 204 may comprise silicon nitride, or comprise other suitable hard mask materials selected according to the etch chemistry applied.

Fig. 4 shows a stage in the post-fabrication of patterning the material of the first stack to define a plurality of channels 435, 436, 437 between the lines 430, 431, 432, 433 of the stack (extending in the Y-direction in the figure). This first patterning step stops on the underlying bottom layer 200. The lines of each stack, for example 430, include a first conductor 1201 in the patterned first conductor layer 201, a line 1202 of switching layer 202 material, a line 1203 of conductive barrier material from the conductive barrier layer 203, and a line 1204 of hardmask material from the hardmask layer 204.

Fig. 5 shows a schematic diagram of a later stage in forming an insulating fill, for example 208, in the trenches (435, 436, 437 of fig. 4). The insulating fill may be formed by depositing silicon oxide, or other insulating fill material suitable for cross-point configurations. Other low dielectric constant (low- κ) dielectrics may also be used. Filler materials other than confining materials are preferred. In this manner, end point detection (end point detection) including RIE etching for etching the confined spacers may be helpful, resulting in a better confined spacer profile. Furthermore, the use of low- κ materials may help to reduce capacitance, allowing better operating speeds. The filling step may be performed using, for example, a spin-on process, CVD, ALD, PVD, Low Pressure Chemical Vapor Deposition (LPCVD), and High Density Plasma Chemical Vapor Deposition (HDPCVD). After the deposition of the insulating fill, a chemical mechanical polishing (cmp) step may be applied stopping on the lines 1204 of hard mask material in the hard mask layer 204, providing a smooth, planar surface. Subsequent layers are formed on this smooth, planar surface.

Fig. 6A shows a top layout view in the X-Y plane at a subsequent stage of the process, and fig. 6B shows a cross-sectional view in the X-Z plane along the line a-a shown in fig. 6A at a subsequent stage of the process. Referring to fig. 6A, a top view shows lines 1203 of conductive barrier material extending in the Y-direction, the lines 1203 of conductive barrier material being separated by lines 1208 of insulating filler material. Fig. 6B shows a cross-sectional view of the structure along line a-a shown in fig. 6A, the result of this structure etch process removing line 1204 of hardmask material. As such, a groove is formed between the lines 1208 of insulating filler material. The lines of insulating filler material 1208 have sidewalls 210, 211 self-aligned to the sides 212, 213 of the lines of first conductors 1201.

Fig. 7A shows a top layout view in the X-Y plane at a subsequent stage of the process, and fig. 7B shows a cross-sectional view in the X-Z plane along the line a-a shown in fig. 7A at a subsequent stage of the process. At this stage, sidewall spacer lines (e.g., 1216, 1217) are formed in the recesses by blanket deposition of a spacer material (silicon nitride) followed by an anisotropic etch using an etch chemistry to remove material above the planar top of the insulating fill 208 and the planar bottom of the recesses while leaving the sidewall spacers shown. The etch chemistry is selective for the localized spacer material over the filler material and the conductive barrier material. Referring to fig. 7A, a top view shows sidewall-confining spacer lines 1216, 1217 of sidewall-confining spacer material, and a line 1203 of underlying conductive barrier material exposed under the line of sidewall spacer material. Figure 7B shows a cross-sectional view of the structure along line a-a of figure 7A resulting in the formation of sidewall spacer lines 1216, 1217. The sidewall spacer lines 1216, 1217 are formed on a first pair of opposite sides of the lines and have outer side surfaces 218, 219 formed on the sides of the lines of insulating fill 208, and as such, the sidewall spacer lines 1216, 1217 are self-aligned to the recesses. Furthermore, the sidewall spacer lines 1216, 1217 may have upper surfaces that are coplanar with the upper surfaces of the lines of insulating fill 208 within practical limits of etching techniques.

Fig. 8A shows a top layout view in the X-Y plane at a subsequent stage of the process, and fig. 8B shows a cross-sectional view in the X-Z plane along the line a-a shown in fig. 8A at a subsequent stage of the process. At this stage, a blanket layer 220 of phase change material is deposited over the structure. Referring to fig. 8A, a top view illustrates blanket layer 220 over the lines formed in the previous stage. In FIG. 8B, the cross-sectional view at line A-A shows the phase change material, including a body 280 of phase change material. A body 280 of phase change material is confined between sidewall-confining spacer lines 1216, 1217. The sidewall spacer lines 1216, 1217 follow the lines between the insulating fill 208. Thus, body 280 extends from blanket layer 220 over the phase change material. During deposition of blanket layer 220, the composition of the phase change material layer may be varied to suit a particular application, such that the concentration of several elements may be varied through the depth of the structure.

FIG. 9A shows a top layout view in the X-Y plane at a subsequent stage in the process; FIG. 9B shows a cross-sectional view along the Y-Z plane of line C-C shown in FIG. 9A in a subsequent stage of the process; FIG. 9C shows a cross-sectional view in the X-Z plane along line B-B shown in FIG. 9A at a subsequent stage in the process; and FIG. 9D shows a cross-sectional view in the X-Z plane along line A-A shown in FIG. 9A at a subsequent stage in the process. At this stage, the process has included depositing a second stack of layers of materials (best seen in fig. 9D), including the material of the second conductor layer, the material of the switching element in the switching layer, the material of the conductive barrier layer, and the material of the hard mask layer. The deposited material may be the same as described above in connection with fig. 3, or may be varied to suit particular embodiments. Furthermore, the process already comprises patterning this second stack to define a channel stopping at the height of the first conductor 1201 between the lines of these stacks. These stacked lines include second conductor 1222, line 1223 of the switching layer, line 1224 of the conductive barrier layer, and line 1225 of the hard mask layer, as best seen in fig. 9B. Referring to fig. 9A, a top view shows a plurality of stacked lines overlapping a plurality of first conductors 1201 (at the bottom of the channel) extending in the Y-direction. These stacked lines extending in the X direction have lines 1225 of hard mask layers on the upper surface.

Fig. 9B is a cross-sectional view taken along line C-C of fig. 9A, showing the structure of the stacked lines 1220, 1223, 1224, 1225 and second conductor 1222 and the stack of memory cells, taken along the X-direction extending along the lines. The memory cell stack is self-aligned to the sides of the first conductor 1201, the line of phase change material 1220, and the second conductor 1222 due to the patterned etch. In the columnar volume of the intersection of the first conductor (1201) and the second conductor (1222), the memory unit stack includes elements 2202 and 2203 and a body 2280 between the phase change material between localized spacers 2216, 2217 (see fig. 9D).

Figure 9C illustrates a cross-sectional view of line B-B of figure 9A between lines of a stack depicting a trench stopping on the upper surface of the first conductor 1201. Fig. 9D illustrates that due to this etch depth, the memory cell stack (2216, 2280, 2217, 2203, 2202) is formed in the columnar volume of the intersection between the second conductor 1222 and the first conductor 1201, while the lines remain above the second conductor 1222.

FIG. 9D shows a cross-sectional view along line A-A of FIG. 9A along a line of the stack. In this cross-sectional view, a confined spacer 2216, 2217 of the memory cell is shown in a first height of the cell, and a body 2280 of phase change material is confined between the confined spacers 2216, 2217. The body 2280 is an extension of the overlying line 1220 of phase change material.

The deep etch at this stage (deep etch) may be separated into two steps using separate alignment masks to reduce the aspect ratio of the deep trench for some embodiments. A first etch may be performed before depositing the material for lines 1223, 1224, 1225 and a second etch after depositing the material for lines 1223, 1224, 1225.

FIG. 10A shows a top layout view in the X-Y plane at a subsequent stage in the process; FIG. 10B shows a cross-sectional view along the Y-Z plane of line C-C shown in FIG. 10A in a subsequent stage of the process; FIG. 10C shows a cross-sectional view in the X-Z plane along line B-B shown in FIG. 10A at a subsequent stage in the process; and FIG. 10D shows a cross-sectional view in the X-Z plane along line A-A shown in FIG. 10A at a subsequent stage in the process. Referring to fig. 10A, a top view of a blanket deposited silicon nitride film 228 over the structure shown in fig. 9A-9D is shown. FIG. 10B shows the thin film 228 lining the sides of the channel, forming insulating spacer pads 230, 229 on the sides of the line 1220 of phase change material and at the first height of the stack. Fig. 10C shows a membrane 228 lining the bottom of the channel. FIG. 10D shows the film 228 on top of the stacked lines that extend in the X direction.

FIG. 11A shows a top layout view in the X-Y plane at a subsequent stage in the process; FIG. 11B shows a cross-sectional view along the Y-Z plane of line C-C shown in FIG. 11A in a subsequent stage of the process; FIG. 11C shows a cross-sectional view along the X-Z plane along line B-B shown in FIG. 11A in a subsequent stage of processing; and FIG. 11D shows a cross-sectional view in the X-Z plane along line A-A shown in FIG. 11A at a subsequent stage in the process. At this stage, the process has included depositing an insulating filler material 235 between the lines and applying a chemical mechanical polishing step or other planarization step stopping on the upper surface of the thin film of silicon nitride 228. Referring to fig. 11A, a top view shows the lines extending in the X-direction covered by the thin film 228 of silicon nitride, with an insulating filler material 235 separating the thin film 228 of silicon nitride. Fig. 11B illustrates a structure having an insulating filler material 235 between the lines of the stack. The insulating filler material 235 has an upper surface that is coplanar with the upper surface of the film 228. Fig. 11C shows insulating filler material 235 filling the trenches between the lines. Fig. 11d shows lines extending in the X-direction in the higher level of the structure, the lines of the stack being located above the memory cell stack in the columnar volume of the intersection.

FIG. 12A shows a top layout view in the X-Y plane at a subsequent stage in the process; FIG. 12B shows a cross-sectional view along the Y-Z plane of line C-C shown in FIG. 12A in a subsequent stage of processing; FIG. 12C shows a cross-sectional view along the X-Z plane along line B-B shown in FIG. 12A in a subsequent stage of processing; and FIG. 12D shows a cross-sectional view in the X-Z plane along line A-A shown in FIG. 12A at a subsequent stage in the process. At this stage, the thin film 228 and the line 1225 of the hard mask layer on top of the patterned line are removed by a selective etch process, leaving the recess 240 on top of the stacked line. The recess 240 has sidewalls that are self-aligned to the sides of the insulating filler material 235 and, thus, have some offset self-aligned to the sides of the second conductor 1222. These offsets are determined by the thickness of the pads 228a, 228 b. The remaining portion of the thin film of silicon nitride includes the pads 228a, 228 b. The liners 228a, 228b are on the sides of the insulating filler material 235 in the channel and contact first and second opposite sides of the body 2280 of phase change memory material in the stack of memory cells in the lower height of the structure. Referring to fig. 12A, a top view shows lines 1224 of conductive barrier layers extending in the X-direction and pads 228a and 228b in the lines, as well as insulating filler material 235 between the lines. Recess 240 is created by removing line 1225 and film 228 of the hard mask layer of silicon nitride on top of the line, recess 240 best seen in fig. 12B. Fig. 12C shows that the insulating filler material 235 remains intact. The cross-sectional view depicted in fig. 12D shows line 1225 and film 228 with the hard mask layer of silicon nitride on top of the line removed.

FIG. 13A shows a top layout view in the X-Y plane at a subsequent stage in the process; FIG. 13B shows a cross-sectional view along the Y-Z plane of line C-C shown in FIG. 13A in a subsequent stage of processing; FIG. 13C shows a cross-sectional view in the X-Z plane along line B-B shown in FIG. 13A in a subsequent stage of processing; and FIG. 13D shows a cross-sectional view in the X-Z plane along line A-A shown in FIG. 13A at a subsequent stage in the process. At this stage, the process has included forming spacer lines 1241, 1242 in the recesses. Spacer lines 1241, 1242 may be formed by blanket deposition of a spacer material and then anisotropic etching using an etch chemistry to remove material above the planar top of the insulating filler material 235 and the planar bottom of the recess below the insulating filler material 235 while leaving spacer lines 1241, 1242 of sidewall spacer material, spacer lines 1241, 1242. The etch chemistry is selective for the localized spacer material over the insulating filler material and the conductive barrier material. Referring to fig. 13A, a top view depicts spacer lines 1241, 1242, and lines 1224 of conductive barrier layer exposed under the spacer lines of sidewall spacer material. Fig. 13B shows spacer lines 1241, 1242 of localised spacer material on top of the lines 1224 of the conductive barrier layer and aligned to the sides of the insulating filler material 235 in the higher height of the structure. Fig. 13C shows the insulating filler material 235 between the lines. Fig. 13D shows a cross-sectional view between the alignment spacers, and shows the top surface of the line 1224 of the conductive barrier layer exposed between the spacers.

FIG. 14A shows a top layout view in the X-Y plane at a subsequent stage in the process; FIG. 14B shows a cross-sectional view along the Y-Z plane of line C-C shown in FIG. 14A in a subsequent stage of processing; FIG. 14C shows a cross-sectional view in the X-Z plane along line B-B shown in FIG. 14A at a subsequent stage in the process; and FIG. 14D shows a cross-sectional view in the X-Z plane along line A-A shown in FIG. 14A at a subsequent stage in the process. At this stage, a blanket layer 245 of phase change material is deposited over the structure. Referring to fig. 14A, a top view shows the blanket layer 245 over the lines formed in the previous stage. In fig. 14B, the cross-sectional view at line C-C shows the blanket layer 245, including the main body 1246. The body 1246 is confined between spacer lines 1241, 1242 along a line between the insulating filler material 235. Thus, the main body 1246 extends in a line from the upper layer of the blanket layer 245. As described above, during deposition of the blanket layer 245, the composition of the phase change material may be varied to suit a particular application, such that the concentration of several elements may be varied through the depth of the structure. Fig. 14C shows blanket layer 245 over insulating filler material 235. Fig. 14D shows the blanket layer 245 having a main body 1246. The body 1246 extends on the side between the spacer lines 1241, 1242 and contacts the line 1224 of the conductive barrier layer.

FIG. 15A shows a top layout view in the X-Y plane at a subsequent stage in the process; FIG. 15B shows a cross-sectional view along the Y-Z plane of line C-C shown in FIG. 15A in a subsequent stage of processing; FIG. 15C shows a cross-sectional view in the X-Z plane along line A-A shown in FIG. 15A in a subsequent stage of processing; FIG. 15D shows a cross-sectional view in the Y-Z plane along line D-D shown in FIG. 15A in a subsequent stage of processing; and FIG. 15E shows a cross-sectional view in the X-Z plane along line B-B shown in FIG. 15A at a subsequent stage in the process. At this stage, the process has included blanket depositing a hard mask material, such as silicon nitride, and patterning the hard mask material to form lines 1248 extending in the Y-direction. The channel 250, which extends down to the second conductor 1222, divides off line 1248, thereby forming a second height of the stack of memory cells in the intersection between the third conductor 1247 and the second conductor 1222. The third conductor 1247 extends in the Y direction and the second conductor 1222 extends in the X direction. Referring to fig. 15A, the top view shows lines 1248 of hard mask material overlying lines extending in the Y-direction, the lines separated by recesses exposing the upper surface of the second conductor 122 extending in the X-direction.

Fig. 15B shows a third conductor 1247 over the memory cell stack in the first and second heights of the structure, the third conductor 1247 extending in the Y-direction. Fig. 15C, rotated 90 ° relative to fig. 15B, shows the second conductor 1222 extending in the X-direction, which is orthogonal to the third conductor 1247 and the first conductor 1201 extending in the Y-direction. Further, the memory cell stack is disposed at a first height between the first conductor 1201 and the second conductor 1222 and at a second height between the third conductor 1247 and the second conductor 1222. A body 2281 of phase change material between the confinement spacers 2241, 2242 extends from the third conductor 1247 in the columnar volume at an intersection point and has sides aligned with the sides of the third conductor 1247, as seen in fig. 15C.

Fig. 15D shows that the trenches 250 are formed to extend between lines extending along the Y-direction, with the trenches 250 extending down to the upper surface of the second conductor 1222 extending in the X-direction. Fig. 15E illustrates the structure outside the memory cell stack, separated by an insulating filler material 235. This shows the line 1245 in this embodiment lining the underside of the third conductor 1247 along the conductor between the memory cell stacks.

FIG. 16A shows a top layout view in the X-Y plane at a subsequent stage in the process; FIG. 16B shows a cross-sectional view along the Y-Z plane of line C-C shown in FIG. 16A in a subsequent stage of processing; FIG. 16C shows a cross-sectional view in the X-Z plane along line A-A shown in FIG. 16A at a subsequent stage in the process; FIG. 16D shows a cross-sectional view in the Y-Z plane along line D-D shown in FIG. 16A in a subsequent stage of processing; and FIG. 16E shows a cross-sectional view along the X-Z plane along line B-B shown in FIG. 16A in a subsequent stage of processing. At this stage, the process has included depositing a thin film liner 251 of silicon nitride or other confining liner material over the structure, followed by providing an insulating fill 252 and planarizing the structure such that the upper surface of the insulating fill 252 is coplanar with the upper surface of the thin film liner 251. Referring to fig. 16A, a top view illustrates the lines extending in the Y-direction covered by a thin film liner 251 of silicon nitride or other confining liner material. The film pads 251 are separated by insulating filler 252. Fig. 16B shows the film pad 251 on top of the extended line in the Y direction. Fig. 16C shows the phase change memory material in the thin film liner 251, the line 1245 overlying the sidewalls of the liner channel and the confinement structure in the higher level, and in the body 2281. The sidewalls of the channel are aligned to the memory cell stack. Fig. 16D shows insulating fill 252 over the thin film liner 251 in the trenches between the lines. Fig. 16E shows a thin film liner 251 lining the channel between the memory cell stacks.

In an alternative embodiment, to fabricate a higher height memory cell stack, the process may include removing the lines 1248 of hard mask material and planarizing the structure down to the upper surface of the third conductor 1247 to create a planar surface for continued formation of the cross-point structure.

Fig. 16B and 16C illustrate the memory cell stack structure in first and second heights of the array. These memory cell stacks are similar except that they are rotated 90 deg. relative to one another, such that the confining spacers 2216, 2217 in the first height extend in the Y direction and the confining spacers 2241, 2242 in the second height extend in the X direction.

The memory cell stack in the first height includes a body 2280 of phase change material between localized spacers 2216 and 2217 on opposite sides of the memory cell stack. The localized spacers 2216 and 2217 are aligned to the first conductors 1201 extending in the Y-direction. Furthermore, in the first height of the memory cell stack, the body 2280 of phase change material between the confined spacers 2216, 2217 is confined on the second pair of opposite sides by the insulating confining liners 230, 231. The insulating location pads 230, 231 are aligned with the second conductor 1222 extending in the X-direction. In the second height, the memory cell stack includes a body 2281 of phase change material between localized spacers 2241, 2242 (fig. 16B) on opposite sides of the memory cell stack. The localized spacers 2241 and 2242 are aligned with the second conductor 1222 extending in the X direction. Furthermore, in a second height of the memory cell stack, the body 2281 of phase change material between the confinement spacers 2241, 2242 is confined on a second opposite side by the confinement liners 261, 262 on the sidewalls (fig. 16C-part of the film liner 251).

Thus, due to the procedure described, a multi-level crosspoint configuration is provided. In a multi-height cross-point configuration, the memory cell stack includes a confined body of programmable resistive memory material. The confined body has a cross-sectional area substantially less than the cross-sectional area of the memory cell stack in the columnar volume. The cross-sectional area is defined by the width of the conductor at the intersection.

For embodiments such as that depicted in fig. 2, in the form of pillars of the memory device, the process flow is adjusted to add a Chemical Mechanical Polishing (CMP) step or other planarization step after depositing the programmable resistive memory material as shown in fig. 8A and 8B and in fig. 14A-14D. A body of programmable resistive memory material is created having an upper surface that is coplanar with the upper surface of the confined spacer. FIG. 17A depicts a cross-sectional view along the Y-Z plane, adjusted for change, equivalent to the line C-C shown in FIG. 16A for this alternative embodiment; and FIG. 17B shows a cross-sectional view along the X-Z plane, adjusted for the change, equivalent to the line B-B shown in FIG. 16A. As shown in fig. 17A and 17B, the phase change material (2290, 2291) is not lined on the underside of the conductors (1222, 1247) between the memory cell stacks in this embodiment.

Fig. 18 depicts an integrated circuit 3250 comprising a 3D cross point memory array 3200, the 3D cross point memory array 3200 comprising memory cells comprising ovonic threshold switches in series with a body of phase change material confined by a confinement spacer as described herein. The plane and row decoder 3201 is coupled to and in electrical communication with a plurality of word lines 3202 and is disposed along rows in the 3D cross-point memory array 3200. Row decoder 3203 is coupled to and in electrical communication with a plurality of bit lines 3204 and is arranged along rows of 3D cross-point memory array 3200 to read data from and write data to memory cells in 3D cross-point memory array 3200. The bus 3205 provides addresses to the plane and column decoders 3201 and row decoders 3203. Sense amplifiers and other support circuits (support circuits), such as precharge circuits, and data-in structures in block 3206 are coupled to row decoder 3203 via bus 3207. Data is supplied via the data-in line 3211 from input/output ports on the integrated circuit 3250 or other data sources to the data-in structures in block 3206. Data is supplied via a data-out line 3215 from the sense amplifiers in block 3206 to input/output ports on integrated circuit 3250, or to other data destinations internal or external to integrated circuit 3250. A bias arrangement state machine (bias arrangement state machine) in the control circuit 3209 controls bias arrangement supply voltages (bias arrangement supply voltages)3208 and sense amplifiers and data-in structures in block 3206 for read and write operations. The control circuit 3209 may be implemented using special purpose logic circuitry (special purpose logic circuitry), a general purpose processor, or a combination thereof, configured to perform read, write, and erase operations.

Cross-point memory constructions and memory cell constructions are provided. Phase change materials or other programmable resistive memory materials may be confined on four sides by silicon nitride or other confining materials in cross-point memory constructions and memory cell structures while maintaining self-alignment to the volume in the array cross-points. Furthermore, memory cell retention is improved and reset current levels can be reduced.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.