阅读说明：本技术 存储器阵列的板节点配置及操作 (Plate node configuration and operation of memory arrays ) 是由 D·维梅尔卡蒂 于 2018-05-09 设计创作，主要内容包括：本发明描述用于存储器阵列的板节点配置及操作的方法、系统及装置。存储器阵列的单个板节点可耦合到存储器单元层面中的存储器单元(例如,铁电存储器单元)的多个行或列。所述单个板节点可执行多个板节点的功能。将所述单个板节点耦合到衬底的触点数目可比将多个板节点耦合到所述衬底的触点数目小。存储器阵列中具有单个板节点的连接器或插座可界定比具有多个板节点的所述连接器或插座的大小小的大小。在一些实例中,所述存储器阵列的单个板节点可耦合到多个存储器单元层面中的存储器单元的多个线。(Methods, systems, and devices for plate node configuration and operation of memory arrays are described. A single plate node of the memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a memory cell plane. The single board node may perform the functions of multiple board nodes. The number of contacts coupling the single board node to a substrate may be less than the number of contacts coupling a plurality of board nodes to the substrate. A connector or receptacle in a memory array having a single board node may define a size that is smaller than the size of the connector or receptacle having multiple board nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of memory cells in multiple memory cell levels.)

1. An electronic memory apparatus, comprising:

a three-dimensional ferroelectric memory cell array having a first ferroelectric memory cell level and a second ferroelectric memory cell level;

a plate node coupled to a first ferroelectric memory cell coupled to a first digit line and a second ferroelectric memory cell coupled to a second digit line different from the first digit line; and

a plate driver coupled to the plate node, the plate driver operable to adjust a voltage of the plate node.

2. The electronic memory device of claim 1, wherein:

the plate node is coupled to the first ferroelectric memory cell deck and the second ferroelectric memory cell deck.

3. The electronic memory device of claim 1, wherein:

the plate node includes a sheet coupled to a plurality of rows or a plurality of columns of ferroelectric memory cells of the first level and a plurality of rows or a plurality of columns of ferroelectric memory cells of the second level in the three-dimensional array.

4. The electronic memory device of claim 1, wherein:

the plate driver is positioned outside of a footprint of the three-dimensional ferroelectric memory cell array.

5. The electronic memory device of claim 4, further comprising:

access lines coupled to the plate driver, the access lines extending from the plate driver to at least one edge of the footprint of the three-dimensional array.

6. The electronic memory device of claim 1, wherein the board node comprises:

a first portion coupled to the first ferroelectric memory cell deck; and

a second portion coupled to the second ferroelectric memory cell level.

7. The electronic memory device of claim 6, wherein:

the second portion of the board node is coupled to the first portion of the board node by a via structure between the first level and the second level.

8. The electronic memory device of claim 1, further comprising:

a connector associated with the two ferroelectric memory cells of the first level and the two ferroelectric memory cells of the second level, the connector configured to couple the associated ferroelectric memory cells to one or more digit lines.

9. The electronic memory device of claim 8, wherein the connector further comprises:

a first connection coupling the first ferroelectric memory cell of the first deck to the first digit line; and

a second connection coupling the second ferroelectric memory cell of the first deck to the second digit line.

10. The electronic memory device of claim 8, wherein:

the connector does not include a connection coupling the plate node to the associated ferroelectric memory cell.

11. The electronic memory device of claim 8, wherein:

the two ferroelectric memory cells of the second deck are coupled to respective digit lines independently of the connector.

12. The electronic memory device of claim 1, further comprising:

a plurality of switching components coupled to a sensing component and a plurality of digit lines, each switching component coupled to a respective digit line of the plurality of digit lines, each switching component configured to selectively couple the respective digit line to the sensing component based at least in part on performing an access operation using the respective digit line.

13. The electronic memory device of claim 1, further comprising:

a plurality of shunt switching components coupled to the board node and a plurality of digit lines, each shunt switching component coupled to a respective digit line of the plurality of digit lines, each shunt switching component configured to selectively couple the respective digit line to the board node based at least in part on an access operation not being performed using the respective digit line.

14. The electronic memory device of claim 13, wherein:

the shunt switching component is in a portion of the substrate below the array.

15. A method, comprising:

applying a first voltage to a plate node and a digit line each coupled to a ferroelectric memory cell during a time period prior to an access operation for the ferroelectric memory cell;

selecting the ferroelectric memory cell for the access operation via a word line coupled to the ferroelectric memory cell; and

discharging the digit line based at least in part on selecting the ferroelectric memory cell for the access operation.

16. The method of claim 15, further comprising:

coupling the plate node to an unselected digit line associated with the plate node.

17. The method of claim 16, wherein coupling the board nodes further comprises:

activating a plurality of shunt switching components coupled to the board node and the unselected digit line.

18. The method of claim 15, further comprising:

maintaining the first voltage on the plate node while discharging the digit line.

19. The method of claim 15, further comprising:

activating a select component of the ferroelectric memory cell based at least in part on selecting the ferroelectric memory cell and discharging the digit line.

20. The method of claim 15, further comprising:

as part of the access operation, a ferroelectric capacitor of the ferroelectric memory cell is discharged onto the digit line based at least in part on discharging the digit line.

21. The method of claim 15, further comprising:

discharging the plate node from the first voltage to a second voltage less than the first voltage based at least in part on activating a sense component coupled to the digit line.

22. The method of claim 15, further comprising:

as part of the access operation, a second voltage on the digit line is sensed based at least in part on activating a sense component coupled to the digit line, the second voltage associated with a charge of the ferroelectric memory cell.

23. The method of claim 15, further comprising:

identifying a voltage level of the plate node; and

applying the voltage level of the plate node to an unselected digit line when the plate node is coupled to the unselected digit line.

24. The method of claim 15, further comprising:

discharging the plate node during a write back portion of the access operation.

25. The method of claim 15, further comprising:

applying the first voltage to the plate node and the digit line based at least in part on completion of the access operation.

26. The method of claim 15, wherein:

the plate node and the digit line are maintained at a non-zero voltage between access operations performed on the ferroelectric memory cells.

27. An apparatus, comprising:

an array of ferroelectric memory cells having a first ferroelectric memory cell level, a second ferroelectric memory cell level, and a plate node coupled to the first ferroelectric memory cell and the second ferroelectric memory cell, the first ferroelectric memory cell coupled to a first digit line, the second ferroelectric memory cell coupled to a second digit line different from the first digit line; and

a controller in electronic communication with the array, wherein the controller is operable to:

applying a first voltage to the plate node and digit line as part of an idle period prior to performing an access operation;

coupling the board node to an unselected digit line associated with the board node;

selecting a ferroelectric memory cell from the array of ferroelectric memory cells as part of a read operation, the selected ferroelectric memory cell coupled to the plate node and the digit line; and

discharging the digit line based at least in part on selecting the ferroelectric memory cell for the access operation.

28. An apparatus, comprising:

means for applying a first voltage to a plate node and a digit line each coupled to a ferroelectric memory cell during a time period prior to an access operation for the ferroelectric memory cell;

means for selecting the ferroelectric memory cell for the access operation via a word line coupled to the ferroelectric memory cell; and

means for discharging the digit line based at least in part on the means for selecting the ferroelectric memory cell for the access operation.

29. The apparatus of claim 28, further comprising:

means for coupling the plate node to an unselected digit line associated with the plate node.

30. The apparatus of claim 29, wherein the means for coupling the plate node further comprises:

activating a plurality of shunt switching components coupled to the board node and the unselected digit line.

31. The apparatus of claim 28, further comprising:

means for maintaining the first voltage on the plate node while discharging the digit line.

32. The apparatus of claim 28, further comprising:

means for activating a select component of the ferroelectric memory cell based at least in part on selecting the ferroelectric memory cell and discharging the digit line.

33. The apparatus of claim 28, further comprising:

means for discharging a ferroelectric capacitor of the ferroelectric memory cell onto the digit line based at least in part on discharging the digit line as part of the access operation.

34. The apparatus of claim 28, further comprising:

means for discharging the plate node from the first voltage to a second voltage less than the first voltage based at least in part on activating a sense component coupled to the digit line.

35. The apparatus of claim 28, further comprising:

means for sensing a second voltage on the digit line as part of the access operation based at least in part on the means for activating a sense component coupled to the digit line, the second voltage associated with a charge of the ferroelectric memory cell.

36. The apparatus of claim 28, further comprising:

means for identifying a voltage level of the plate node; and

means for applying the voltage level of the plate node to an unselected digit line when the plate node is coupled to the unselected digit line.

37. The apparatus of claim 28, further comprising:

means for discharging the plate node during a write back portion of the access operation.

38. The apparatus of claim 28, further comprising:

means for applying the first voltage to the plate node and the digit line based at least in part on completion of the access operation.

39. The apparatus of claim 28, wherein:

the plate node and the digit line are maintained at a non-zero voltage between access operations performed on the ferroelectric memory cells.

Background

The following relates generally to plate node configuration and operation of memory arrays, and more specifically to plate node configuration in memory arrays.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by a logical "1" or a logical "0". In other systems, more than two states may be stored. To access the stored information, components of the electronic device may read or sense a stored state in the memory device. To store information, components of the electronic device may write or program a state in the memory device.

There are various types of memory devices, including magnetic hard disks, Random Access Memory (RAM), Read Only Memory (ROM), dynamic RAM (dram), synchronous dynamic RAM (sdram), ferroelectric RAM (feram), magnetic RAM (mram), resistive RAM (rram), flash memory, Phase Change Memory (PCM), and others. The memory devices may be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) may maintain its stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices (e.g., DRAMs) may lose their stored state over time unless they are periodically refreshed by an external power supply. FeRAM may use a similar device architecture as volatile memory, but may have non-volatile properties due to the use of ferroelectric capacitors as storage devices. Thus, FeRAM devices may have improved performance compared to other non-volatile and volatile memory devices.

In general, improving a memory device may include increasing memory cell density, increasing read/write speed, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Three-dimensional arrays may be desirable to address these issues, but the benefits may be hindered by replicating two-dimensional architectural features, such as a plate-line configuration.

Drawings

FIG. 1 illustrates an example of a memory array supporting board node configuration and operation of the memory array according to an embodiment of the invention.

FIG. 2 illustrates an example of a circuit supporting board node configuration and operation of a memory array according to an embodiment of the invention.

FIG. 3 illustrates an example of hysteresis curves supporting plate node configuration and operation of a memory array, according to an embodiment of the invention.

Figure 4A illustrates an example of a first cross-sectional view of a memory array supporting a plate node configuration and operation of the memory array, according to an embodiment of the invention.

Figure 4B illustrates an example of a second cross-sectional view of the memory array of figure 4A supporting a plate node configuration and operation of the memory array, according to an embodiment of the invention.

Figure 4C illustrates an example of a connector supporting board node configuration and operation of a memory array according to an embodiment of the invention.

FIG. 5A illustrates an example of a memory array supporting board node configuration and operation of the memory array, according to an embodiment of the invention.

FIG. 5B illustrates an example of a connector supporting board node configuration and operation of a memory array, according to an embodiment of the invention.

FIG. 6 illustrates an example of a memory array supporting board node configuration and operation of the memory array, according to an embodiment of the invention.

FIG. 7 illustrates an example of a timing diagram supporting board node configuration and operation of a memory array according to an embodiment of the invention.

FIG. 8 illustrates an example of a circuit supporting the plate node configuration and operation of a memory array, according to an embodiment of the invention.

Figures 9-10 show block diagrams of devices that support board node configuration and operation of a memory array, according to embodiments of the invention.

FIG. 11 illustrates a block diagram of a system including a memory controller supporting board node configuration and operation of a memory array, according to an embodiment of the invention.

Figures 12-13 illustrate a method of plate node configuration and operation for a memory array, according to an embodiment of the invention.

Detailed Description

In a memory array, a single plate node may be coupled to memory cells associated with multiple digit lines in the array. The number of board nodes within the array may thus be reduced relative to alternative architectures. In some examples, a single board node may be coupled to memory cells associated with multiple levels of a memory array. Unlike a two-dimensional architecture, multiple levels of the array may be accessed using a common board node, for example.

By way of example, in some memory arrays, multiple levels of memory cells may be positioned above a substrate. The substrate may include various support components for operating the memory array, including, for example, decoders, amplifiers, drivers, and the like. When an upper memory cell level is stacked on top of a lower memory cell level, contacts for components of the upper level may pass through space available for components of the lower memory cell level. As such, space in the memory array may be allocated to connectors or sockets that couple platelines and other components to the substrate.

A single plate node of the memory array may be coupled to multiple lines of memory cells of the memory cells. In some examples, a single board node may be common to the same section, the same tile (tile), memory cells in the same level, or even memory cells in multiple levels. In such examples, a single board node may perform the functions of multiple board nodes. The number of contacts coupling a single board node to the substrate may be less than the number of contacts coupling a plurality of board nodes to the substrate. A connector or receptacle in a memory array having a single board node may define a size that is smaller than the size of a connector or receptacle having multiple board nodes. In some examples, a single plate node of a memory array may be coupled to multiple lines of memory cells in multiple memory cell levels.

The features of the invention introduced above are further described below in the context of fig. 1 to 13. The features of the present invention are illustrated by and described with reference to apparatus, system, and flow diagrams related to plate configuration and operation of memory arrays.

FIG. 1 illustrates an example memory array 100, according to various embodiments of the invention. The memory array 100 may also be referred to as an electronic memory device. Memory array 100 includes memory cells 105 that are programmable to store different states. Each memory cell 105 may be programmable to store two states, represented as a logic 0 and a logic 1. In some cases, memory cell 105 is configured to store more than two logic states. Memory cell 105 may store a charge representing a programmable state in a capacitor; for example, charged and uncharged capacitors may represent two logic states, respectively. DRAM architectures may typically use this design, and the employed capacitors may include dielectric materials with linear or paraelectric electrical polarization properties as insulators. By comparison, a ferroelectric memory cell may comprise a capacitor having a ferroelectric as the insulating material. Different charge levels of the ferroelectric capacitor may represent different logic states. The ferroelectric material has nonlinear polarization properties; some details and advantages of ferroelectric memory cell 105 are discussed below.

The memory array 100 may be a three-dimensional (3D) memory array, where two-dimensional (2D) memory arrays are formed on top of each other. This may increase the number of memory cells that can be formed on a single die or substrate, which in turn may reduce production costs or increase performance of the memory array, or both, as compared to a 2D array. According to the example depicted in fig. 1, memory array 100 includes two levels of memory cells 105 and thus can be considered a three-dimensional memory array; however, the number of levels is not limited to two. Each level may be aligned or positioned such that memory cells 105 may be substantially aligned with each other across each level, forming a memory cell stack 145.

Each row of memory cells 105 is connected to an access line 110, and each column of memory cells 105 is connected to a bit line 115. The access lines 110 and bit lines 115 may be substantially perpendicular to each other to form an array. Additionally, each row of memory cells 105 may be coupled to a plate line (not shown). As used herein, the terms board node, board line, or board only are used interchangeably. As shown in fig. 1, each memory cell 105 in the memory cell stack 145 may be coupled to a separate conductive line, such as a bitline 115. In other examples (not shown), two memory cells 105 in a memory cell stack 145 may share a common conductive line, such as a bit line 115. That is, bit line 115 may be in electronic communication with a bottom electrode of upper memory cell 105 and a top electrode of lower memory cell 105. Other configurations may be possible, for example, the third level may share access lines 110 with the lower level. In general, one memory cell 105 may be located at an intersection of two conductive lines (e.g., access line 110 and bit line 115). This intersection may be referred to as the address of the memory cell. Target memory cell 105 may be memory cell 105 located at the intersection of powered access line 110 and bitline 115; that is, access lines 110 and bit lines 115 may be energized in order to read or write to memory cells 105 at their intersections. Other memory cells 105 in electronic communication with (e.g., connected to) the same access line 110 or bitline 115 may be referred to as non-target memory cells 105.

As discussed above, electrodes may be coupled to memory cells 105 and access lines 110 or bit lines 115. The term electrode may refer to an electrical conductor, and in some cases, an electrode may be employed as an electrical contact to memory cell 105. The electrodes may include traces, wires, conductive lines, conductive layers, and the like that provide conductive paths between elements or components of the memory array 100.

Operations such as reads and writes may be performed on memory cells 105 by activating or selecting access lines 110 and digit lines 115. The access lines 110 may also be referred to as word lines 110 and the bit lines 115 may also be referred to as digit lines 115. In some examples, the term access line may refer to a word line, a bit line, a digit line, or a plate line. The mentioned word lines and bit lines or the like are interchangeable without losing understanding or operation. Activating or selecting a word line 110 or digit line 115 may include applying a voltage to the respective line. The word lines 110 and digit lines 115 can be made of conductive materials such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), etc.), metal alloys, carbon, conductively doped semiconductors or other conductive materials, alloys, compounds, and so forth.

In some architectures, the logic storage (e.g., capacitor) of the cell may be electrically isolated from the digit line by a select component. A word line 110 may be connected to and may control the select component. For example, the select component may be a transistor and the word line 110 may be connected to the gate of the transistor. Activating a word line 110 creates an electrical connection or close circuit between the capacitor of a memory cell 105 and its corresponding digit line 115. The digit lines can then be accessed to read or write to memory cells 105. Upon selection of memory cell 105, the resulting signal may be used to determine the stored logic state.

Access to memory cells 105 may be controlled by a row decoder 120 and a column decoder 130. For example, the row decoder 120 may receive a row address from the memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, a column decoder 130 receives a column address from a memory controller 140 and activates the appropriate digit lines 115. For example, the memory array 100 may include a plurality of word lines 110 and a plurality of digit lines 115. Thus, by activating word line 110 and digit line 115, memory cell 105 at its intersection can be accessed. As described in more detail below, by coupling a single plate to multiple memory cell lines (e.g., rows or columns), access operations to the memory cells can be modified. For example, during an idle period, the plate line and digit line of a memory cell may be maintained at a non-zero voltage. In another example, during an access operation, digit lines coupled to unselected memory cells can be selectively coupled to plates to mitigate undesired transient voltages.

Upon access, the memory cell 105 may be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105. For example, after accessing memory cell 105, the ferroelectric capacitor of memory cell 105 may discharge onto its corresponding digit line 115. Discharging the ferroelectric capacitor may result from biasing the ferroelectric capacitor or applying a voltage to the ferroelectric capacitor. The discharge may result in a change in the voltage of digit line 115, which sensing component 125 may compare to a reference voltage (not shown) in order to determine the stored state of memory cell 105. Exemplary access operations for ferroelectric memory cells are described below with reference to fig. 2 and 3.

The sensing component 125 may include various transistors or amplifiers in order to detect and amplify differences in signals, which may be referred to as latching. The detected logic state of memory cell 105 may then be output as output 135 through column decoder 130. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, sensing component 125 can be connected to column decoder 130 or row decoder 120 or in electronic communication with column decoder 130 or row decoder 120. As described in more detail below, unselected memory cells may be shunted to the plate to mitigate undesired transient voltages.

In some memory architectures, accessing the memory cell 105 may degrade or destroy the stored logic state, and a rewrite or refresh operation may be performed to return the original logic state to the memory cell 105. In a DRAM, for example, the capacitor may be partially or fully discharged during a sensing operation, destroying the stored logic state. Thus, the logic state may be rewritten after the sensing operation. Additionally, activating a single word line 110 can cause the discharge of all memory cells in a row; thus, it may be desirable to re-write several or all of memory cells 105 in a row. In non-volatile memories (e.g., arrays employing ferroelectrics), accessing the memory cell 105 may not destroy the logic state, and thus, the memory cell 105 may not need to be rewritten after the access. In some examples, multiple levels of memory cells may be coupled to the same plate. This plate configuration can result in a smaller amount of area for connecting higher level memory cells to the substrate.

Some memory architectures that include DRAMs may lose their stored state over time unless they are periodically refreshed by an external power supply. For example, a charged capacitor may discharge over time through leakage current, causing loss of stored information. The refresh rate of these so-called volatile memory devices can be relatively high, e.g., tens of refresh operations per second of a DRAM array, which can cause significant power consumption. As memory arrays get larger, increased power consumption may inhibit the deployment or operation of the memory array (e.g., power supply, heat generation, material limitations, etc.), especially for mobile devices that rely on a limited power source, such as a battery. As discussed below, ferroelectric memory cell 105 may have beneficial properties that may result in improved performance relative to other memory architectures.

The memory controller 140 may control the operation (e.g., read, write, re-write, refresh, discharge, etc.) of the memory cells 105 through various components (e.g., the row decoder 120, the column decoder 130, and the sensing component 125). In some cases, one or more of the row decoder 120, column decoder 130, and sensing component 125 may be co-located with the memory controller 140. The memory controller 140 may generate row and column address signals in order to activate the desired word line 110 and digit line 115. The memory controller 140 may also generate and control various voltages or currents used during operation of the memory array 100. For example, it may apply a discharge voltage to the word line 110 or digit line 115 after accessing one or more memory cells 105. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory array 100. Furthermore, one, more, or all of the memory cells 105 within the memory array 100 may be accessed simultaneously; for example, multiple or all cells of the memory array 100 may be accessed simultaneously during a reset operation, with all memory cells 105 or groups of memory cells 105 set to a single logic state.

FIG. 2 illustrates an example circuit 200 according to various embodiments of the invention. The circuit 200 includes a memory cell 105-a, a word line 110-a, a digit line 115-a, and a sensing component 125-a, which can be examples of a memory cell 105, a word line 110, a digit line 115, and a sensing component 125, respectively, as described with reference to FIG. 1. Memory cell 105-a may include a logic storage component, such as capacitor 205 having a first plate (cell plate 230) and a second plate (cell bottom 215). Cell plate 230 and cell bottom 215 may be capacitively coupled by a ferroelectric material positioned therebetween. The orientation of the cell plate 230 and the cell bottom 215 may be flipped without changing the operation of the memory cell 105-a. The circuit 200 also includes a select component 220 and a reference line 225. Cell plate 230 may be accessed via plate line 210 and cell bottom 215 may be accessed via digit line 115-a. In some cases, some memory cells 105-a may share an access line (e.g., a digit line, a word line, a plate line) with other memory cells. For example, a digit line 115-a may be shared with memory cells 105-a in the same column, a word line 110-a may be shared with memory cells 105-a in the same row, and a plate line 210 may be shared with memory cells 105-a in the same segment, tile, level, or even multiple levels. As described above, various states may be stored by charging or discharging the capacitor 205. In many examples, a connector or socket may be used to couple a digit line 115-a or a plateline 210 of an upper memory cell level to a substrate positioned below a memory cell array. The size of the connector or receptacle may be modified based on the configuration of the plateline in the memory array.

The stored state of the capacitor 205 may be read or sensed by operating the various elements represented in the circuit 200. Capacitor 205 may be in electronic communication with digit line 115-a. For example, capacitor 205 may be isolated from digit line 115-a when select component 220 is deactivated, and capacitor 205 may be connected to digit line 115-a when select component 220 is activated. Activating selection component 220 may be referred to as selecting memory cell 105-a. In some cases, the select component 220 is a transistor and its operation is controlled by applying a voltage to the transistor gate, where the voltage magnitude is greater than the threshold magnitude of the transistor. The word line 110-a may activate the select element 220; for example, a voltage applied to the word line 110-a is applied to the transistor gate, connecting the capacitor 205 with the digit line 115-a. As described in more detail below, access operations (e.g., read operations or write operations) may be modified based on the plate configuration of the memory array.

In other examples, the locations of select component 220 and capacitor 205 may be swapped such that select component 220 is connected between plate line 210 and cell plate 230 and such that capacitor 205 is located between digit line 115-a and another terminal of select component 220. In this embodiment, selection component 220 may remain in electronic communication with digit line 115-a through capacitor 205. Such a configuration may be associated with alternative timing and biasing for read and write operations.

Due to the ferroelectric material located between the plates of capacitor 205, and as discussed in more detail below, capacitor 205 may not discharge upon connection to digit line 115-a. In one scheme, to sense the logic state stored by ferroelectric capacitor 205, word line 110-a may be biased to select memory cell 105-a and a voltage may be applied to plate line 210. In some cases, the digit line 115-a is virtually grounded and then isolated from the virtual ground before being biased to the plate line 210 and the word line 110-a, which may be referred to as "floating". Biasing plate line 210 may cause a voltage difference across capacitor 205 (e.g., plate line 210 voltage minus digit line 115-a voltage). The voltage difference may generate a change in the stored charge on the capacitor 205, where the magnitude of the change in the stored charge may depend on the initial state of the capacitor 205 — e.g., whether the initial state stores a logic 1 or a logic 0. This may result in a change in the voltage of digit line 115-a based on the charge stored on capacitor 205. Operating memory cell 105-a by varying the voltage to cell plate 230 may be referred to as "moving the cell plate". As described in more detail below, access operations (e.g., read operations or write operations) may be modified based on the plate configuration of the memory array.

The change in voltage of digit line 115-a may depend on its intrinsic capacitance. That is, as charge flows through digit line 115-a, some finite charge may be stored in digit line 115-a and the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance may depend on the physical characteristics of the digit line 115-a, including size. Digit line 115-a may connect many memory cells 105 and thus digit line 115-a may have a length that produces a non-negligible capacitance, e.g., on the order of a few picofarads (pF). The resulting voltage of digit line 115-a may then be compared to a reference (e.g., the voltage of reference line 225) by sensing component 125-a in order to determine the stored logic state in memory cell 105-a. Other sensing processes may be used.

The sensing component 125-a may include various transistors or amplifiers to detect and amplify the signal difference, which may be referred to as latching. Sense component 125-a may include a sense amplifier that receives the voltage of digit line 115-a and the voltage of reference line 225 (which may be a reference voltage) and compares the voltage of digit line 115-a to the voltage of reference line 225. The sense amplifier output may be driven to a higher (e.g., positive) or lower (e.g., negative or ground) supply voltage based on the comparison. For example, if digit line 115-a has a higher voltage than reference line 225, the sense amplifier output may be driven to a positive supply voltage. In some cases, the sense amplifier may additionally drive the digit line 115-a to a supply voltage. Sense component 125-a can then latch the output of the sense amplifier and/or the voltage of digit line 115-a, which can be used to determine a stored state, e.g., a logic 1, in memory cell 105-a. Alternatively, if digit line 115-a has a lower voltage than reference line 225, the sense amplifier output may be driven to a negative or ground voltage. Sense component 125-a may similarly latch the sense amplifier output to determine a stored state, e.g., a logic 0, in memory cell 105-a. The latched logic state of memory cell 105-a may then be output as output 135, for example, through column decoder 130 (see FIG. 1).

To write to memory cell 105-a, a voltage may be applied across capacitor 205. Various methods may be used. In one example, the select component 220 may be activated by the word line 110-a in order to electrically connect the capacitor 205 to the digit line 115-a. A voltage may be applied across capacitor 205 by controlling the voltage of cell plate 230 (through plate line 210) and cell bottom 215 (through digit line 115-a). To write a logic 0, cell plate 230 may be made high, i.e., a positive voltage may be applied to plate line 210, and cell bottom 215 may be made low, e.g., digit line 115-a is virtually grounded or a negative voltage is applied to digit line 115-a. The reverse process is performed to write a logic 1 with cell plate 230 low and cell bottom 215 high.

FIG. 3 illustrates an example of non-linear electrical properties having hysteresis curves 300-a and 300-b for a ferroelectric memory cell operating according to various embodiments of the present disclosure. Hysteresis curves 300-a and 300-b illustrate exemplary ferroelectric memory cell write and read processes, respectively. Hysteresis curves 300-a and 300-b depict the charge Q stored on a ferroelectric capacitor (e.g., capacitor 205 of FIG. 2) as a function of the voltage difference V.

Ferroelectric materials are characterized by spontaneous electric polarization, i.e., they maintain a non-zero electric polarization in the absence of an electric field. Exemplary ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconium titanate (PZT), and Strontium Bismuth Titanate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. Electrical polarization within the ferroelectric capacitor creates a net charge at the surface of the ferroelectric material and attracts an opposite charge through the capacitor terminals. Thus, charge is stored at the interface of the ferroelectric material and the capacitor terminals. Since electrical polarization can be maintained for relatively long periods of time, even indefinitely, in the absence of an externally applied electric field, charge leakage can be significantly reduced compared to capacitors employed in, for example, DRAM arrays. This may reduce the need to perform refresh operations as described above for some DRAM architectures.

The hysteresis curves 300-a and 300-b may be understood from the perspective of a single terminal of the capacitor. By way of example, if the ferroelectric material has a negative polarization, positive charges accumulate at the terminals. Likewise, if the ferroelectric material has a positive polarization, negative charges accumulate at the terminals. Additionally, it should be understood that the voltages in the hysteresis curves 300-a and 300-b represent the voltage difference across the capacitors and are directional. For example, a positive voltage may be achieved by applying a positive voltage to the terminal in question (e.g., cell plate 230) and maintaining the second terminal (e.g., cell bottom 215) at ground (or substantially zero volts (0V)). A negative voltage may be applied by maintaining the terminal in question at ground and applying a positive voltage to the second terminal-i.e. a positive voltage may be applied to negatively polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages may be applied to the appropriate capacitor terminals to generate the voltage differences shown in the hysteresis curves 300-a and 300-b.

As depicted in the hysteresis curve 300-a, the ferroelectric material may maintain a positive or negative polarization with a zero voltage difference, resulting in two possible charged states: charge state 305 and charge state 310. According to the example of fig. 3, charge state 305 represents a logic 0 and charge state 310 represents a logic 1. In some examples, the logic values of the respective charge states may be reversed to accommodate other schemes for operating the memory cells.

A logic 0 or 1 may be written to a memory cell by: the electric polarization of the ferroelectric material and thus the charge on the capacitor terminals is controlled by applying a voltage. For example, applying a net positive voltage 315 across the capacitor causes charge to accumulate until the charge state 305-a is reached. Upon removal of the voltage 315, the charge state 305-a follows the path 320 until it reaches the charge state 305 at zero voltage. Similarly, the charge state 310 is written by applying a net negative voltage 325, which results in charge state 310-a. After the negative voltage 325 is removed, the charge state 310-a follows the path 330 until it reaches the charge state 310 at zero voltage. The charge states 305-a and 310-a may also be referred to as remnant polarization (Pr) values, i.e., the polarization (or charge) that remains after the external bias (e.g., voltage) is removed. The coercive voltage is the voltage at which the charge (or polarization) is zero.

To read or sense the stored state of the ferroelectric capacitor, a voltage may be applied across the capacitor. In response, the stored charge Q changes, and the extent of the change depends on the initial charge state-i.e., whether the last stored charge (Q) depends on the initial stored charge state 305-b or 310-b. For example, hysteresis curve 300-b illustrates two possible stored charge states 305-b and 310-b. A voltage 335 may be applied across the capacitor as discussed with reference to fig. 2. In other cases, a fixed voltage may be applied to the cell plate, and although depicted as a positive voltage, voltage 335 may be negative. In response to voltage 335, charge state 305-b may follow path 340. Likewise, if charge state 310-b is initially stored, it follows path 345. The final location of charge state 305-c and charge state 310-c depends on a number of factors, including the particular sensing scheme and circuitry.

In some cases, the final charge may depend on the intrinsic capacitance of the digit line connected to the memory cell. For example, if a capacitor is electrically connected to the digit line and a voltage 335 is applied, the voltage of the digit line may rise due to its intrinsic capacitance. Thus, the voltage measured at the sense component may not equal the voltage 335 and may instead depend on the voltage of the digit line. The location of the last charge states 305-c and 310-c on the hysteresis curve 300-b may thus depend on the capacitance of the digitline and may be determined by load line analysis-i.e., the charge states 305-c and 310-c may be defined relative to the digitline capacitance. Thus, the voltage of the capacitor (voltage 350 or voltage 355) may be different and may depend on the initial state of the capacitor.

By comparing the digital line voltage to a reference voltage, the initial state of the capacitor can be determined. The digital line voltage may be the difference between voltage 335 and the last voltage across the capacitor (voltage 350 or voltage 355) -i.e., (voltage 335-voltage 350) or (voltage 335-voltage 355). The reference voltage may be generated such that its magnitude is between two possible voltages of the two possible digital line voltages in order to determine the stored logic state-i.e., whether the digital line voltage is above or below the reference voltage. For example, the reference voltage may be an average of two quantities (voltage 335-voltage 350) and (voltage 335-voltage 355). After comparison by the sense component, it can be determined whether the sensed digit line voltage is above or below the reference voltage, and the stored logic value (i.e., logic 0 or 1) of the ferroelectric memory cell can be determined.

As discussed above, reading a memory cell that does not use a ferroelectric capacitor can degrade or destroy the stored logic state. However, the ferroelectric memory cell may maintain an initial logic state after a read operation. For example, if charge state 305-b is stored, the charge state may follow path 340 to charge state 305-c during a read operation, and after voltage 335 is removed, the charge state may return to the initial charge state 305-b by following path 340 in the opposite direction.

In some examples of ferroelectric memory arrays, plate lines may be coupled to multiple lines of memory cells. In such configurations, the die region may be more efficiently used and allocated to additional memory cells. Various examples of plateline configurations are described herein and access operations associated with those configurations are also described herein.

Figure 4A illustrates an example of a first cross-sectional view of a memory array 400 supporting board node configuration and operation of the memory array, according to various embodiments of the invention. In the example of the memory array 100 described with reference to FIG. 1, a cross-sectional view of the memory array 400 can be taken along the lines 4A-4A shown in FIG. 1. As such, the digit lines and plate lines of the memory array 400 extend into or out of the page.

Memory array 400 may include a substrate 405, a first level 410 of memory cells 420, and a second level 415 of memory cells 420. Second level 415 may be positioned between substrate 405 and first level 410. The memory array 400 may be an example of the memory array 100 described with reference to FIG. 1. The first level 410 and the second level 415 may be examples of memory cell levels described with reference to fig. 1.

Each deck 410, 415 may include a plurality of memory cells 420, digit lines 425, plate lines 430, and other components and access lines not shown. Memory cell 420 may include a capacitor (not shown) and a select component (not shown). In some examples, word lines (not shown) may extend perpendicular to digit lines 425 and plate lines 430. In some examples, a word line may be connected to a select component placed between memory cell 420 and digit line 425 or between memory cell 420 and plate line 430, depending on the array architecture. Memory cell 420 may be an example of memory cell 105 described with reference to fig. 1 and 2. In some examples, memory cell 420 is a ferroelectric memory cell. In other examples, memory cell 420 may be a dielectric memory cell. For illustrative purposes only, each deck 410, 415 is shown with four memory cells. A level may include any number of memory cells and access lines.

Each memory cell 420 is coupled to a digit line 425 and a plate line 430. Each digit line 425 may be coupled to a plurality of memory cells 420. Each plate line 430 may be coupled to a plurality of memory cells 420. For example, digit line 425-a and plate line 430-a may extend outward from the plane of the page and be coupled to additional memory cells adjacent to memory cell 420-a. Digit line 425 may be an example of digit line 115 described with reference to fig. 1 and 2. Plate line 430 may be an example of plate line 210 described with reference to fig. 2.

Substrate 405 may be positioned below levels 410, 415 and access lines (e.g., digit line 425 and/or plate line 430) of memory cells 420. Substrate 405 may include components to support the operation of memory cell 420. For example, the substrate 405 may include decoders, amplifiers, drivers, and the like. Memory controller 140 may be coupled to various components of substrate 405 to perform operations on memory cells 420. In a memory array 400 that includes multiple levels of cells, a connector must pass through intervening layers of memory cells, access lines, or levels to reach a particular component.

Figure 4B illustrates an example of a second cross-sectional view of the memory array 400-a of figure 4A supporting a plate node configuration and operation of the memory array, according to an embodiment of the invention. The memory array 400-a of FIG. 4B may be an example of a memory array 400, but is illustrated from a different perspective. In the example of the memory array 100 described with reference to FIG. 1, a cross-sectional view of the memory array 400 can be taken along the line 4B-4B shown in FIG. 1. As such, the digit lines and plate lines of the memory array 400 extend horizontally across the page. In some examples, word lines (not shown) may extend outward from the plane of the page and couple to respective select components of each memory cell (not shown).

Memory array 400-a includes a substrate 405, a portion of a first level 410, and a portion of a second level 415. Specifically, memory array 400-a depicts memory cells 420-a from first level 410 and memory cells 420-e from second level 415 with their associated digit lines 425 and plate lines 430. Although digit lines 425-a, 425-e are illustrated as being coupled to two memory cells (420-a-1, 420-a-2, and 420-e-1, 420-e-2), digit lines 425 and plate lines 430 can be coupled to any number of memory cells 420. Two memory cells 420 are provided for illustrative purposes only.

Contacts 450 may couple digit lines 425-e to substrate 405. Contacts 450 may be configured to provide electronic communication between digit lines 425-e and supporting components (e.g., decoders, amplifiers, drivers, etc.) positioned in substrate 405. In some examples, the contacts 450 may be examples of vias. Contact 450 may be positioned in memory array 400-a without disturbing or interfering with other components of memory array 400-a (e.g., digit line 425-a, plate line 430-a, or plate line 430-e).

Contacts 455 may couple plateline 430-e to substrate 405. The contacts 455 may be configured to provide electronic communication between the plateline 430-e and supporting components (e.g., decoders, amplifiers, drivers, etc.) positioned in the substrate 405. In some examples, the contacts 455 may be examples of vias. In some examples, contact 455 may pass through digit lines 425-e. In some examples, digit lines 425-e may be terminated to allow contacts 455 to couple substrate 405 to plate lines 430-e. In some examples, the pattern of memory cells 420-e may be interrupted to be discontinuous to allow contact 455 to pass through.

Contacts 460 may couple digit line 425-a to substrate 405. Contacts 460 may be configured to provide electronic communication between digit line 425-a and supporting components (e.g., decoders, amplifiers, drivers, etc.) positioned in substrate 405. In some examples, the contacts 460 may be examples of vias. As with contact 455, in some examples, contact 460 may pass through other components to reach substrate 405. In some examples, plate lines 430-e, a pattern of memory cells 420-e, digit lines 425-e, or a combination thereof may be terminated, interrupted, and/or discontinuous to allow contacts 460 to pass through.

Contacts 465 may couple plateline 430-a to substrate 405. The contacts 465 may be configured to provide electronic communication between the plateline 430-a and supporting components (e.g., decoders, amplifiers, drivers, etc.) positioned in the substrate 405. In some examples, the contacts 465 may be examples of vias. As with contacts 455, 460, in some examples, contact 465 may pass through other components to reach substrate 405. In some examples, the pattern of memory cells 420-a, digit lines 425-a, plate lines 430-e, the pattern of memory cells 420-e, digit lines 425-e, or a combination thereof may be terminated, interrupted, and/or discontinuous to allow contacts 465 to pass through. In some examples, other conductive paths (not shown) may be configured to provide electronic communication between support components positioned in the substrate 405 and the respective digit lines 425 and/or plate lines 430. For example, these other conductive paths may include contacts or vias to higher level metal connections and contacts or vias to the silicon substrate (e.g., digit lines 425 and/or plate lines 435 may be staggered to ensure that the topmost level/level is inside, rather than extending outward beyond, the footprint of the underlying layer).

The contacts 455, 460, 465 may cooperate with the substrate 405 to form a connector 470. In some examples, the connection 470 may be referred to as a socket or a substrate connector. To reduce disturbance to the memory cell array, the contacts 455, 460, 465 may be located in groups. Such groupings can reduce the area of the memory array used to connect higher components and access lines to lower components and access lines. In some examples, connector 470 may refer to one of these groups. In some examples, connector 470 may refer to a portion 475 of substrate 405 that is configured to receive contacts from a higher layer or level. In some examples, the connector 470 may include contacts 455, 460, 465, other contacts, a portion 475 of the substrate 405, or a combination thereof. The memory array 400 may include a plurality of connectors 470 based at least in part on the number of lines of memory cells in the memory array 400.

FIG. 4C illustrates an example of circuitry 480 supporting plate node configuration and operation of a memory array, according to an embodiment of the invention. Circuit 480 includes an example of a connector 485 that may be used in memory array 400. Connector 485 may be configured to couple two cell stacks of components to substrate 405. For example, connector 485 may couple access lines associated with memory cell 420-a, memory cell 420-b, memory cell 420-e, and memory cell 420-f to substrate 405. As used herein, an access line may refer to a word line, or plate line. The circuit 480 illustrates a simplified circuit diagram of the memory array 400. Connector 485 may be an example of connector 470 described with reference to fig. 4B.

Connector 485 may include contacts for plateline 430-a, contacts for digit line 425-a, plateline 430-e, contacts for plateline 430-b, contacts for digit line 425-b, contacts for plateline 430-f, or combinations thereof. The connector 485 may also include a portion 490 of the substrate 405. The connector 485 may define a size 495. Size 495 may indicate the amount of area of memory array 400 used to couple components and access lines of higher level levels to substrate 405. In some examples, size 495 may be a first dimension measured along a first axis. In some examples, the size 495 may be a two-dimensional area. In some examples, size 495 may be a three-dimensional volume. The memory array 400 may include a plurality of connectors 485 based at least in part on the number of lines of memory cells in the memory array 400.

Figure 5A illustrates an example of a memory array 500 supporting board node configuration and operation of the memory array, according to various embodiments of the invention. In the example of the memory array 100 described with reference to FIG. 1, a cross-sectional view of the memory array 500 may be taken along the lines 4A-4A shown in FIG. 1. As such, the digit lines and plate lines of the memory array 500 extend into or out of the page.

The memory array 500 may be an example of the memory array 400 described with reference to fig. 4A-4C. As such, a full description of at least some of the components of the memory array 500 is not repeated here. The memory array 500 can include a substrate 505, a first level 510 of memory cells 520, and a second level 515 of memory cells 520. Memory cell 520 may be coupled to digit line 525 and plates 530, 535. The substrate 505 may be an example of the substrate 405 described with reference to fig. 4A-4C. The levels 510, 515 of the memory cells 520 may be examples of the levels 410, 415 described with reference to fig. 4A-4B. Memory cell 520 may be an example of memory cell 105 and memory cell 420 described with reference to fig. 1, 2, 4A, and 4B. Digit line 525 may be an example of digit line 115 and digit line 425 described with reference to figures 1, 2, 4A, and 4B.

The memory array 500 can include a first plate line 530 associated with the first deck 510. First plate line 530 may be coupled to a plurality of lines of memory cells (e.g., memory cells 520-a, 520-b, 520-c, 520-d). As shown in FIGS. 4A and 4B, a single plate line 430-a is coupled to a single line of memory cells 420-a. In some examples, a single plate line 430-a is associated with a single digit line 425-a, where memory cells 420-a coupled to digit line 425-a are also coupled to plate line 430-a.

First plate line 530 may be configured to bias multiple lines of memory cells 520. As such, first plate line 530 may be associated with a plurality of digit lines (e.g., digit lines 525-a, 525-b, 525-c, 525-d). In practice, there may be a one-to-many mapping of first plate lines 530 to digit lines 525. In contrast, the memory array 400 includes an individual plate line 430 for each individual digit line 425. In effect, plate line 430 maps one-to-one with digit line 425. In some examples, first plate line 530 (and second plate line 535) may be formed as a sheet of material coupled to multiple rows or columns of memory cells 520. The plate lines 530, 535 may be formed of a conductive or metallic material using various methods. The plate lines 530, 535 may be formed by deposition and patterning (e.g., etching of a conductive/metallic material or compound).

The memory array 500 may include a second plate line 535 associated with the second deck 515. Second plate line 535 may be coupled to a plurality of lines of memory cells (e.g., memory cells 520-e, 520-f, 520-g, 520-h). Second plate line 535 may be configured to bias multiple lines of memory cells 520. The second plate line 535 may be associated with a plurality of digit lines (e.g., digit lines 525-e, 525-f, 525-g, 525-h). In practice, there is a one-to-many mapping of the second plate line 535 to the digit line 525. In contrast, the memory array 400 includes an individual plate line 430 for each individual digit line 425. In effect, plate line 430 maps one-to-one with digit line 425.

The configuration of the first plateline 530 and the second plateline 535 can reduce the number of contacts between the plateline and the substrate 505. For example, instead of contacts being located or formed for each individual plateline (e.g., plateline 430-a), a single contact may couple the first plateline 530 to the substrate 505. Additionally, a single contact may couple the second plate line 535 to the substrate 505. A plate driver may be coupled to each plate line 530, 535 in the memory array 500. The plate driver may be coupled to the plate lines 530, 535 through the substrate 505 and contacts. The architecture of the memory array 500 may reduce the number of plate drivers in the memory array 500. In some examples, the plate driver may be positioned outside of a footprint of the three-dimensional ferroelectric memory cell array. Additionally or alternatively, the access lines may be coupled to the plate driver and may extend from the plate driver to an edge of a footprint of the three-dimensional array. In some examples, the configuration of first plate line 530 and second plate line 535 may reduce the amount of die area employed to connect the plate lines of levels 510, 515 to the substrate.

In some cases, a plate line (or plate node) may be coupled to memory cell 520, with memory cell 520 coupled to a different digit line 525. For example, plate line 530 may be coupled to memory cell 520-a and memory cell 520-b, with memory cell 520-a coupled to digit line 525-a, which digit line 525-a is different than digit line 525-b coupled to memory cell 520-b. In some examples, a plate line (or plate node) may be coupled to memory cells of a section of memory array 500. In some examples, a plate line (or plate node) may be coupled to memory cells of a tile of memory array 500. In some examples, plate lines (or plate nodes) (e.g., plate lines 530, 535) may be coupled to memory cells of a level of the memory array 500.

FIG. 5B illustrates an example of a circuit 550 supporting the board node configuration and operation of a memory array, according to an embodiment of the invention. Circuitry 550 illustrates how the size of connector 555 may be reduced (as compared to connector 485) based on the configuration of platelines 530, 535. The connector 555 can be configured to couple two cell stacks of components to the substrate 505. For example, the connector 555 can couple a plurality of digit lines 525 associated with the first tier 510 to the substrate 505.

Connector 555 may not include plateline contacts. This means that the connector 555 may not include any contacts (or vias) that couple the plate lines 530, 535 to the substrate 505. Since connector 555 may not include any plateline contacts, size 565 of connector 555 may be smaller than size 495 of connector 485.

Connector 555 may include contacts for digit line 525-a and contacts for digit line 525-b. The connector 555 may also include a portion 560 of the substrate 505. Size 565 may indicate an amount of area of memory array 500 used to couple higher layers or levels of components and access lines to substrate 505. In some examples, the size 565 may be a first dimension measured along a first axis. In some examples, size 565 may be a two-dimensional area. In some examples, size 565 may be a three-dimensional volume. In some examples, connector 555 may be an example of connector 470 or connector 485 described with reference to fig. 4B and 4C. Memory array 500 may include a plurality of connectors 555 based at least in part on the number of lines of memory cells in memory array 500.

By reducing the number of contacts in connector 555, the die area occupied by connector 555 may be reduced. In some examples, this may provide additional die area to be occupied by additional memory cells or other components.

The plate lines 530, 535 may be coupled to the substrate at another location than the connector 555. In some examples, a contact (not shown) may couple the first plate line 530 to the substrate 505. The contact may extend from the first plate line 530 beyond an edge of a footprint of the memory cell array and couple to the substrate 505 outside of the footprint. In some examples, the contacts may be located in the footprint of the memory cell array, but at a different location than connector 555. In some examples, the contact between the first plate line 530 and the substrate 505 may be positioned within one of the connectors 555 of the memory array 500. As such, the connector 555, including the contacts between the first plate line 530 and the substrate 505, may define a size greater than size 565. A contact (not shown) may couple the second plate line 535 to the substrate 505. This contact may similarly be embodied as a contact for the first plateline 530 and a full description of the features of the contact for the second plateline 535 is not repeated here. In some examples, the plate driver may be positioned outside of a footprint of the three-dimensional ferroelectric memory cell array. Additionally or alternatively, the access lines may be coupled to the plate driver and may extend from the plate driver to at least an edge of a footprint of the three-dimensional array. In some examples, the plate driver may be positioned within a footprint of the memory cell array.

FIG. 6 illustrates an example of a memory array 600, 640, 670 supporting board node configuration and operation of the memory array, according to various embodiments of the invention. The memory array 600 includes a single plate line 630 associated with both the first deck 610 and the second deck 615 of the memory array 600.

The plate lines of the first level 610 and the plate lines of the second level 615 may be coupled together by contacts 635. In some examples, the contact 635 may be part of one continuous plate line 630. In some examples, contact 635 may be an example of a via extending between two separate plate lines. In some examples, contact 635 may be an example of a shunt line extending between two separate plate lines.

Contacts (not shown) may couple plate lines 630 to substrate 605. The contacts may be examples of contacts for the first plateline 530 and the second plateline 535 described with reference to fig. 5B. As such, a full description of the contacts is not repeated here.

Memory array 600 may include connectors (not shown) for digit lines 625. The connectors may include contacts through levels that may otherwise be occupied by other components, such as digit lines, memory cells, and plate lines.

Memory array 600 may be an example of memory arrays 400 and/or 500 described with reference to fig. 4-5. As such, a full description of at least some of the components of the memory array 600 is not repeated here. The memory array 600 may include a substrate 605, a first level 610 of memory cells 620, and a second level 615 of memory cells 620. Memory cells 620 may be coupled to digit lines 625 and plate lines 630. The substrate 605 may be an example of the substrate 405 and/or 505 described with reference to fig. 4-5. The levels 610, 615 of the memory cells 620 may be examples of the levels 410, 415, 510, 515 described with reference to fig. 4-5. Memory cell 620 may be an example of memory cells 105, 420, 520 described with reference to fig. 1, 2, and 4-5. Digit line 625 may be an example of digit lines 115, 425, 525 described with reference to fig. 1, 2, and 4-5.

Memory array 640 illustrates an example of a configuration of a memory array. Memory array 640 may include a single common plate line 665 positioned between first level 645 and second level 650 of memory cells 655. Contacts (not shown) may couple the plate lines 630 to a substrate (not shown). The contacts may be examples of contacts for plate lines 530, 535, 530, 630 described with reference to fig. 5-6. As such, a full description of the contacts is not repeated here. Memory array 640 may include connectors (not shown) for digit lines 660. The connectors may include contacts through levels that may otherwise be occupied by other components, such as digit lines, memory cells, and plate lines.

Memory array 640 may be an example of memory arrays 400, 500, and/or 600 described with reference to fig. 4-6. Memory array 640 may include a substrate (not shown), a first level 645 of memory cells 655 and a second level 650 of memory cells 655. Memory cell 655 may be coupled to digit line 660 and plate line 665. The substrate may be an example of the substrates 405, 505, and/or 605 described with reference to fig. 4-6. The levels 645, 650 of the memory cells 655 may be examples of the levels 410, 415, 510, 515, 610, 615 described with reference to fig. 4-6. Memory cell 655 may be an example of memory cells 105, 420, 520, 620 described with reference to fig. 1, 2, and 4-6. Digit line 660 may be an example of digit lines 115, 425, 525, and/or 625 described with reference to fig. 1, 2, and 4-6.

The memory array 670 illustrates an example of a configuration of a memory array. The memory array 670 can include a single common digitline 690 positioned between the first level 675 and the second level 680 of memory cells 685. Contacts (not shown) may couple plate lines 695-a to a substrate (not shown). In some examples, plate line 695-a is coupled to plate line 695-b to form a single plate associated with both tiers 675, 680. The contacts may be examples of contacts for plate lines 530, 535, 530, 630, 665 described with reference to fig. 5-6. As such, a full description of the contacts is not repeated here. Memory array 670 may include connectors (not shown) for digit lines 690. The connectors may include contacts through levels that may otherwise be occupied by other components, such as digit lines, memory cells, and plate lines.

Memory array 670 may be an example of memory arrays 400, 500, 600, and/or 640 described with reference to fig. 4-6. As such, a full description of at least some of the components of the memory array 670 is not repeated here. The memory array 670 can include a substrate (not shown), a first level 675 of memory cells 685, and a second level 680 of memory cells 685. Memory cells 685 may be coupled to digit lines 690 and plate lines 695. The substrate may be an example of the substrates 405, 505, and/or 605 described with reference to fig. 4-6. The levels 675, 680 of the memory cells 685 may be examples of the levels 410, 415, 510, 515, 610, 615, 675, 650 described with reference to figures 4-6. Memory unit 685 may be an example of memory units 105, 420, 520, 620, 655 described with reference to fig. 1, 2, and 4-6. Digit line 690 may be an example of digit lines 115, 425, 525, 625, and/or 660 described with reference to fig. 1, 2, and 4-6.

In other examples, other configurations of memory arrays are contemplated. For example, the memory arrays 400, 500, 600 may be flipped upside down so that the plate lines are closest to the substrate in each level rather than the digit lines. Each of memory arrays 500, 600, 640, 670, and/or other configurations of memory arrays may include connectors that define a size that is smaller than size 495.

FIG. 7 illustrates an example of a timing diagram 700 supporting board node configuration and operation of a memory array, according to various embodiments of the invention. Timing diagram 700 illustrates access operations that may be performed on memory cells including one plate line configuration discussed with reference to fig. 4-6. More specifically, timing diagram 700 illustrates read operations performed on selected memory cells (e.g., memory cells 420, 520, 620, 655, 685) of a memory array. The principles of timing diagram 700 may be applied in the context of a write operation.

At time t0, memory controller 140 may initiate an access operation to a selected memory cell 105 coupled to a plate line (e.g., plate lines 430, 530, 630, 665, 695) and precondition the circuit. Memory controller 140 may select one or more memory cells coupled to the plate line. At time t0, memory controller 140 may send select signal 705 from zero voltage level V0 to the higher voltage level. In some examples, the higher voltage level is in a range between 2.9 volts and 3.3 volts, 3.0 volts and 3.2 volts, or about 3.1 volts. Select signal 705 may be associated with selecting a selected memory cell.

Before initiating an access operation, memory controller 140 may maintain the plate lines (as represented by plate signal 710) and digit lines (as represented by digit line signal 715) at a non-zero voltage during an idle period. As used herein, an idle period for a selected memory cell may refer to any time period in which an access operation is not performed on the selected memory cell. In some examples, memory controller 140 may apply voltages to the plate lines and digit lines to maintain them at the third voltage level V3. In some examples, plate signal 710 and digit line signal 715 may be maintained at a third voltage level V3 that is greater than zero voltage level V0. In some examples, plate signal 710 and digit line signal 715 may be maintained at a third voltage level V3 that is less than the higher voltage level of select signal 705. During the idle period, the plate signal 710 is depicted as being offset from the third voltage level V3 for illustrative purposes only. The third voltage level V3 may be configured to bias a selected memory cell during an access operation (e.g., a read operation or a write operation).

At time t0, the memory controller 140 may cause the digit line signal 715 to reach the zero voltage level V0 from the third voltage level V3. Memory controller 140 may discharge the digit lines so that digit line signal 715 reaches a zero voltage level V0. Memory controller 140 may discharge the digit line in preparation for the selected memory cell to dump its charge onto the digit line.

At time t1, memory controller 140 may begin forming signals from the selected memory cells. At time t1, memory controller 140 may activate a selection component (e.g., selection component 220) of the selected memory cell. By activating the select component, the capacitor of the selected memory cell can be coupled to the digit line. In some examples, the select component is activated after memory controller 140 determines that digit line signal 715 has dropped to zero voltage level V0.

The voltage levels seen on the digit lines can vary depending on the logic state of the selected memory cell. For example, if the selected memory cell stores a logic '1' as its logic state, the digit line may rise to a higher voltage level than if the selected memory cell stored a logic '0'. The digit line signal 716 represents the voltage level of the digit line when storing a logic '1'. Digit line signal 717 represents the voltage level of the digit line when storing a logic '0'.

At time t2, memory controller 140 may isolate the selected memory cell from ground or virtual ground, thereby causing the circuitry of the memory cell to float. To accomplish this, the memory controller may activate or deactivate various switching components (not shown).

At time t3, memory controller 140 may activate a sensing component (e.g., sensing component 125) to sense the logic state of the selected memory cell. To accomplish this, the memory controller 140 may activate or deactivate various switching components (not shown). Additionally, at time t3, memory controller 140 may cause the voltage level of plate signal 710 to drop to a second voltage level V2 that is less than a third voltage level V3. In some examples, the second voltage level V2 may be configured to bias a selected memory cell during an access operation. Using the sensing components, the memory controller 140 can identify the logic state of the selected memory cell based on the voltage level of the digit line (e.g., digit line signal 716 for a logic '1' or digit line signal 717 for a logic '0'). For example, memory controller 140 may compare the digit line voltage level to a reference voltage (e.g., voltage level V1). If digit line signal 715 is higher than reference voltage V1 (e.g., digit line signal 716), memory controller 140 may identify the logic state as a logic '1'. If the digit line signal 715 is lower than the reference voltage V1 (e.g., digit line signal 717), the memory controller 140 may identify the logic state as a logic '0'.

At time t4, memory controller 140 may perform the sensing portion of the read operation. Memory controller 140 may activate/deactivate a number of switching components (not shown) at time t 4. In some examples, memory controller 140 may perform the sensing portion based on plate signal 710 falling to second voltage level V2. In some examples, the digit line signals 716, 717 may rise to the second voltage level V2 at time t 4.

At time t5, memory controller 140 may complete the sense portion of the read operation and initiate the write back portion of the read operation. In some memory arrays, the act of reading the logic state of a selected memory cell alters the logic state of the selected memory cell. In such scenarios, the read operation of the selected memory cell may include a write-back portion in which the sensed logic state is written back to the selected memory cell. At time t5, memory controller 140 may activate or deactivate a number of switching components (not shown). The precise timing of the activation/deactivation of these switching components may be based on the logic state of the selected memory cells. For example, if the logic state of the selected memory cell is a logic '0', at time t5, the memory controller 140 may cause the digit line signal 717 to reach the zero voltage level V0 from the second voltage level V2. At time t5, memory controller 140 may also maintain plate signal 710 at the second voltage level V2, thereby biasing the selected memory cell to write a logic '0'.

At time t6, memory controller 140 may ground the plate line or virtual ground such that plate signal 710 falls to a zero voltage level V0. At time t6, memory controller 140 may activate or deactivate a number of switching components (not shown). In some examples, grounding the board may be based on completing a write back portion of a logical '0'. In some examples, grounding the plate may be performed before performing a write operation for a logic '1'. For example, if the logic state of the selected memory cell is a logic '1', at time t6, memory controller 140 may drop plate signal 710 from the second voltage level V2 to a zero voltage level V0. At time t6, memory controller 140 may also maintain digit line signal 716 at the second voltage level V2, thereby biasing the selected memory cell to write a logic '1'.

At time t7, memory controller 140 may complete the write-back portion of the read operation. At time t7, memory controller 140 may ground the digit line or virtual ground. This action may not have much effect on the circuit if the digit line carries a digit line signal 717 associated with a logic '0'. If the digit line carries a digit line signal 716 associated with a logic '1', the digit line may reach a zero voltage level V0 from a high voltage level (e.g., V2).

At time t8, memory controller 140 may complete the access operation. At time t8, memory controller 140 may isolate the capacitor of the selected memory cell from the digit line by deactivating the select component. Memory controller 140 may do so by causing word line signal 720 to drop to a zero voltage level V0. Memory controller 140 may also deselect the selected memory cell, thereby causing select signal 705 to fall to a zero voltage level V0. In some examples, time t8 begins another idle period. In some examples, memory controller 140 may deselect memory cells based on determining that the digit line is at zero voltage level V0.

At time t8, memory controller 140 may again apply voltages to the plates and digit lines based on the access operation being completed. Applying the voltages may cause the digit line signal 715 and the plate signal 710 to rise from the zero voltage level V0 to a third voltage level V3 during idle periods between access operations. In this manner, the memory controller 140 may maintain the digit lines and plate lines at non-zero voltages between access operations performed on selected memory cells.

FIG. 8 illustrates an example of a circuit 800 supporting board node configuration and operation of a memory array, according to various embodiments of the invention. The circuit 800 may be configured to couple the digit line 805 of an unselected memory cell to the plate line 820. The circuit 800 may be implemented in conjunction with any of the memory arrays 100, 400, 500, 600, 640, 670 described with reference to fig. 1-6. Plate line 820 may be an example of plate lines 210, 430, 530, 535, 630, 665, 695 described with reference to fig. 2-6. Digit line 805 may be an example of digit lines 115, 425, 525, 625, 660, 690 described with reference to fig. 1-6.

In some examples, plate lines 820 may be capacitively coupled to unselected digit lines 805 during an access operation. This capacitive coupling may induce a transient voltage on the plate 820 or the unselected digit line 805. The transient voltage may interfere with the logic state of unselected memory cells coupled to the unselected digit lines 805. To mitigate the magnitude and type of transient voltages, the digit lines 805 may be selectively coupled to the board 820 through shunt lines and shunt switching components 825. Memory controller 140 may activate shunt switching component 825-a via select control line 830-a.

During an access operation, one of the memory cells (not shown) in the circuit 800 may be selected to perform the access operation. As part of an access operation, the digit line 805 associated with the selected memory cell can be coupled to the sense component 125-c. For example, the digit line 805-a may be coupled to a sense amplifier using a switching component 810-a. The memory controller 140 may activate the switching component 810-a via a select control line 815-a.

In some examples, the sensing component 125-c may be coupled to a single memory cell (the memory cell associated with digit line 805-a) while the remaining memory cells (the memory cells associated with digit lines 805-b through 805-h) are coupled to the plate 820. To achieve this result, the memory controller may activate a single switching component 810 (e.g., switching component 810) and simultaneously activate seven other shunt switching components 825 (e.g., shunt switching components 825-b through 825-h). Such actions may reduce transient voltages induced on unselected digital lines.

In some examples, memory controller 140 may be configured to equalize the voltages of unselected digit lines 805 and plate lines 820. For example, prior to activating the shunt switching component 825, the memory controller may identify the voltage level of the plateline 820 and apply the voltage level of the plateline 820 to the unselected digit line 805. In some examples, capacitive coupling may be reduced by equalizing the voltages of the unselected digit lines 805 and the pad 820 without activating the shunt switching component 825.

In some examples, the shunt switching component 825 may be in a portion of the substrate 405, 505, 605 below the array described with reference to fig. 4-6. The shunt switching component may be part of a support component positioned in the substrate 405, 505, 605. In some examples, shunt switching component 825 may be positioned proximate to an edge of the array. In some examples, shunt switching component 825 may be coupled to the digit lines and/or the plate lines through connector 470/485.

FIG. 9 shows a block diagram 900 of a memory array 905 supporting board node configuration and operation of the memory array, according to various embodiments of the invention. The memory array 905 may be referred to as an electronic memory device and may be an example of components of the memory controller 140 as described with reference to FIG. 1.

The memory array 905 may include one or more memory cells 910, a memory controller 915, word lines 920, plate lines 925, reference components 930, sense components 935, digit lines 940, and latches 945. These components may be in electronic communication with each other and may perform one or more of the functions described herein. In some cases, memory controller 915 may include a biasing component 950 and a timing component 955.

Memory controller 915 may be in electronic communication with wordline 920, digit line 940, sense component 935, and plate line 925, which may be examples of wordline 110, digit line 115, sense component 125, and plate line 210 described with reference to fig. 1 and 2. The memory array 905 may also include a reference component 930 and a latch 945. The components of the memory array 905 may be in electronic communication with each other and may perform portions of the functions described with reference to fig. 1-8. In some cases, the reference component 930, the sense component 935, and the latch 945 can be components of the memory controller 915.

In some examples, digit line 940 is in electronic communication with sensing component 935 and the ferroelectric capacitors of ferroelectric memory cell 910. Ferroelectric memory cell 910 may be writable in a logic state (e.g., a first or second logic state). Word line 920 may be in electronic communication with memory controller 915 and the select components of ferroelectric memory cell 910. Plate line 925 may be in electronic communication with memory controller 915 and the plates of the ferroelectric capacitors of ferroelectric memory cell 910. The sense component 935 may be in electronic communication with a memory controller 915, a digit line 940, a latch 945, and a reference line 960. The reference component 930 may be in electronic communication with the memory controller 915 and the reference line 960. Sense control lines 965 may be in electronic communication with sense component 935 and memory controller 915. These components may also be in electronic communication with other components (in addition to those not listed above) both inside and outside the memory array 905 via other components, connections, or buses.

The memory controller 915 may be configured to activate the word line 920, plate line 925, or digit line 940 by applying voltages to those various nodes. For example, bias component 950 may be configured to apply a voltage to operate memory cell 910 to read or write to memory cell 910 as described above. In some cases, the memory controller 915 may include a row decoder, a column decoder, or both as described with reference to fig. 1. This may enable memory controller 915 to access one or more memory cells 105. Bias component 950 can also provide a voltage potential to reference component 930 in order to generate a reference signal for sensing component 935. In addition, bias component 950 can provide a voltage potential for operating sensing component 935.

In some cases, the memory controller 915 may perform its operations using a timing component 955. For example, timing component 955 may control the timing of various word line selections or plate biases, including the timing for switching and voltage application to perform memory functions discussed herein (e.g., read and write). In some cases, timing component 955 may control operation of bias component 950.

Reference component 930 may include various components to generate a reference signal for sensing component 935. The reference component 930 may include circuitry configured to generate a reference signal. In some cases, reference component 930 may be implemented using other ferroelectric memory cells 105. Sensing component 935 may compare the signal from memory cell 910 (via digit line 940) to a reference signal from reference component 930. Upon determining the logic state, the sense component may then store the output in latch 945, where it may be used according to the operation of the electronic device of which the memory array 905 is a part. Sense component 935 may include a sense amplifier in electronic communication with the latch and the ferroelectric memory cell.

The memory controller 915 may be examples of portions of the memory controller 1115 described with reference to fig. 11. Memory controller 915 and/or at least some of its various subcomponents may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions of memory controller 915 and/or at least some of its various subcomponents may be performed by: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in this disclosure. Memory controller 915 and/or at least some of its various subcomponents may be physically located at various locations, including portions that are distributed such that functions are performed by one or more physical devices at different physical locations. In some examples, memory controller 915 and/or at least some of its various subcomponents may be separate and distinct components according to various embodiments of the invention. In other examples, memory controller 915 and/or at least some of its various subcomponents may be combined with one or more other hardware components, including but not limited to I/O components, transceivers, network servers, another computing device, one or more other components described in this disclosure, or a combination thereof, in accordance with various embodiments of the present disclosure.

Memory controller 915 may apply a first voltage to a plate and an access line each coupled to a ferroelectric memory cell during a time period prior to an access operation for the ferroelectric memory cell, select the ferroelectric memory cell for the access operation via a second access line coupled to the ferroelectric memory cell, and discharge the access line based on selecting the ferroelectric memory cell for the access operation. In some examples, memory controller 915 may couple plate line 925 to an unselected digit line associated with plate line 925. In some cases, the memory controller 915 may activate a plurality of shunt switching components coupled to the plate lines 925 and the unselected digit lines. In some cases, the memory controller 915 may identify the voltage level of the plate line 925. In some cases, the memory controller 915 may apply the voltage level of the plate line 925 to the unselected digit lines when the plate line 925 is coupled to the unselected digit lines.

In some cases, the memory array 905 may include various means for operating the memory array 905. For example, the memory array 905 and/or the memory controller 915 may include means for performing the functions described above with reference to fig. 10.

The memory array 905 may include: means for applying a first voltage to a plate and an access line each coupled to a ferroelectric memory cell during a time period prior to an access operation for the ferroelectric memory cell; means for selecting the ferroelectric memory cell for the access operation via a second access line coupled to the ferroelectric memory cell; and means for discharging the access line based at least in part on selecting the ferroelectric memory cell for the access operation.

Some examples of the memory array 905 described above may further include processes, features, means, or instructions for maintaining a first voltage on the plate when the access line can be discharged. Some examples of the memory array 905 described above may further include processes, features, means, or instructions for activating a select component of a ferroelectric memory cell based at least in part on selecting the ferroelectric memory cell and discharging an access line.

Some examples of the memory array 905 described above may further include processes, features, means, or instructions for discharging ferroelectric capacitors of ferroelectric memory cells onto the access lines based at least in part on discharging the access lines as part of an access operation. Some examples of the memory array 905 described above may further include processes, features, means, or instructions for discharging the plate from a first voltage to a second voltage less than the first voltage based at least in part on activating a sensing component coupled to the access line.

Some examples of the memory array 905 described above may further include processes, features, means, or instructions for sensing a second voltage on an access line associated with a charge of a ferroelectric memory cell based at least in part on activating a sensing component coupled to the access line as part of an access operation.

Some examples of the memory array 905 described above may further include processes, features, means, or instructions for coupling a plate to unselected access lines associated with the plate. In some examples of the memory array 905 described above, the coupling plate further comprises: a plurality of shunt switching components coupled to the plate and unselected access lines are activated.

Some examples of the memory array 905 described above may further include processes, features, means, or instructions for identifying a voltage level of a plate. Some examples of the above-described methods and apparatus may further include processes, features, means, or instructions for applying a voltage level of a plate to an unselected access line when the plate may be coupled to the unselected access line.

Some examples of the memory array 905 described above may further include processes, features, means, or instructions for discharging the plate during a write-back portion of an access operation. Some examples of the memory array 905 described above may further include processes, features, means, or instructions for applying a first voltage to the plate and the access line based at least in part on the access operation being completed. In some examples of the memory array 905 described above, the plates and access lines may be maintained at non-zero voltages between access operations performed on ferroelectric memory cells.

FIG. 10 shows a block diagram 1000 of a memory controller 1015 supporting the board node configuration and operation of a memory array, according to various embodiments of the invention. The memory controller 1015 may be an example of portions of the memory controllers 140, 915, or 1115 described with reference to fig. 1, 9, and 11. The memory controller 1015 may include a bias component 1020, a timing component 1025, an idle period manager 1030, an access operation manager 1035, a discharge manager 1040, a sense manager 1045, and a shunt manager 1050. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

Idle cycle manager 1030 may apply a first voltage to a plate node and a digit line each coupled to a ferroelectric memory cell during a time period prior to an access operation for the ferroelectric memory cell and based on completion of the access operation. In some cases, the plate node and the digit line are maintained at a non-zero voltage between access operations performed on the ferroelectric memory cell.

The access operation manager 1035 may select a ferroelectric memory cell for an access operation via a word line coupled to the ferroelectric memory cell, activate a select component of the ferroelectric memory cell based on selecting the ferroelectric memory cell and discharging the digit line, and discharge the plate node from a first voltage to a second voltage less than the first voltage based on activating a sense component coupled to the digit line.

Discharge manager 1040 may discharge the digit line based on selecting the ferroelectric memory cell for an access operation, maintain a first voltage on the plate node while discharging the digit line, and discharge the plate node during a write back portion of the access operation.

The sensing manager 1045 may discharge the ferroelectric capacitor of the ferroelectric memory cell onto the digit line based on discharging the digit line as part of an access operation and sense a second voltage on the digit line associated with a charge of the ferroelectric memory cell based on activating a sense component coupled to the digit line as part of the access operation.

The shunt manager 1050 may couple a plate node to an unselected digit line associated with the plate node, identify a voltage level of the plate node, and apply the voltage level of the plate node to the unselected digit line when the plate node is coupled to the unselected digit line. In some cases, the coupling plate node further comprises: a set of shunt switching components coupled to the board node and the unselected digit lines are activated.

Figure 11 shows a diagram of a system 1100 including a device 1105, the device 1105 supporting board node configuration and operation of a memory array, according to various embodiments of the invention. The means 1105 may be an example of, or include a memory controller 140 or a component of a memory controller 915 as described above, for example, with reference to fig. 1 and 9. Device 1105 may include components for two-way voice and data communications, including components for transmitting and receiving communications, including a memory controller 1115, a memory unit 1120, a basic input/output system (BIOS) component 1125, a processor 1130, an I/O controller 1135, and peripheral components 1140. These components may be in electronic communication via one or more buses, such as bus 1110.

The memory controller 1115 can operate one or more memory cells as described herein. Specifically, the memory controller 1115 can be configured to support board configuration and operation of the memory array. In some cases, the memory controller 1115 can include a row decoder, a column decoder, or both (not shown) as described with reference to fig. 1. Memory unit 1120 may store information (i.e., in the form of logic states) as described herein.

The BIOS component 1125 is a software component that includes a BIOS operated as firmware that can initialize and run various hardware components. The BIOS component 1125 may also manage data flow between the processor and various other components (e.g., peripheral components, input/output control components, etc.). The BIOS component 1125 may include programs or software stored in Read Only Memory (ROM), flash memory, or any other non-volatile memory.

Processor 1130 may include intelligent hardware devices such as general purpose processors, DSPs, Central Processing Units (CPUs), microcontrollers, ASICs, FPGAs, programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combinations thereof. In some cases, the processor 1130 may be configured to operate the memory array using a memory controller. In other cases, a memory controller may be integrated into processor 1130. The processor 1130 may be configured to execute computer readable instructions stored in memory to perform various functions (e.g., functions or tasks to support board configuration and operation of a memory array).

I/O controller 1135 may manage input and output signals for device 1105. The I/O controller 1135 may also manage peripheral devices that are not integrated into the device 1105. In some cases, I/O controller 1135 may represent a physical connection or port to an external peripheral device. In some cases, I/O controller 1135 may utilize an operating system, for exampleOr another known operating system. In other cases, I/O controller 1135 may represent or interact with: modem, keyboard, mouse, touch screen, or similar device. In some cases, I/O controller 1135 may be implemented as part of a processor. In some cases, a user may interact with the device 1105 via the I/O controller 1135 or via hardware components controlled by the I/O controller 1135.

Peripheral components 1140 may include any input or output device or interface for such devices. Examples may include disk controllers, sound controllers, graphics controllers, ethernet controllers, modems, Universal Serial Bus (USB) controllers, serial or parallel ports, or peripheral card slots, such as Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slots.

FIG. 12 shows a flow diagram illustrating a method 1200 of plate node configuration and operation for a memory array, according to various embodiments of the invention. The operations of method 1200 may be implemented by memory controller 915 or components thereof as described herein. For example, the operations of method 1200 may be performed by a memory controller as described with reference to fig. 9-11. In some examples, the memory controller 915 may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller 915 may perform portions of the functions described below using dedicated hardware.

At block 1205, the memory controller 915 may apply a first voltage to a plate node and a digit line each coupled to a ferroelectric memory cell during a time period prior to an access operation for the ferroelectric memory cell. The operations of block 1205 may be performed in accordance with the methods described with reference to fig. 1 through 13. In a particular example, portions of the operations of block 1205 may be performed by an idle cycle manager as described with reference to fig. 9-11.

At block 1210, the memory controller 915 may select a ferroelectric memory cell for an access operation via a word line coupled to the ferroelectric memory cell. The operations of block 1210 may be performed according to the methods described with reference to fig. 1-13. In a particular example, portions of the operations of block 1210 may be performed by an access operation manager as described with reference to fig. 9-11.

At block 1215, the memory controller 915 may discharge the digit line based at least in part on selecting the ferroelectric memory cell for an access operation. The operation of block 1215 may be performed in accordance with the methods described with reference to fig. 1-13. In a particular example, portions of the operations of block 1215 may be performed by the discharge manager as described with reference to fig. 9-11.

In some cases, the method may further comprise: a first voltage is applied to a plate node and a digit line each coupled to a ferroelectric memory cell during a time period prior to an access operation for the ferroelectric memory cell. In some cases, the plate and digit line are maintained at a non-zero voltage between access operations performed on the ferroelectric memory cell. In some cases, the method may further comprise: the digit line is discharged based at least in part on selecting the ferroelectric memory cell for an access operation. In some cases, the method may further comprise: the first voltage on the plate node is maintained while the digit line is discharged. In some cases, the method may further comprise: activating a select component of the ferroelectric memory cell based at least in part on selecting the ferroelectric memory cell and discharging the digit line. In some cases, the method may further comprise: discharging a ferroelectric capacitor of a ferroelectric memory cell onto a digit line based at least in part on discharging the digit line as part of an access operation.

In some cases, the method may further comprise: the plate node is discharged from a first voltage to a second voltage less than the first voltage based at least in part on activating a sense component coupled to the digit line. In some cases, the method may further comprise: the ferroelectric memory cell is selected for an access operation via a word line coupled to the ferroelectric memory cell. In some cases, the method may further comprise: a plate node is coupled to an unselected digit line associated with the plate node. In some cases, the coupling plate node further comprises: a plurality of shunt switching components coupled to the board nodes and the unselected digit lines are activated. In some cases, the method may further comprise: the voltage level of the panel node is identified. In some cases, the method may further comprise: the voltage level of the plate node is applied to the unselected digit lines when the plate node is coupled to the unselected digit lines.

In some cases, the method may further comprise: the plate node is discharged during a write back portion of the access operation. In some cases, the method may further comprise: a first voltage is applied to the plate node and the digit line based at least in part on completion of the access operation. In some cases, the method may further comprise: a second voltage on the digit line is sensed as part of the access operation based at least in part on activating a sensing component coupled to the digit line, the second voltage associated with a charge of the ferroelectric memory cell.

FIG. 13 shows a flow diagram illustrating a method 1300 for plate node configuration and operation of a memory array, according to various embodiments of the invention. The operations of method 1300 may be implemented by memory controller 915 or components thereof as described herein. For example, the operations of method 1300 may be performed by a memory controller as described with reference to fig. 9-11. In some examples, the memory controller 915 may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller 915 may perform portions of the functions described below using dedicated hardware.

At block 1305, the memory controller 915 may apply a first voltage to a plate node and a digit line each coupled to a ferroelectric memory cell during a time period prior to an access operation for the ferroelectric memory cell. The operations of block 1305 may be performed in accordance with the methods described with reference to fig. 1-13. In a particular example, portions of the operations of block 1305 may be performed by an idle cycle manager as described with reference to fig. 9-11.

At block 1310, the memory controller 915 may select the ferroelectric memory cell for an access operation via a word line coupled to the ferroelectric memory cell. The operations of block 1310 may be performed in accordance with the methods described with reference to fig. 1-13. In a particular example, portions of the operations of block 1310 may be performed by an access operation manager as described with reference to fig. 9-11.

At block 1315, the memory controller 915 may couple the board node to the unselected digit line associated with the board node. The operations of block 1315 may be performed in accordance with the methods described with reference to fig. 1-13. In a particular example, portions of the operations of block 1315 may be performed by an access operation manager as described with reference to fig. 9-11.

At block 1320, the memory controller 915 may discharge the digit line based at least in part on selecting the ferroelectric memory cell for the access operation. The operations of block 1320 may be performed according to the method described with reference to fig. 1-13. In a particular example, portions of the operations of block 1320 may be performed by a discharge manager as described with reference to fig. 9-11.

At block 1325, the memory controller 915 may apply a first voltage to the plate node and the digit line based at least in part on completion of the access operation. The operations of block 1325 may be performed in accordance with the methods described with reference to fig. 1-13. In a particular example, portions of the operations of block 1325 may be performed by an idle cycle manager as described with reference to fig. 9-11.

An apparatus is disclosed. The apparatus may include: means for applying a first voltage to a plate node and a digit line each coupled to a ferroelectric memory cell during a time period prior to an access operation for the ferroelectric memory cell; means for selecting the ferroelectric memory cell for the access operation via a word line coupled to the ferroelectric memory cell; and means for discharging the digit line based at least in part on selecting the ferroelectric memory cell for the access operation.

Some examples may further include means for coupling the plate node to an unselected digit line associated with the plate node. Some examples may further include means for maintaining the first voltage on the plate node when the digit line can be discharged. Some examples may further include means for activating a select component of the ferroelectric memory cell based at least in part on selecting the ferroelectric memory cell and discharging the digit line. Some examples may further include means for discharging a ferroelectric capacitor of the ferroelectric memory cell onto the digitline based at least in part on discharging the digitline as part of the access operation.

Some examples may further include means for discharging the plate node from the first voltage to a second voltage less than the first voltage based at least in part on activating a sensing component coupled to the digit line. Some examples may further include means for sensing a second voltage on the digit line based at least in part on activating a sensing component coupled to the digit line as part of the access operation, the second voltage associated with a charge of the ferroelectric memory cell.

In some examples, coupling the board node further comprises means for activating a plurality of shunt switching components coupled to the board node and the unselected digit line. Some examples may further include means for identifying a voltage level of the plate node. Some examples may further include means for applying the voltage level of the plate node to the unselected digit line when the plate node can be coupled to the unselected digit line. Some examples may further include means for discharging the plate node during a write back portion of the access operation.

Some examples may further include means for applying the first voltage to the plate node and the digit line based at least in part on completion of the access operation. In some examples, the plate node and the digit line may be maintained at a non-zero voltage between access operations performed on the ferroelectric memory cells.

It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, embodiments from two or more of the methods may be combined.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate signals as a single signal; however, those skilled in the art will appreciate that the signals may represent a signal bus, where the bus may have various bit widths.

As used herein, the term "virtual ground" refers to a node of a circuit that is held at a voltage of approximately zero volts (0V) but is not directly connected to ground. Therefore, the voltage of the virtual ground may temporarily fluctuate and return to substantially 0V in a steady state. The virtual ground may be implemented using various electronic circuit elements, such as a voltage divider composed of an operational amplifier and a resistor. Other embodiments are also possible. "virtual ground" or "virtually grounded" means connected to approximately 0V.

The terms "electronic communication" and "coupled" refer to the relationship between components that support the flow of electrons between the components. This may include direct connections between the components or may include intermediate components. Components that are in electronic communication or coupling with each other may or may not actively exchange electrons or signals (e.g., in powered-on circuitry), but may be configured and operable to exchange electrons or signals upon powering-on the circuitry. By way of example, two components physically connected via a switch (e.g., a transistor) may be in electronic communication or may be coupled regardless of the state of the switch (i.e., open or closed).

As used herein, the term "substantially" means that a modified property (e.g., a verb or adjective that is substantially modified by the term) need not be absolute, but rather close enough to achieve the benefit of the property.

As used herein, the term "electrode" may refer to an electrical conductor, and in some cases may be employed as an electrical contact to a memory cell or other component of a memory array. The electrodes may include traces, wires, conductive lines, conductive layers, and the like that provide conductive paths between elements or components of the memory array 100.

The term "isolated" refers to a relationship between components between which electrons are not currently able to flow; if there is an open circuit between the components, the components are isolated from each other. For example, when a switch is open, two components physically connected by the switch may be isolated from each other.

As used herein, the term "short circuit" refers to a relationship between components in which a conductive path is established between the components in question via activation of a single intermediate component between the two components. For example, a first component shorted to a second component may exchange electrons with the second component when a switch between the two components is closed. Thus, a short may be a dynamic operation that enables charge to flow between components (or lines) in electronic communication.

The devices discussed herein, including the memory array 100, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-Sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorous, boron or arsenic. The doping may be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

The transistor or transistors discussed herein may represent Field Effect Transistors (FETs) and include three terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components through conductive materials (e.g., metals). The source and drain may be conductive and may comprise heavily doped (e.g., degenerated) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulated gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor may be "off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

The illustrations set forth herein in connection with the figures describe example configurations and are not meant to be all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," and is not "preferred" or "advantageous over other examples. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description may apply to any of the similar components having the same first reference label, regardless of the second reference label.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various illustrative blocks and modules described herein in connection with the present invention may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a Digital Signal Processor (DSP) and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the invention and the following claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement a function may also be physically located at various locations, including portions that are distributed such that the function is implemented at different physical locations. Also, as used herein (including in the claims), "or" as used in a list of items (for example, a list of items preceded by a phrase such as "at least one of … …" or one or more of "… …") indicates an inclusive list such that, for example, a list of at least one of A, B or C means a or B or C or AB or AC or BC or ABC (i.e., a and B and C). Also, as used herein, the phrase "based on" should not be construed as a reference to a set of closed conditions. For example, an exemplary step described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

Computer-readable media includes both non-transitory computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media may comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), Compact Disc (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that may be used to carry or store desired program code means in the form of instructions or data structures that may be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, magnetic and optical disks include: CD. Laser discs, optical discs, Digital Versatile Discs (DVDs), floppy discs, and blu-ray discs where discs usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the invention. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.