阅读说明：本技术 存储装置及其测试读写方法 (Storage device and test read-write method thereof ) 是由 中冈裕司 于 2018-06-19 设计创作，主要内容包括：本发明提供一种存储装置及其测试读写方法。预充电压控制电路根据预充参考电压产生第一预充电压以及第二预充电压。感测放大电路耦接于位线与互补位线之间,用以感测耦接于位线的存储单元的数据,并且耦接预充电压控制电路,以使位线与互补位线分别接收第一预充电压与第二预充电压,其中,在预充操作中,第一预充电压与第二预充电压的电压电平相同,在预充操作之后的测试写入感测期间与测试读取感测期间,预充电压控制电路提供给位线与互补位线的第一预充电压以及第二预充电压的电压电平不同。(The invention provides a storage device and a test read-write method thereof. The pre-charging voltage control circuit generates a first pre-charging voltage and a second pre-charging voltage according to the pre-charging reference voltage. The sense amplifier circuit is coupled between the bit line and the complementary bit line for sensing data of the memory cell coupled to the bit line, and coupled to the precharge voltage control circuit, so that the bit line and the complementary bit line receive a first precharge voltage and a second precharge voltage, respectively, wherein the first precharge voltage and the second precharge voltage have the same voltage level during the precharge operation, and the precharge voltage control circuit provides the bit line and the complementary bit line with different voltage levels during the test write sensing period and the test read sensing period after the precharge operation.)

1. A memory device, comprising:

a precharge voltage control circuit generating a first precharge voltage and a second precharge voltage according to the precharge reference voltage; and

a sense amplifier coupled between a bit line and a complementary bit line for sensing data of a memory cell coupled to the bit line, and the sense amplifier is coupled to the precharge voltage control circuit such that the bit line and the complementary bit line receive the first precharge voltage and the second precharge voltage, respectively,

wherein, in a precharge operation, the first precharge voltage and the second precharge voltage have the same voltage level, and the precharge voltage control circuit provides the bit line and the complementary bit line with different voltage levels of the first precharge voltage and the second precharge voltage during a test write sensing period and a test read sensing period after the precharge operation.

2. The memory device of claim 1, wherein the sense amplification circuit comprises:

a first switch having a first terminal receiving the first precharge voltage and a second terminal coupled to the bit line and controlled by a first precharge enable signal;

a second switch having a first terminal receiving the second precharge voltage and a second terminal coupled to the complementary bit line and controlled by the first precharge enable signal;

a third switch coupled between the bit line and the complementary bit line and controlled by a second precharge enable signal; and

a sensing circuit coupled between the bit line and the complementary bit line for amplifying a voltage difference between the bit line and the complementary bit line.

3. The storage device of claim 2, further comprising:

a pre-charge enable control circuit coupled to the sense amplifier circuit for generating the first pre-charge enable signal and the second pre-charge enable signal according to a pre-charge enable signal,

wherein the first pre-charge enable signal switches a voltage level and the second pre-charge enable signal has a logic level different from the first pre-charge enable signal when a test write operation and a test read operation are performed on the memory cell, and the second pre-charge enable signal switches the voltage level to restore the same logic level as the first pre-charge enable signal after the test write operation and the test read operation are completed.

4. The storage device of claim 1, further comprising:

a test comparison circuit coupled to the precharge voltage control circuit for comparing one of the first precharge voltage and the second precharge voltage with a test reference voltage to generate a test result,

wherein the test result indicates that the data sensing of the memory cell is successful when one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, and indicates that the data sensing of the memory cell is failed when both the first precharge voltage and the second precharge voltage are less than the test reference voltage.

5. The storage device of claim 4, wherein a voltage level of the test reference voltage is higher than the pre-charge reference voltage and less than a supply voltage.

6. The memory device of claim 5, wherein a voltage value of the test result is substantially equal to one of the power supply voltage and a ground voltage when one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, and substantially equal to the other of the power supply voltage and the ground voltage when both the first precharge voltage and the second precharge voltage are less than the test reference voltage.

7. The memory device according to claim 1, wherein in the test write sensing period, one of the first precharge voltage and the second precharge voltage has a voltage value lower than a power supply voltage but higher than the precharge reference voltage, and wherein the other has a voltage value lower than the precharge reference voltage.

8. The memory device of claim 1, wherein the first and second precharge voltages are pulled to substantially equal a supply voltage prior to the test read sensing period when the test read operation is performed on the memory cell.

9. A test read-write method for a memory device, the method being used for performing a test write operation and a test read operation on a memory cell, the test read-write method comprising:

generating a first pre-charge voltage and a second pre-charge voltage according to the pre-charge reference voltage;

causing a bit line and a complementary bit line to receive the first precharge voltage and the second precharge voltage, respectively,

wherein, in a precharge operation, the first precharge voltage and the second precharge voltage have the same voltage level, and the precharge voltage control circuit provides the bit line and the complementary bit line with different voltage levels of the first precharge voltage and the second precharge voltage during a test write sensing period and a test read sensing period after the precharge operation.

10. The test read-write method according to claim 9, further comprising:

controlling a first switch and a second switch by using a first pre-charge enable signal to determine whether the bit line and the complementary bit line respectively receive the first pre-charge voltage and the second pre-charge voltage;

controlling a third switch by using a second pre-charge enable signal to determine whether to electrically connect the bit line and the complementary bit line; and

a voltage difference of the bit line and the complementary bit line is amplified with a sensing circuit.

11. The test read-write method according to claim 10, further comprising:

generating the first and second precharge enable signals according to a precharge enable signal,

wherein the first pre-charge enable signal switches a voltage level and the second pre-charge enable signal has a logic level different from the first pre-charge enable signal when the test write operation and the test read operation are performed on the memory cell, and the second pre-charge enable signal switches the voltage level to restore the same logic level as the first pre-charge enable signal after the test write operation and the test read operation are completed.

12. The test read-write method according to claim 9, further comprising:

comparing one of the first and second precharge voltages with a test reference voltage to generate a test result,

wherein the test result indicates that the data sensing of the memory cell is successful when one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, and indicates that the data sensing of the memory cell is failed when both the first precharge voltage and the second precharge voltage are less than the test reference voltage.

13. The test read-write method according to claim 12, wherein a voltage level of the test reference voltage is higher than the precharge reference voltage and is less than a power supply voltage.

14. The method of claim 13, wherein the test result has a voltage substantially equal to one of the power voltage and the ground voltage when one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, and the test result has a voltage substantially equal to the other of the power voltage and the ground voltage when both the first precharge voltage and the second precharge voltage are less than the test reference voltage.

15. The test read-write method of claim 9, wherein in the test write sensing period, one of the first precharge voltage and the second precharge voltage has a voltage value lower than a power supply voltage but higher than the precharge reference voltage, and the other has a voltage value lower than the precharge reference voltage.

16. The test read-write method of claim 9, wherein the first pre-charge voltage and the second pre-charge voltage are pulled to be substantially equal to a supply voltage prior to the test read sensing period when the test read operation is performed on the memory cell.

Technical Field

The present invention relates to a semiconductor memory technology, and more particularly, to a memory device capable of reading and writing all sense circuits on a selected word line at once in a parallel test mode (parallel test mode) and a test reading and writing method thereof.

Background

A general semiconductor memory device, such as a Dynamic Random Access Memory (DRAM), is constructed with a sense amplifier connected to a bit line of a memory cell array and capable of accessing data from a selected memory cell and amplifying the data.

In the prior art, when a memory device is tested, for example, in a parallel test mode, a plurality of amplifiers for normal reading and writing are selected at a time, but the memory device cannot be tested by selecting more memory cells than Data lines (Data lines) at a time, so how to select a plurality of sense amplifiers on a word line in one cycle (cycle) to perform the parallel test mode becomes one of the problems to be solved at present.

Disclosure of Invention

The present disclosure relates to memory devices and test read/write methods thereof, which can select a plurality of sense amplifiers on a word line in one cycle (cycle) to perform a parallel test mode.

The present disclosure provides a memory device, comprising: a precharge voltage control circuit and a sense amplifier circuit. The pre-charging voltage control circuit generates a first pre-charging voltage and a second pre-charging voltage according to the pre-charging reference voltage. The sense amplifier circuit is coupled between the bit line and the complementary bit line for sensing data of the memory cell coupled to the bit line, and coupled to the precharge voltage control circuit, so that the bit line and the complementary bit line receive a first precharge voltage and a second precharge voltage, respectively, wherein the first precharge voltage and the second precharge voltage have the same voltage level during the precharge operation, and the precharge voltage control circuit provides the bit line and the complementary bit line with different voltage levels during the test write sensing period and the test read sensing period after the precharge operation.

The present disclosure provides a test read/write method for a memory device, for performing a test write operation and a test read operation on a memory cell, the test read/write method comprising: generating a first pre-charge voltage and a second pre-charge voltage according to the pre-charge reference voltage; the bit line and the complementary bit line respectively receive a first pre-charge voltage and a second pre-charge voltage, wherein, in the pre-charge operation, the voltage levels of the first pre-charge voltage and the second pre-charge voltage are the same, and in the test write sensing period and the test read sensing period after the pre-charge operation, the voltage levels of the first pre-charge voltage and the second pre-charge voltage provided by the pre-charge voltage control circuit for the bit line and the complementary bit line are different.

In order to make the aforementioned and other features and advantages of the disclosure more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram illustrating an array structure of a memory device according to an embodiment of the present disclosure.

FIG. 3 is a block diagram of a control and test circuit according to an embodiment of the present disclosure.

FIG. 4 is a circuit diagram of a sensing control circuit according to an embodiment of the disclosure.

FIG. 5 is a circuit diagram of a test read write circuit according to an embodiment of the present disclosure.

Fig. 6 to 8 are waveform diagrams illustrating test write operations of logic "0" and logic "1" of a memory device according to an embodiment of the present disclosure, respectively.

Fig. 9 to 11 are waveform diagrams illustrating a test read operation of a memory device according to an embodiment of the present disclosure.

FIG. 12 is a waveform diagram illustrating the operation of a memory device writing logic "0" to all memory cells according to another embodiment of the present disclosure.

Description of the reference numerals

100: storage device

110: sensing amplifying circuit

120: control and test circuit

130: memory array

140: x decoder block

150: y decoder block

160: sense amplifier block

200: sensing control circuit

210: pre-charge enable control circuit

220: sense amplifier voltage control circuit

300: test read write circuit

310: precharge voltage control circuit

312: comparator with a comparator circuit

314: latch circuit

320: test comparison circuit

BLT: bit line

BLN: complementary bit line

BLPE 1: precharge enable signal

BLP 1: a first precharge enable signal

BLP 2: second precharge enable signal

HFV: pre-charged reference voltage

HFVT: first pre-charge voltage

HFVN: second pre-charge voltage

INV: inverter with a capacitor having a capacitor element

MC: memory cell

N1: first intermediate node

N2: second intermediate node

NP: SAP output node

NN: SAN output node

NHT: HFVT output node

NHN: HFVN output node

NT: test node

NA 21-NA 23, NA 31-NA 35: NAND gate

NO 31-NO 33: NOR gate

Q1, Q2, Q3, Q4: transistor with a metal gate electrode

Q21-Q25, Q1-Q39: switch with a switch body

And SA: sensing circuit

SE1, SE 2: sense enable signal

SAP: p-channel control voltage

SAN: n-channel control voltage

T: extended write cycle

T1: first switch

T2: second switch

T3: third switch

TG 31-TG 34: transmission gate

TFAIL: test results

TWE: test write enable signal

TDA: testing data signals

TDE: test data enable signal

And (6) TEST: test enable signal

TPIO: testing data line precharge signals

tR: test read sensing period

tW: test write sensing period

TMREF: testing reference voltages

VDD: supply voltage

VSS: ground voltage

VTN: threshold voltage of n-channel transistor

WL: word line

WLn, WLm: word line signal

X12B 13B: column address signal

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram illustrating a memory device according to an embodiment of the disclosure. The memory device 100 includes a word line WL, a bit line BLT, a complementary bit line BLN, a memory cell MC, a sense amplifying circuit 110, and a control and test circuit 120. The control and test circuit 120 is coupled to the sense amplifier circuit 110 to provide a plurality of control signals.

The memory cell MC includes, for example, a memory capacitor (memory capacitor) for storing a data potential and a Metal Oxide Semiconductor Transistor (MOSFET) (not shown) as a switch, wherein a first terminal of the MOS Transistor is coupled to the capacitor, a second terminal of the MOS Transistor is coupled to the bit line BLT, and a gate terminal of the MOS Transistor is coupled to the word line WL. Here, a plurality of memory cells MC are arranged in an array in the direction of a plurality of word lines WL, a plurality of bit lines BLT, and a plurality of complementary bit lines BLN to form a memory array 130. In addition, word line signals WLn and WLm shown in fig. 1 indicate signals on different word lines WL.

The sense amplifier circuit 110 is coupled to a pair of bit lines, i.e., the bit line BLT and the complementary bit line BLN, for sensing data of the memory cell MC, so that a test write operation or a test read operation can be performed on the memory cell MC.

The sense amplifier circuit 110 receives the first pre-charge voltage HFVT, the second pre-charge voltage HFVN, the first pre-charge enable signal BLP1 and the second pre-charge enable signal BLP2 from the control and test circuit 120. The sense amplifier circuit 110 determines whether the bit line BLT and the complementary bit line BLN receive the first pre-charge voltage HFVT and the second pre-charge voltage HFVN respectively according to the first pre-charge enable signal BLP1 and the second pre-charge enable signal BLP2, wherein the first pre-charge voltage HFVT and the second pre-charge voltage HFVN have the same voltage level in the pre-charge operation, so that the bit line BLT and the complementary bit line BLN have the same voltage level, but the first pre-charge voltage HFVT and the second pre-charge voltage HFVN provided by the control and test circuit 120 are different in the test write sensing period and the test read sensing period after the pre-charge operation, and the first pre-charge enable signal BLP1 is different in the time point of switching the voltage level in the test write sensing period and the test read sensing period, so that the voltage difference between the bit line BLT and the complementary bit line BLN is mainly affected by the data released by the memory cell during the sensing process, the voltage difference between the bit line BLT and the complementary bit line BLN in this embodiment is related to the voltage difference between the first pre-charge voltage HFVT and the second pre-charge voltage HFVN. The following examples will provide more detailed descriptions.

The sense amplifying circuit 110 includes a first switch T1, a second switch T2, a third switch T3 and a sensing circuit SA, wherein the first switch T1, the second switch T2 and the third switch T3 are n-channel transistors, but not limited thereto. The first switch T1 has a first terminal (drain) receiving the first precharge voltage HFVT, a second terminal (source) coupled to the bit line BLT, and a gate terminal receiving the first precharge enable signal BLP1 for determining whether to turn on. The second switch T2 has a first terminal (drain) receiving the second precharge voltage HFVN, a second terminal (source) coupled to the complementary bit line BLN, and a gate terminal also receiving the first precharge enable signal BLP1 for determining whether to turn on. The third switch T3 is coupled between the bit line BLT and the complementary bit line BLN, and has its gate terminal receiving the second precharge enable signal BLP 2.

The sensing circuit SA is coupled between the bit line BLT and the complementary bit line BLN for amplifying a voltage difference between the bit line BLT and the complementary bit line BLN according to a p-channel control voltage SAP and an n-channel control voltage SAN received from the control and test circuit 120. In this embodiment, the sensing circuit SA is implemented as a flip-flop having a CMOS inverter comprising two MOS transistors Q1, Q2 and a CMOS inverter comprising two MOS transistors Q3, Q4 connected as a positive feedback circuit.

The first terminals (sources) of the transistors Q1 and Q3 of the sensing circuit SA are coupled to a first intermediate node N1, the first intermediate node N1 receives a p-channel control voltage SAP, the second terminals (sources) of the transistors Q2 and Q4 are coupled to a second intermediate node N2, and the second intermediate node N2 receives an N-channel control voltage SAN. The other ends (drains) of the transistors Q1 and Q2 and the gates of the transistors Q3 and Q4 of the sensing circuit SA are coupled to the bit line BLT, and the other ends (drains) of the transistors Q3 and Q4 and the gates of the transistors Q1 and Q2 are coupled to the complementary bit line BLN, so that the voltage levels of the bit line BLT and the complementary bit line BLN can be pulled up (pull up) or pulled down (pull down) to represent a logic "1" or a logic "0" under the influence of the p-channel control voltage SAP and the n-channel control voltage SAN.

FIG. 2 is a schematic diagram illustrating an array structure of a memory device according to an embodiment of the present disclosure. The embodiment of fig. 2 may be applied to the memory device 100 of fig. 1. Referring to fig. 2, the memory array 130 is composed of memory cells MC at the intersections of a plurality of word lines WL and a plurality of bit lines BLT, and an X decoder block (XDEC)140 and a Y decoder block (YDEC)150 are coupled to the memory array 130 for selecting which memory cells MC are accessed. The memory array 130 is coupled to the sense amplifier block 160, the sense amplifier block 160 is coupled to the control and test circuit 120, the sense amplifier block 160 includes a plurality of the sense amplifier circuits 110, and the control and test circuit 120 and the sense amplifier circuits 110 of the sense amplifier block 160 are disposed in relation to each other as described above with reference to the disclosure of fig. 1.

FIG. 3 is a block diagram of a control and test circuit according to an embodiment of the present disclosure. Referring to fig. 3, the control and test circuit 120 includes a sensing control circuit 200 and a test read/write circuit 300 disposed beside the sensing control circuit 200. The sense control circuit 200 and the test read write circuit 300 are coupled to the sense amplifier circuit 110, and respectively provide a first pre-charge enable signal BLP1, a second pre-charge enable signal BLP2, a p-channel control voltage SAP, an n-channel control voltage SAN, a first pre-charge voltage HFVT and a second pre-charge voltage HFVN. In the test mode, the test read/write circuit 300 generates a test result TFAIL according to a comparison result between one of the first pre-charge voltage HFVT and the second pre-charge voltage HFVN and the test reference voltage TMREF to determine whether any memory cell MC fails. The following embodiments will describe in detail the mechanism for determining whether the memory cell MC fails.

FIG. 4 is a circuit diagram of a sensing control circuit according to an embodiment of the disclosure. Referring to fig. 4, in the present embodiment, the sensing control circuit 200 includes a precharge enable control circuit 210 and a sense amplifier voltage control circuit 220. The precharge enable control circuit 210 is formed by connecting inverters INV21 to INV26 and a nand gate NA21, for example.

Specifically, the input terminal of the inverter INV21 receives the precharge enable signal BLPE1, the precharge enable signal BLPE1 is used to determine when to start precharging the bit BLT and the complementary bit line BLN, the output terminal is coupled to one of the input terminals of the nand gate NA21, the other input terminal of the nand gate NA21 receives the column address signal X12B13B, the column address signal X12B13B is used to select which word line WL is activated (act), the output terminal is coupled to the input terminal of the inverter INV22, the inverter INV22 is connected in series with the inverter INV23, and the inverter INV23 outputs the first precharge enable signal BLP 1. The inverter INV24, the inverter INV25 and the inverter INV26 are sequentially connected in series, the inverter INV24 receives the column address signal X12B13B, and the inverter INV26 outputs the second precharge enable signal BLP 2.

Therefore, the precharge enable control circuit 210 is coupled to the sense amplifier circuit 110, and generates the first precharge enable signal BLP1 and the second precharge enable signal BLP2 according to the precharge enable signal BLPE1 and the column address signal X12B13B for providing to the sense amplifier circuit 110. The precharge enable control circuit 210 may control the first precharge enable signal BLP1 to switch a voltage level and the logic level of the second precharge enable signal BLP2 to be different from the first precharge enable signal BLP1 when the test write operation and the test read operation are performed on the memory cell MC, and the precharge enable control circuit 210 switches the voltage level of the second precharge enable signal BLP2 to restore the same logic level as the first precharge enable signal BLP1 after the test write operation and the test read operation are completed.

The sense amplifier voltage control circuit 220 is formed by connecting inverters INV 27-INV 29, gates NA22 and NA23, and switches Q21-Q25, wherein the switches Q21-Q25 are implemented by transistors to switch the voltage levels of the SAP output node NP and the SAN output node NN between the pre-charge reference voltage HFV and the power supply voltage VDD and VSS, respectively. The SAP output node NP and the SAN output node NN may output a p-channel control voltage SAP and an n-channel control voltage SAN.

Specifically, the nand gate NA22 and the nand gate NA23 receive the column address signal X12B13B, the other input terminals thereof receive sense enable signals SE2 and SE1, respectively, the nand gate NA22 is connected in series with the inverter INV27 and the inverter INV28, the switch Q21 is controlled by the output signal of the inverter INV28, and the first terminal thereof receives the power voltage VDD, and the second terminal thereof is coupled to the SAP output node NP for pulling up the p-channel control voltage SAP to the power voltage VDD.

The nand gate NA23 is connected in series with the inverter INV29, and the switch Q22 is controlled by the output signal of the inverter INV29, and has a first terminal coupled to the SAN output node NN and a second terminal coupled to the ground voltage VSS for pulling the n-channel control voltage SAN down to the ground voltage VSS.

The switches Q23, Q24, and Q25 are all controlled by the second precharge enable signal BLP2, wherein the first terminals of the switches Q24 and Q25 receive a precharge reference voltage HFV, which is lower than the power supply voltage VDD. The second terminal of the switch Q24 is coupled to the first terminal of the switch Q23, the second terminal of the switch Q25 is coupled to the SAP output node NP, and the second terminal of the switch Q23 is coupled to the SAN output node NN. The switches Q23-Q25 are used for restoring the voltage levels of the p-channel control voltage SAP and the n-channel control voltage SAN to the pre-charge reference voltage HFV during the enabling period of the second pre-charge enable signal BLP2 (for example, the switches Q23-Q25 are here exemplified as n-channel transistors, so that the enabling period of the second pre-charge enable signal BLP2 is in a high state).

FIG. 5 is a circuit diagram of a test read write circuit according to an embodiment of the present disclosure. Referring to fig. 5, the test read write circuit 300 includes a precharge voltage control circuit 310 and a test comparison circuit 320, the precharge voltage control circuit 310 is coupled to the test comparison circuit 320 and the sense amplifier circuit 110. For example, the precharge voltage control circuit 310 includes inverters INV31 through INV33, nand gates NA31 through NA33, nor gates NO31 and NO32, switches Q31 through Q36, and transmission gates TG31 through TG 34. The test comparator circuit 320 includes a comparator 312, inverters INV34 and INV35, nand gates NA34 and NA35, nor gate NO33, and switches Q37 to Q39. In the present embodiment, the switches Q31 to Q39 and the transmission gates TG31 to TG34 are implemented by CMOS transistors, but are not limited thereto.

In the present embodiment, the test comparator circuit 320 further includes a latch circuit (latch)314, but it is not necessary, and in another embodiment, the test comparator circuit 320 may not include the latch circuit 314.

Specifically, the nand gate NA31 of the precharge voltage control circuit 310 receives the column address signal X12B13B and the TEST enable signal TEST, the output terminal of the nand gate NA31 is coupled to the n-channel gates of the inverter INV31, the transmission gate TG31 and the transmission gate TG32, the output terminal of the inverter INV31 is coupled to the p-channel gates of the transmission gate TG31 and the transmission gate TG32, one terminals of the transmission gate TG31 and the transmission gate TG32 receive the precharge reference voltage HFV, and the other terminals thereof are coupled to the HFVT output node NHT and the HFVN output node NHN, respectively, wherein the HFVT output node NHT and the HFVN output node NHN provide the first precharge voltage HFVT and the second precharge voltage HFVN to the sense amplifier circuit 110, respectively. The transmission gate TG31 and transmission gate TG32 are turned on or off simultaneously, and the HFVT output node NHT and the HFVN output node NHN receive the pre-charge reference voltage HFV simultaneously when turned on.

The inverter INV32 receives the test data signal TDA, and has an output terminal coupled to the p-channel gate of the transmission gate TG33, the n-channel gate of the transmission gate TG34, an input terminal of the inverter INV33, and one of the input terminals of the nor gate NO 31. An output end of the inverter INV33 is coupled to the n-channel gate of the transmission gate TG33, the p-channel gate of the transmission gate TG34, and one of the input ends of the nor gate NO 32. One end of the transmission gate TG33 and one end of the transmission gate TG34 are respectively coupled to the HFVT output node NHT and the HFVN output node NHN, and the other end thereof is commonly coupled to the inverting input terminal of the comparator 312 of the test comparing circuit 320 for providing one of the first pre-charge voltage HFVT and the second pre-charge voltage HFVN to the comparator 312.

The nand gate NA32 receives the column address signal X12B13B and the test data line precharge signal TPIO, and its output terminal controls whether the switches Q35 and Q36 are turned on, and the first terminals of the switches Q35 and Q36 receive the power voltage VDD, the second terminal of the switch Q35 is coupled to the HFVN output node NHN, and the second terminal of the switch Q36 is coupled to the HFVT output node NHT. Therefore, the first and second pre-charge voltages HFVT and HFVN are pulled up to the power voltage VDD during the enabling period (i.e. high state) of the test data line pre-charge signal TPIO.

The NAND gate NA33 receives the column address signal X12B13B and the test write enable signal TWE, and has outputs coupled to the other inputs of the NOR gate NO31 and the NOR gate NO 32. The output terminal of the nor gate NO31 controls whether the switches Q31 and Q34 are turned on, the output terminal of the nor gate NO32 controls whether the switches Q32 and Q33 are turned on, wherein the first terminal of the switch Q31 receives the voltage source VDD, the second terminal thereof is coupled to the first terminal of the switch Q32 and the HFVT output node NHT, and the second terminal of the switch Q32 is coupled to the ground voltage VSS, so that the voltage level of the first precharge voltage HFVT can be changed to the ground voltage VSS or the voltage level of the first precharge voltage HFVT obtained by subtracting the threshold voltage of the switch Q31 from the voltage source VDD; the first terminal of the switch Q33 receives the voltage source VDD, the second terminal thereof is coupled to the first terminal of the switch Q34 and the HFVN output node NHN, and the second terminal of the switch Q34 is coupled to the ground voltage VSS, so that the voltage level of the second pre-charge voltage HFVN can be changed to the ground voltage VSS or the voltage obtained by subtracting the threshold voltage of the switch Q33 from the voltage source VDD.

Therefore, the pre-charge control circuit 310 generates the first pre-charge voltage HFVT and the second pre-charge voltage HFVN according to the pre-charge reference voltage HFV, and further receives the test write enable signal TWE and the test data signal TDA such that the first pre-charge voltage HFVT and the second pre-charge voltage HFVN can be the power supply voltage VDD, the voltage power supply VDD minus the threshold voltage of the transistor, the ground voltage VSS or the pre-charge reference voltage HFV.

Specifically, the nand gate NA34 of the test compare circuit 320 receives the column address signal X12B13B and the test data enable signal TDE and outputs the signals to the inverter INV34, the output terminal of the inverter INV34 is coupled to the input terminal of the inverter INV35 and one input terminal of the nand gate NA35, and the output terminal of the inverter INV35 is coupled to one input terminal of the nor gate NO 33. The non-inverting input of the comparator 312 receives the test reference voltage TMREF, the inverting input receives one of the first precharge voltage HFVT and the second precharge voltage HFVN from the transmission gate TG33 or the transmission gate TG34, and the output of the comparator 312 is coupled to the other input of the nand gate NA35 and the nor gate NO 33. Here, the test reference voltage TMREF is a predetermined fixed voltage value, which is greater than one-half of the power voltage VDD or higher than the pre-charge reference voltage HFV and is smaller than the power voltage VDD, for example, the test reference voltage TMREF may be three-quarters of the power voltage VDD.

The switch Q37 is controlled by the output result of the nand gate NA35, and has a first terminal coupled to the power voltage VDD and a second terminal coupled to the test node NT, wherein the test node NT outputs the test result TFAIL. The switch Q38 is controlled by the output of the nor gate NO33, and has a first terminal coupled to the test node NT and a second terminal coupled to the ground voltage VSS. The voltage level of the test result TFAIL may be changed into the power voltage VDD or the ground voltage VSS by the output result of the comparator 312.

In addition, the switch Q39 has a first terminal coupled to the test node NT and a second terminal coupled to the ground voltage VSS, and is controlled by the test data line precharge signal TPIO to pull down the voltage level of the test result TFAIL to the ground voltage VSS during the enabling period of the test data line precharge signal TPIO. The latch circuit 314 is also coupled to the test node NT for latching the voltage level of the test result TFAIL.

Briefly, the test comparing circuit 320 compares one of the first precharge voltage HFVT and the second precharge voltage HFVN with the test reference voltage TMREF to generate a test result TFAIL for determining whether there is a memory cell MC failure, wherein when one of the first precharge voltage HFVT and the second precharge voltage HFVN is greater than the test reference voltage TMREF, the test result TFAIL is substantially equal to one of the power voltage VDD and the ground voltage VDD, for example, to indicate that data sensing of the memory cell MC is successful, and when both the first precharge voltage HFVT and the second precharge voltage HFVN are less than the test reference voltage TMREF, the test result TFAIL is substantially equal to the other of the power voltage VDD and the ground voltage VSS, for example, to indicate that data sensing of the memory cell MC is failed. The following examples will further describe the implementation of the read/write test and the determination of whether there is a memory cell MC failure.

Referring to fig. 6 to 8, fig. 6 to 8 are waveform diagrams illustrating a test write operation of a logic "0" and a logic "1" of a memory device according to an embodiment of the disclosure, respectively. The operations of fig. 6 to 8 may be applied to the embodiments of fig. 1 to 5. In a test write operation, taking any memory cell MC as an example, fig. 6 shows operation waveforms of a word line signal WLn, a test write enable signal TWE, sense enable signals SE1 and SE2, a first pre-charge enable signal BLP1, and a second pre-charge enable signal BLP2 on a corresponding word line WL. FIG. 7 is a waveform diagram showing the operation of the test write operation when the write data is logic "0", the voltage levels of the first pre-charge voltage HFVT, the second pre-charge voltage HFVN, the p-channel control voltage SAP, the n-channel control voltage SAN, the bit line BLT and the complementary bit line BLN. In particular, the thin straight line segments shown in fig. 7 and 8 without reference numbers are shown to represent the waveform operations in fig. 6, and no reference numbers are used to avoid the cluttering of the screen, and those skilled in the art can know the meaning of the thin straight line segments in conjunction with fig. 6.

Referring to fig. 6 and 7 in conjunction with fig. 1 to 5, before the testing, the first pre-charge voltage HFVT and the second pre-charge voltage HFVN are maintained at the voltage level of the pre-charge reference voltage HFV because the transmission gate TG31 and the transmission gate TG32 are turned on. In the test write operation, particularly during the test write sensing period tW, one of the first pre-charge voltage HFVT and the second pre-charge voltage HFVN has a voltage value lower than the power supply voltage VDD but higher than the pre-charge reference voltage HFV, and the other voltage value is lower than the pre-charge reference voltage HFV, e.g., substantially equal to the ground voltage VSS.

First, taking the example of writing data indicating logic "0" into the memory cell MC, the test data signal TDA is set to a low state, and the word line signal WLn and the test write enable signal TWE are at a high state, so that the switches Q31 and Q34 are turned off, and the switches Q32 and Q33 are turned on, wherein the switches Q31-Q34 are all n-channel transistors, but not limited thereto, such that the voltage of the first pre-charge voltage HFVT provided by the pre-charge voltage control circuit 310 is pulled down to VSS, and the second pre-charge voltage HFVN is pulled up to the voltage of the power voltage VDD minus the threshold voltage VTN of the n-channel transistor. It should be noted that the voltage level of the power voltage VDD is greater than the sum of the pre-charge reference voltage HFV and the threshold voltage VTN.

Then, the precharge enable control circuit 210 switches the first precharge enable signal BLP1 from the original low level state to the high level state, but the second precharge enable signal BLP2 maintains the low level state, so that the first switch T1 and the second switch T2 are turned on, and the third switch T3 is turned off, so that the bit line BLT and the complementary bit line BLN can respectively receive the first precharge voltage HFVT and the second precharge voltage HFVN.

Specifically, in the embodiment, when the memory cell MC is subjected to the test write operation, and before the first precharge enable signal BLP1 is switched to the enable state, i.e. before the first switch T1 and the second switch T2 are turned on, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are different.

Then, the sense amplifier voltage control circuit 220 switches the p-channel control voltage SAP and the n-channel control voltage SAN from the pre-charge reference voltage HFV to the power voltage VDD and the ground voltage VSS, respectively. The voltage levels of the p-channel control voltage SAP and the n-channel control voltage SAN, which are originally maintained lower than the power voltage VDD, are the same as the precharge reference voltage HFV, and the off Q21 and the off Q22 are turned on during the enabling periods of the sense enable signals SE1 and SE2, the p-channel control voltage SAP and the n-channel control voltage SAN are respectively switched to the power voltage VDD and the ground voltage VSS to amplify the voltage difference between the bit line BLT and the complementary bit line BLN, so that the voltage level of the bit line BLT is substantially equal to the ground voltage VSS and the voltage level of the complementary bit line BLN is the power voltage VDD during the test write sensing period tW, so that the memory cell MC stores data representing logic "0".

Next, referring to fig. 6 and 8 in conjunction with fig. 1 to 5, fig. 8 is a waveform diagram illustrating the operation of the first pre-charge voltage HFVT, the second pre-charge voltage HFVN, the p-channel control voltage SAP and the n-channel control voltage SAN in the test write operation when the write data is logic "1". In the test write operation, taking the case of writing the data representing logic "1" into the memory cell MC as an example, the test data signal TDA is set to a high state, and during the test write sensing period tW, the voltage value of the first precharge voltage HFVT output by the precharge voltage control circuit 310 is pulled up to the voltage obtained by subtracting the threshold voltage VTN of the n-channel transistor from the power voltage VDD, and the voltage level of the second precharge voltage HFVN is pulled down to the ground voltage VSS.

Fig. 9 to 11 are waveform diagrams illustrating a test read operation of a memory device according to an embodiment of the present disclosure. The operations of fig. 9 to 11 may be applied to the embodiments of fig. 1 to 8. Referring to fig. 9 to 11 in combination with fig. 1 to 5, in a test read operation, taking any memory cell MC as an example, fig. 9 shows operation waveforms of a word line signal WLn, sense enable signals SE1 and SE2, a test data line precharge signal TPIO, a test data enable signal TDE, a first precharge enable signal BLP1, and a second precharge enable signal BLP 2. FIGS. 10 and 11 are schematic diagrams illustrating the operation waveforms of the first pre-charge voltage HFVT, the second pre-charge voltage HFVN, the p-channel control voltage SAP, the n-channel control voltage SAN, the voltage levels of the bit line BLT and the complementary bit line BLN under the conditions of determining the success and failure of the read result of the test read operation, respectively. In particular, the thin straight line segments shown in fig. 10 and 11 without reference numbers are shown to represent the waveform operations in fig. 9, and no reference numbers are used to avoid the disorder of the screen, and those skilled in the art can know the meaning of the thin straight line segments in conjunction with fig. 9.

Referring to fig. 9 and 10, before the testing, the first pre-charge voltage HFVT and the second pre-charge voltage HFVN are maintained at the voltage level of the pre-charge reference voltage HFV because the transmission gate TG31 and the transmission gate TG32 are turned on.

When performing a test read operation on the memory cell MC, taking the read memory cell MC representing the data of logic "0" as an example, the data line precharge operation is performed before the test read sensing period tR in the high state of the word line signal WLn, i.e., the switch Q35, the switch Q36 and the switch Q39 are turned on during the enabling period of the test data line precharge signal TPIO, so that the first precharge voltage HFVT and the second precharge voltage HFVN are pulled up to be substantially equal to the power voltage VDD, and the test node NT substantially receives the ground voltage VSS. The switches Q35 and Q36 are p-channel transistors, and the switch Q39 is an example of an n-channel transistor.

After the data line precharge operation is completed, the test data line precharge signal TPIO is disabled (e.g., is in a low state), and the sense enable signals SE1 and SE2 are enabled, so that the p-channel control voltage SAP and the n-channel control voltage SAN are switched from the precharge reference voltage HFV to the power voltage VDD and the ground voltage VSS, respectively.

Then, the first precharge enable signal BLP1 is switched from the original low level state to the high level state, and the second precharge enable signal BLP2 maintains the low level state. The first precharge enable signal BLP1 switched to the high state turns on the first switch T1 and the second switch T2, if the data of the memory cells MC on the same word line WL are successfully sensed, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are different during the trr period, one of the first precharge voltage HFVT and the second precharge voltage HFVN is maintained at the power voltage VDD, and the other one is pulled down to be substantially equal to the ground voltage VSS, in the embodiment of fig. 9, the second precharge voltage HFVN is maintained at the power voltage VDD and the first precharge voltage HFVT is pulled down to the ground voltage VSS.

In particular, the time point at which the first precharge enable signal BLP1 switches from the low level state to the high level state is different between the test write operation and the test read operation, and in particular, the time point at which the first precharge enable signal BLP1 switches the voltage level when the test write operation is performed is earlier than the time point when the test read operation is performed. In the test write operation, the first precharge enable signal BLP1 switches to the high state earlier than the sense enable signals SE1 and SE2, whereas in the test read operation, the first precharge enable signal BLP1 switches to the high state later than the sense enable signals SE1 and SE 2.

Then, the comparator 312 receives the test reference voltage TMREF and one of the first precharge voltage HFVT and the second precharge voltage HFVN, for example, the voltage level of which is higher, so in the present embodiment, the comparator 312 receives the test reference voltage TMREF and the second precharge voltage HFVN, wherein the voltage value of the test reference voltage TMREF is preset to be three-quarters of the power supply voltage VDD, and the second precharge voltage HFVN is substantially equal to the power supply voltage VDD at this moment. During the test read sensing period tR, since the second precharge voltage HFVN is greater than the test reference voltage TMREF, the test result TFAIL is set to a low voltage level, for example, substantially equal to the ground voltage VSS, to indicate that the data of the memory cells MC on the same word line WL are all successfully sensed.

Referring to fig. 9 and 11, if the data sensing of the memory cells MC on the same word line WL fails, the first precharge voltage HFVT and the second precharge voltage HFVN are originally in a high state, and the voltage value of the first precharge enable signal BLP1 is pulled down by the ground voltage VSS after the first switch T1 and the second switch T2 are turned on by the high state, so that the voltage value is lower than the original voltage level.

In the present embodiment, the second pre-charge voltage HFVN is originally in a high state, and the voltage value is substantially equal to the power voltage VDD, and the voltage value of the first pre-charge voltage HFVT is substantially equal to the ground voltage VSS. During the trr period, after the first switch T1 and the second switch T2 are turned on, the first pre-charge voltage HFVT is still equal to the ground voltage VSS, but the second pre-charge voltage HFVN is pulled down to be close to half of the power voltage VDD, specifically, the voltage of the second pre-charge voltage HFVN is reduced to be equal to the power voltage VDD minus the threshold voltage VTN of the n-channel transistor, in one embodiment, the power voltage VDD is 1.5V, the threshold voltage VTN of the n-channel transistor is 0.7V, and thus the reduced voltage of the second pre-charge voltage HFVN is close to half of the power voltage VDD.

Then, the comparator 312 receives the test reference voltage TMREF and the second precharge voltage HFVN for comparison, the voltage value of the test reference voltage TMREF is preset to be three-quarters of the power supply voltage VDD, the voltage value of the second precharge voltage HFVN at the moment is close to one-half of the power supply voltage VDD and is smaller than the test reference voltage TMREF, so that the test result TFAIL is set to be changed to a high voltage level, for example, substantially equal to the power supply voltage VDD, indicating a sensing failure state of the memory cells MC on the same word line WL.

In the embodiments of fig. 9 to 11, when performing the test read operation on the memory cell MC, in the test read sensing period tR, one of the first pre-charge voltage HFVT and the second pre-charge voltage HFVN has a voltage value not greater than the power voltage VDD but higher than the pre-charge reference voltage HFV, and the other voltage value is lower than the pre-charge reference voltage HFV, for example, equal to the ground voltage VSS.

In another embodiment, the first precharge voltage HFVT may be in a high state, and the comparator 312 receives the test reference voltage TMREF and the first precharge voltage HFVT for comparison, and detailed description will be omitted since those skilled in the art can obtain sufficient teachings from the above description and general knowledge.

Referring to fig. 12, fig. 12 is a waveform diagram illustrating operations of a memory device writing logic "0" to all memory cells according to another embodiment of the present disclosure. The present embodiment can be applied to the memory device 100 of the above embodiments of fig. 1 to 11. In the embodiment of fig. 12, after the Power supply of the memory device 100 is turned on (Power up) or RESET (RESET), the memory device 100 performs a write operation on all word lines WL and all connected sense amplifier circuits 110 in the memory device 100 within an extended write period T, for example, within a range of less than 200 microseconds to 300 microseconds, for example, the extended write period T is about 300 microseconds in the embodiment of fig. 12, and the omitted symbols in fig. 12 indicate the write operation. That is, the memory device 100 of the present embodiment can write data logic "0" to the memory cells MC on all the word lines WL in a short time. Regarding the implementation of the operation waveforms of fig. 12, those skilled in the art can obtain sufficient suggestions and teachings from the embodiments of fig. 6 to 8, and the description thereof is omitted here.

In summary, the present disclosure provides a memory device, including: a precharge voltage control circuit and a sense amplifier circuit. The pre-charging voltage control circuit generates a first pre-charging voltage and a second pre-charging voltage according to the pre-charging reference voltage. The sense amplifier circuit is coupled between the bit line and the complementary bit line for sensing data of the memory cell coupled to the bit line, and coupled to the precharge voltage control circuit, so that the bit line and the complementary bit line receive a first precharge voltage and a second precharge voltage, respectively, wherein the first precharge voltage and the second precharge voltage have the same voltage level during the precharge operation, and the precharge voltage control circuit provides the bit line and the complementary bit line with different voltage levels during the test write sensing period and the test read sensing period after the precharge operation. In this way, multiple sense amplifiers on a word line can be selected to perform a parallel test mode in one cycle (cycle).

Although the present disclosure has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure, and therefore the scope of the present disclosure should be limited only by the terms of the appended claims.