阅读说明：本技术 高静电放电耐受力的静电保护元件布局结构 (Layout structure of electrostatic protection element with high electrostatic discharge tolerance ) 是由 谢协缙 林欣逸 于 2018-06-20 设计创作，主要内容包括：本发明公开了一种高静电放电耐受力的静电保护元件布局结构,包含有多个相互并联的NMOS晶体管,且该些并联的NMOS晶体管构成一隔离型NMOS多指型半导体布局结构；其中该隔离型NMOS多指型半导体布局结构的中间区域是掺杂高能量P型植入离子浓度的P型掺杂区域,使该中间区域的基板电阻减低；如此,即可使得该中间区域所对应的NMOS晶体管的总基板电阻减低,并减少其与两旁其中之一所对应的NMOS晶体管的基板电阻差,使得NMOS晶体管可被均匀导通,使提升NMOS晶体管的静电放电耐受力。(The invention discloses a layout structure of an electrostatic protection element with high electrostatic discharge tolerance, which comprises a plurality of NMOS transistors which are connected in parallel, wherein the NMOS transistors which are connected in parallel form an isolated NMOS multi-finger type semiconductor layout structure; wherein the middle region of the isolated NMOS multi-finger semiconductor layout structure is a P-type doped region doped with high-energy P-type implanted ion concentration, so that the substrate resistance of the middle region is reduced; therefore, the total substrate resistance of the NMOS transistor corresponding to the middle area can be reduced, the substrate resistance difference between the NMOS transistor corresponding to the middle area and one of the two sides can be reduced, the NMOS transistors can be uniformly conducted, and the electrostatic discharge tolerance of the NMOS transistors can be improved.)

1. An electrostatic protection device layout structure with high electrostatic discharge endurance is characterized by comprising:

a P-type substrate having an isolation layer formed thereon in a device region;

a first P-type doped region formed on the isolation layer;

a P-type well formed on the first P-type doped region;

a second P-type doped region implanted in the P-well and the first P-type doped region corresponding to a middle region of the device region; wherein the concentration of the P-type implanted ions in the second P-type doped region is higher than that in the first P-type doped region;

a plurality of drain doped regions implanted into the P-well;

a plurality of source doped regions implanted in the P-well;

a doped base region implanted in the P-well and located outside the doped drain regions and the doped source regions; and

a plurality of gate structures formed on the P-type well; wherein each grid structure is positioned between two adjacent drain electrode doped regions and source electrode doped regions to form a plurality of NMOS transistors connected in parallel.

2. The layout structure of claim 1 wherein the second P-type doped region has a lower P-type ion concentration than the P-type well.

3. The layout structure of electrostatic protection devices according to claim 1 or 2, wherein there is a space between each side of the middle region and the base doped region.

4. The layout structure of electrostatic protection devices according to claim 3, wherein the middle region corresponds to a single NMOS transistor.

5. The layout structure of electrostatic protection devices according to claim 3, wherein the middle region corresponds to a plurality of NMOS transistors.

6. The layout structure of electrostatic protection devices as claimed in claim 1, wherein an N-type doped region is formed on the isolation layer corresponding to the periphery of the device region, the N-type doped region being outside the base doped region.

7. The layout structure of electrostatic protection device of claim 6 wherein the N-type doped region is a high voltage N-well.

8. The layout structure of electrostatic protection device as claimed in claim 1, wherein the isolation layer is an N-type buried layer.

9. The layout structure of electrostatic protection devices according to claim 1, wherein:

the first P-type doped region is a P-type epitaxial layer; and

the second P-type doped region is a high voltage P-type well.

10. The layout structure of electrostatic protection devices according to claim 1, wherein:

each drain electrode doped region is an N + type doped region;

each source electrode doping area is an N + type doping area; and

the base doped region is a P + doped region.

Technical Field

The present invention relates to an electrostatic discharge protection device layout structure, and more particularly, to an electrostatic discharge protection device layout structure with high electrostatic discharge endurance.

Background

Generally, in an Integrated Circuit (IC) using a MOS process, MOS devices of the IC are easily damaged by electrostatic high voltage discharge. Taking one of the esd protection devices frequently used in an integrated circuit, i.e., the NMOS transistor device 30, as an example, it includes a plurality of NMOS transistors connected in parallel, as shown in fig. 5A, the NMOS transistors are formed on a P-type substrate 31; the P-type substrate 31 is formed with an N-type isolation layer 32, a P-type doped region 33 and a P-type well 34 from bottom to top, and the P-type well 34 is implanted with a plurality of drain doped regions 35 and a plurality of source doped regions 36, and then a plurality of gate structures 37 are formed on the P-type well 34; wherein each gate structure 37 is located between two adjacent drain doped regions 35 and source doped regions 36 to form a plurality of parallel NMOS transistors Mn, as shown in fig. 5B.

Referring to fig. 5B, since the NMOS transistors Mn are formed on the same P-type substrate 31, the substrate resistances R of the NMOS transistors Mn are connected in series, so that the equivalent total substrate resistance of the NMOS transistor Mn located in the middle region is higher than that of the other NMOS transistors Mn; taking fig. 5B as an example, the equivalent total substrate resistance of the 6 th NMOS transistor from right to left is approximately 6 times the substrate resistance R. Therefore, when a static electricity discharges the esd protection NMOS transistor device 30, a part of the static electricity discharge current flows through the substrate resistor R, and the base resistor R of the parasitic BJT of the NMOS transistor Mn in the middle region is higher than the base resistors R of the NMOS transistors Mn in the two side regions, so that the parasitic BJT of the NMOS transistor Mn in the middle region is turned on first, and the NMOS transistor Mn in the middle region is easily burned.

Therefore, the electrostatic discharge tolerance of the conventional electrostatic protection NMOS transistor device in the integrated circuit structure in a large area cannot provide the electrostatic tolerance, so that further improvement is needed.

Disclosure of Invention

In view of the above-mentioned problem that the ESD endurance of the ESD protection NMOS device of the general integrated circuit can not be improved, the present invention provides a layout structure of ESD protection NMOS device with high ESD endurance.

The main technical means to achieve the above purpose is to make the layout structure of the electrostatic protection device with high electrostatic discharge endurance include:

a P-type substrate having an N-type isolation layer formed thereon in a device region;

a first P-type doped region formed on the N-type isolation layer;

a P-type well formed on the first P-type doped region;

a second P-type doped region implanted in the P-well and the first P-type doped region corresponding to a middle region of the device region; wherein the concentration of the P-type implanted ions in the second P-type doped region is higher than that in the first P-type doped region;

a plurality of drain doped regions implanted into the P-well;

a plurality of source doped regions implanted in the P-well;

a doped base region implanted in the P-well and located outside the doped drain regions and the doped source regions; and

a plurality of gate structures formed on the P-type well; wherein each grid structure is positioned between two adjacent drain electrode doped regions and source electrode doped regions to form a plurality of NMOS transistors connected in parallel.

In view of the above, the NMOS transistors are formed on the same P-type substrate, so the substrate resistances of the NMOS transistors are connected in series, and since the second P-type doped region is implanted in the middle region according to the present invention, the substrate resistance of the middle NMOS transistor covered by the second P-type doped region is reduced, thereby effectively reducing the equivalent total substrate resistance of the NMOS transistor located in the middle region; therefore, when a static electricity discharges to the electrostatic protection element, a hot carrier effect (hot carrier) is generated in a depletion region between the drain and the base, so that a current flows to the base, and the middle implanted region is reduced due to the implantation of the second P-type doped region, so that the voltage difference between the middle region and the two sides is reduced, and the defect that an NMOS transistor in the middle region and NMOS transistors in the two side regions cannot be uniformly conducted to instantly and simultaneously discharge the static current is overcome, thereby improving the electrostatic discharge tolerance of the NMOS transistor.

Drawings

FIG. 1: the invention relates to an electrostatic protection element layout structure applied to a circuit diagram of an integrated circuit.

FIG. 2A: a semiconductor structure of the first embodiment of a layout structure of an electrostatic protection device according to the present invention.

FIG. 2B: fig. 2A is an equivalent circuit schematic.

FIG. 3: fig. 2A is a top plan view.

FIG. 4A: a semiconductor structure of a second embodiment of a layout structure of an electrostatic protection device according to the present invention.

FIG. 4B: fig. 4A is an equivalent circuit schematic.

FIG. 5A: a semiconductor structure of an electrostatic protection device of an existing integrated circuit is provided.

FIG. 5B: fig. 5A is an equivalent circuit schematic.

Wherein, the reference numbers:

10 integrated circuit 11 internal circuit

20 electrostatic protection GGNMOS transistor circuit 21P type substrate

211N type isolation layer 212N type doped region

22 first P-type doped region 23P-type well

24. 24' second P-type doped region 25 Drain doped region

26 source doped region 27 base doped region

28-gate structure 30NMOS transistor

31P-type substrate 32N-type isolation layer

33P-type doped region 34P-type well

35 drain doped region 36 source doped region

37 grid structure

Detailed Description

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

The invention provides an improvement for the electrostatic discharge tolerance of an electrostatic protection element of an integrated circuit, in particular to an improvement for the electrostatic protection element formed by an NMOS transistor, thereby improving the electrostatic discharge tolerance of the electrostatic protection element. Several embodiments are described in detail below with reference to the drawings.

Referring to fig. 1, a layout structure of an electrostatic protection device according to the present invention is shown, in the present embodiment, the electrostatic protection device is an NMOS transistor device 20; as shown in fig. 2A, the NMOS transistor device 20 includes a P-type substrate 21, a first P-type doped region 22, a P-type well 23, a second P-type doped region 24, a plurality of drain doped regions 25, a plurality of source doped regions 26, a base doped region 27, and a plurality of gate structures 28; wherein an N-type isolation layer 211 is formed on the P-type substrate 21 in a device region; in the present embodiment, the N-type isolation Layer 211 is an N + Buried Layer (N + Buried Layer), and the device region of the P-type substrate 21 is defined by an N-type doped region 212 formed on the N-type isolation Layer 211; preferably, the N-Type doped region 212 is a High Voltage N-Type Well (HVNW).

The first P-type doped region 22 is formed on the N-type isolation layer 211; in the present embodiment, the first P-type doped region 22 is a P-type epitaxial Layer (P-EPI Layer).

The P-well 23 is formed on the first P-type doped region 22.

The second P-type doped region 24 is implanted in the P-well 23 and the first P-type doped region 22 in a middle region corresponding to the device region; wherein the second P-type doped region 24 has a higher concentration of P-type implanted ions than the first P-type doped region 22, but lower concentration of P-type implanted ions than the P-well 23; in other words, the concentration of the P-type ions in the second P-type doped region 24 is between the concentration of the P-type ions in the P-well 23 and the concentration of the P-type ions in the first P-type doped region 22.

The drain doped regions 25 are implanted into the P-well 23; wherein each of the drain doped regions 25 is an N + type doped region.

The source doped regions 26 are implanted into the P-well 23; wherein each of the source doped regions 26 is an N + type doped region.

The doped base region 27 is implanted into the P-well 23 and outside the doped drain regions 25 and the doped source regions 26, but within the doped N-type region 212; in the present embodiment, the base doped region 27 is a P + doped region.

A plurality of gate structures 28 formed on the P-well 23; each of the gate structures 28 is located between two adjacent drain doped regions 25 and source doped regions 26 to form a plurality of NMOS transistors Mn, Mn' connected in parallel, as shown in fig. 2B, which can be used as an electrostatic protection device connected to an output buffer 11 in an integrated circuit 10, i.e., the NMOS transistor device 20, as shown in fig. 1.

Referring to fig. 3, which is a top plan view of fig. 3, it can be seen that a distance d1 is maintained between each side of the middle region C and the base doped region 27; in the present embodiment, the second P-type doped region 24 corresponding to the middle region C covers the middle 4 NMOS transistors Mn ', so as shown in fig. 2B, the substrate resistance R ' of the middle 4 NMOS transistors Mn ' is higher than the substrate resistance R of the remaining NMOS transistors Mn; since the concentration of the P-type implanted ions in the second P-type doped region 24 is higher than that in the first P-type doped region 22, the impedance difference between the substrate resistance R 'of the middle 4 NMOS transistors Mn' and the substrate resistance R of the remaining NMOS transistors Mn is reduced.

Referring to fig. 4A, a semiconductor structure diagram of a second embodiment of an esd protected device layout structure according to the present invention is shown, as compared with fig. 2A, the middle region C ' of the present embodiment is more reduced, which means that the number of middle NMOS transistors Mn ' covered by the second P-type doped region 24 ' is reduced, and at least one single NMOS transistor can be covered, but in the present embodiment, the second P-type doped region 24 ' covers the middle 2 NMOS transistors Mn '; as shown in fig. 4B, the substrate resistance R 'of the middle 2 NMOS transistors Mn' is reduced; therefore, the present invention can flexibly adjust the size of the second P-type doped region 24' according to different NMOS transistor processes.

Since the size of the second P-type doped region can be adjusted according to different processes, different distances d1 can be selected, and how to determine the range d2 of the middle region C is described in further detail below; firstly, according to a resistance formula R ═ rho L/A; wherein ρ is the resistivity, L is the conductor length, a is the conductor cross-sectional area, and the formula of the electrical conductivity in accordance with the physics of the semiconductor element σ 1/ρ q (μ n n + μ p p); where σ is the conductivity, q is the unit charge, μ n is the electron mobility, n is the free electron concentration, μ P is the hole mobility, and P is the free hole concentration, since the present invention uses a P-type substrate, μ n n < < μ P P, the conductivity can be approximated as σ ═ q μ P P; since the impurity concentration is proportional to μ P P, it is further assumed that the conductivity of the undoped second P-type doped region is σ, and the conductivity of the doped second P-type doped region 24 is σ ', which proves that σ' > σ; therefore, assuming that the center of the device region C is a distance d3 from the base doping region, d3 is d1+ d 2/2.

Similarly, assuming that the second P-type doped region is not doped, the substrate resistance (maximum effective resistance) of the middle NMOS transistor is R ═ ρ L/a ═ L/(σ ×) whereas the maximum equivalent substrate resistance of the second P-type doped region with doping becomes R '═ d1/(σ × a) + d2/(σ' ×; it can be demonstrated that the maximum equivalent substrate resistance R' of the doped second P-type doped region is actually smaller than the maximum equivalent substrate resistance R of the undoped second P-type doped region.

As can be seen from the foregoing first and second embodiments of the present invention, the NMOS transistors are formed on the same P-type substrate, so the substrate resistances of the NMOS transistors are connected in series, and the second P-type doped region is implanted in the middle region, so that the substrate resistance of the middle NMOS transistor covered by the second P-type doped region is reduced, and the equivalent total substrate resistance of the NMOS transistor in the middle region is effectively reduced; therefore, when a static electricity discharges the static electricity protection element (namely NMOS transistor element), because the difference of the equivalent total substrate resistance of the NMOS transistor positioned in the middle area and the NMOS transistors positioned in the two side areas is reduced, the defect that the NMOS transistors positioned in the middle area and the two side areas are conducted at different time to discharge the static electricity current is improved, the NMOS transistors can be synchronously and uniformly conducted, and the static electricity discharge tolerance of the NMOS transistors is improved.

Although the present invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.