Semiconductor device including fin field effect transistor
阅读说明：本技术 包括鳍型场效应晶体管的半导体器件 (Semiconductor device including fin field effect transistor ) 是由 卢昶佑 宋昇珉 裵金钟 裵东一 于 2019-02-27 设计创作，主要内容包括：一种包括鳍型场效应晶体管(fin-FET)的半导体器件包括：设置在衬底上的有源鳍；在有源鳍的两侧上的隔离层；形成为与有源鳍和隔离层交叉的栅极结构；在栅极结构的侧壁上在有源鳍上的源极/漏极区；第一层间绝缘层,在隔离层上与栅极结构的侧壁的部分和源极/漏极区的表面的部分接触；蚀刻停止层,构造为重叠第一层间绝缘层、栅极结构的侧壁和源极/漏极区；以及接触插塞,形成为穿过蚀刻停止层以接触源极/漏极区。源极/漏极区具有与有源鳍的上表面接触的主生长部分。(A semiconductor device including a fin-FET (fin-FET) includes: an active fin disposed on the substrate; an isolation layer on both sides of the active fin; forming a gate structure crossing the active fin and the isolation layer; source/drain regions on the active fin on sidewalls of the gate structure; a first interlayer insulating layer on the isolation layer in contact with portions of sidewalls of the gate structure and portions of surfaces of the source/drain regions; an etch stop layer configured to overlap the first interlayer insulating layer, a sidewall of the gate structure, and the source/drain region; and a contact plug formed through the etch stop layer to contact the source/drain region. The source/drain regions have a main growth portion in contact with an upper surface of the active fin.)
1. A semiconductor device, comprising:
an active fin extending in a first direction on the substrate;
an isolation layer on a side of the active fin;
a gate structure formed to cross the active fin and the isolation layer and to extend in a second direction perpendicular to the first direction;
a source/drain region on the active fin on a sidewall of the gate structure;
a first interlayer insulating layer formed on the isolation layer and in contact with a first portion of the sidewall of the gate structure and a first surface of the source/drain region;
an etch stop layer on the first interlayer insulating layer, a second portion of the sidewall of the gate structure, and a second surface of the source/drain region; and
a contact plug formed through the etch stop layer and contacting the source/drain region,
wherein the source/drain region has a main growth portion contacting an upper surface of the active fin and a merged growth portion where edges of the main growth portion merge with each other.
2. The semiconductor device of claim 1, wherein the source/drain region comprises a lateral protrusion protruding in an outward direction of the active fin and comprising a lateral protrusion end, and
wherein a flat lower surface of the etch stop layer is at a first level higher than a level of the lateral protruding end with respect to the substrate and lower than a level of an upper end of the merged growth portion.
3. The semiconductor device of claim 2, wherein the planar lower surface of the etch stop layer is at a second level, the second level and a midpoint between a level of the lateral protrusion end with respect to the substrate and the level of the upper end of the merged growth portion match or are higher than the midpoint.
4. The semiconductor device of claim 1, further comprising a protective layer on the spacers, the sidewalls of the gate structure, and the source/drain regions,
wherein the protective layer is between the isolation layer and the first interlayer insulating layer, between the first interlayer insulating layer and the source/drain region, between the source/drain region and the etch stop layer, and between the etch stop layer and the gate structure.
5. The semiconductor device of claim 1, further comprising:
an etch stop layer overlying the isolation layer, the source/drain regions, and the sidewalls of the gate structure,
wherein the lower etch stop layer is between the isolation layer and the first interlayer insulating layer, between the first interlayer insulating layer and the source/drain region, between the source/drain region and the etch stop layer, and between the etch stop layer and the gate structure.
6. The semiconductor device of claim 1, wherein a centerline of one of the contact plugs is misaligned with a centerline of a respective one of the source/drain regions in the first direction.
7. The semiconductor device as set forth in claim 6,
wherein a first end of said one of said contact plugs extends outwardly from a first end of said respective source/drain region,
wherein a second end of the one of the contact plugs is on the respective source/drain region, an
Wherein a lower surface of the extension portion of the one of the contact plugs contacts the first interlayer insulating layer.
8. The semiconductor device of claim 1, wherein one of the contact plugs comprises a silicide layer in contact with an upper surface of a respective one of the source/drain regions.
9. A semiconductor device, comprising:
an active fin extending in a first direction on the substrate;
isolation layers on both sides of the active fin;
a gate structure formed to cross the active fin and the isolation layer and to extend in a second direction perpendicular to the first direction;
a source/drain region on the active fin on a side of the gate structure;
an etch stop layer on sidewalls of the gate structure and the source/drain regions and having a sigma shape;
a first interlayer insulating layer interposed between the etch stop layers; and
a contact plug formed through the etch stop layer and contacting the source/drain region.
10. The semiconductor device of claim 9, wherein the etch stop layer comprises a lower etch stop layer on the isolation layer, the sidewalls of the gate structure, and the source/drain regions, and an upper etch stop layer on the lower etch stop layer and the first interlayer insulating layer.
11. The semiconductor device as set forth in claim 10,
wherein the lower etch stop layer includes a lower upper surface contacting a lower surface of the first interlayer insulating layer, a first side surface extending from a lower end of the source/drain region in an outward and upward direction of the source/drain region, and a second side surface extending from an upper end of the first side surface in an inward and upward direction of the source/drain region, and
wherein a first corner is between the lower upper surface and the first side surface and a second corner is between the first side surface and the second side surface.
12. The semiconductor device of claim 11, wherein a lower surface of the upper etch stop layer is at a level relative to the substrate that is higher than a level of the second corner and lower than a level of an upper end of a merged growth portion of the source/drain regions.
13. The semiconductor device as set forth in claim 11,
wherein the upper etch stop layer has a flat lower surface in contact with an upper surface of the first interlayer insulating layer,
wherein a third corner is between the planar lower surface and the second side surface, and a portion of the etch stop layer at a level above the third corner relative to the substrate is thicker than a portion thereof disposed at a level below the third corner relative to the substrate.
14. The semiconductor device as set forth in claim 11,
wherein a third corner is between the second side surface and a planar lower surface of the upper etch stop layer, an
Wherein the sigma shape of the etch stop layer is formed by connecting the lower upper surface, the first corner, the first side surface, the second corner, the second side surface, the third corner, and the planar lower surface of the upper etch stop layer of the lower etch stop layer.
15. The semiconductor device of claim 9, wherein a centerline of a first one of the contact plugs is misaligned with a centerline of a respective one of the source/drain regions in the first direction.
16. The semiconductor device of claim 9, further comprising:
a protective layer on the isolation layer, the sidewalls of the gate structure, and the source/drain regions,
wherein the protective layer is in contact with a lower surface of an underlying etch stop layer of the etch stop layer.
17. A semiconductor device, comprising:
an active fin extending in a first direction on the substrate;
an isolation layer disposed on a side of the active fin;
a gate structure formed to cross the active fin and the isolation layer and to extend in a second direction perpendicular to the first direction;
a source/drain region on the active fin on a sidewall of the gate structure;
a lower etch stop layer on the spacers, the source/drain regions, and the sidewalls of the gate structure;
a first interlayer insulating layer on the lower etch stop layer and having a height smaller than a height of an upper end of the source/drain region;
an upper etch stop layer on a portion of the lower etch stop layer and the first interlayer insulating layer; and
a contact plug formed through the lower etch stop layer and the upper etch stop layer to contact an upper surface of the source/drain region,
wherein a centerline of a first one of the contact plugs is misaligned with a centerline of the source/drain region in the first direction.
18. The semiconductor device as set forth in claim 17,
wherein the source/drain regions comprise lateral protrusions protruding in an outward direction of the active fin and comprising lateral protruding ends, an
Wherein a lower surface of the upper etch stop layer is at a higher level relative to the substrate than a level of the lateral protrusion end.
19. The semiconductor device as set forth in claim 18,
wherein the lower etch stop layer has a first side surface at a lower level with respect to the lateral protrusion end of the source/drain region and a second side surface disposed at a higher level with respect to the lateral protrusion end of the source/drain region,
wherein the first side surface extends from a lower end of the source/drain region in an outward and upward direction of the source/drain region, an
Wherein the second side surface extends from an upper end of the first side surface in an inward and upward direction of the source/drain region.
20. The semiconductor device of claim 17, wherein the source/drain region comprises a main growth portion in contact with an upper surface of the active fin and a merged growth portion where edges of the main growth portion merge with each other, and
a lower surface of the upper etch stop layer is at a lower level relative to the substrate than an upper end of the merged growth end of the source/drain regions.
Technical Field
Devices and methods relate to semiconductor devices including fin-field effect transistors (fin-FETs) and methods of fabricating the semiconductor devices.
Background
In accordance with the demand for high integration of semiconductor devices, it becomes more difficult to form a plurality of contact plugs in a limited space. The contact plug is used to provide an electrical connection between the lower pattern and the upper line.
When the lower pattern is excessively recessed in the process of forming the contact plug, parasitic capacitance is generated between the gate electrode and the contact plug, and thus a current delay may occur.
Disclosure of Invention
Example embodiments of the inventive concepts aim to provide a semiconductor device in which generation of parasitic capacitance is reduced and which has improved operation characteristics.
According to an example embodiment, there is provided a semiconductor device including: an active fin extending in a first direction on a substrate; an isolation layer on a side of the active fin; a gate structure formed to cross the active fin and the isolation layer and to extend in a second direction perpendicular to the first direction; source/drain regions on the active fin on sidewalls of the gate structure; a first interlayer insulating layer formed on the isolation layer and in contact with a first portion of a sidewall of the gate structure and a first surface of the source/drain region; an etch stop layer on the first interlayer insulating layer, a second portion of the sidewall of the gate structure, and a second surface of the source/drain region; and a contact plug formed through the etch stop layer to contact the source/drain region, wherein the source/drain region has a main growth portion contacting an upper surface of the active fin and a merged growth portion where edges of the main growth portion merge with each other.
According to an example embodiment, there is provided a semiconductor device including: an active fin extending in a first direction on a substrate; an isolation layer on both sides of the active fin; a gate structure formed to cross the active fin and the isolation layer and to extend in a second direction perpendicular to the first direction; source/drain regions on the active fin on both sides of the gate structure; an etch stop layer on sidewalls of the gate structure and the source/drain regions and having a sigma (Σ) shape; a first interlayer insulating layer interposed between the etch stop layers; and a contact plug formed through the etch stop layer and contacting the source/drain region.
According to an example embodiment, there is provided a semiconductor device including: an active fin extending in a first direction on a substrate; an isolation layer on both sides of the active fin; a gate structure formed to cross the active fin and the isolation layer and to extend in a second direction; a source/drain region on the active fin on a sidewall of the gate structure; a lower etch stop layer configured to cover sidewalls of the isolation layer, the source/drain region, and the gate structure; a first interlayer insulating layer on the lower etch stop layer and having a height smaller than a height of an upper end of the source/drain region; an upper etch stop layer on a portion of the lower etch stop layer and the first interlayer insulating layer; and contact plugs formed through the lower and upper etch stop layers and contacting the upper surfaces of the source/drain regions, wherein centerlines of first ones of the contact plugs and centerlines of the source/drain regions are misaligned in the second direction.
Drawings
Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic layout illustrating a semiconductor device according to an example embodiment of the inventive concepts.
Fig. 2 is a perspective view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
Fig. 3A is a cross-sectional view taken along line a-a' of fig. 2, according to an example embodiment of the inventive concept.
Fig. 3B is a cross-sectional view taken along line B-B' of fig. 2, according to an example embodiment of the inventive concept.
Fig. 3C is a sectional view taken along line C-C' of fig. 2, according to an example embodiment of the inventive concept.
Fig. 4 is a cross-sectional view taken along line B-B' of fig. 2, according to an example embodiment.
Fig. 5 is a perspective view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
Fig. 6A is a cross-sectional view taken along line a-a' of fig. 5, according to an example embodiment of the inventive concept.
Fig. 6B is a cross-sectional view taken along line B-B' of fig. 5, according to an example embodiment of the inventive concept.
Fig. 7 is a perspective view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
Fig. 8A is a sectional view taken along line a-a' of fig. 7, according to an example embodiment of the inventive concept.
Fig. 8B is a cross-sectional view taken along line B-B' of fig. 7, according to an example embodiment of the inventive concept.
Fig. 9 is a perspective view illustrating a semiconductor device according to an example embodiment of the inventive concepts.
Fig. 10 is a sectional view taken along line B-B' of fig. 9, according to an example embodiment of the inventive concept.
Fig. 11 to 24 are views illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts.
Fig. 25 to 30 are views illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts.
Detailed Description
It is noted that aspects of the inventive concept described with respect to one embodiment may be incorporated in a different embodiment, although not specifically described with respect thereto. That is, the features of all embodiments and/or any embodiment may be combined in any manner and/or combination. These and other objects and/or aspects of the inventive concept are explained in detail in the specification set forth below. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of … …" when following a column of elements modify the entire column of elements without modifying individual elements in the column.
Fig. 1 is a schematic layout illustrating a semiconductor device according to some embodiments of the inventive concept. Fig. 2 is a perspective view illustrating a semiconductor device according to some embodiments of the inventive concept. Fig. 3A is a sectional view taken along line a-a' of fig. 2. Fig. 3B is a sectional view taken along line B-B' of fig. 2. Fig. 3C is a sectional view taken along line C-C' of fig. 2. Fig. 4 is a cross-sectional view taken along line B-B' of fig. 2, according to some embodiments. For convenience of description, only main elements are shown in fig. 1, and the second interlayer insulating layer and the upper contact plug will be omitted in fig. 2.
Referring to fig. 1 to 4, the semiconductor device 100 may include a substrate 101, an active fin 105, an isolation layer 107, source/drain regions 110, a gate structure 140, a first interlayer insulating layer 153, an etch stop layer 160, a second interlayer insulating layer 155, a contact plug 180, and an upper contact plug 190. The semiconductor device 100 according to some embodiments of the inventive concept may be a transistor such as a fin-field effect transistor (fin-FET) in which the active fin 105 has a fin structure. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms; rather, these terms are only used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the scope of the inventive concept.
The substrate 101 may have an upper surface extending in an X direction (first direction) and a Y direction (second direction). The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may comprise silicon, germanium, or silicon germanium. The substrate 101 may include a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, and the like.
The active fin 105 may be formed as a fin structure protruding from the main surface of the substrate 101. The active fin 105 may be disposed to extend in the X direction (first direction). The active fin 105 may be formed from a portion of the substrate 101 or may include an epitaxial layer grown from the substrate 101. However, the active fin 105 on the substrate 101 may be recessed, and the source/drain regions 110 may be disposed on the side surfaces of the gate structure 140. Here, the active fin 105 may mean an element in which a channel is formed in a field effect transistor. Although not shown in the drawings, the active fin 105 may be formed of a plurality of vertically stacked semiconductor patterns. For example, each of the plurality of semiconductor patterns may extend in the X direction, and may be disposed on the substrate 101 apart from the upper surface of the substrate 101 in the Z direction. The plurality of semiconductor patterns may be disposed apart from each other in the Z direction. Top, bottom, and side surfaces of the plurality of semiconductor patterns may be surrounded by the gate structure 140.
The isolation layer 107 may define an active fin 105 on the substrate 101. Isolation layers 107 may be disposed on both sides of active fin 105 on substrate 101. The isolation layer 107 may be made of an insulating material. For example, the isolation layer 107 may be formed by a Shallow Trench Isolation (STI) process. The isolation layer 107 may include, for example, one selected from oxide, nitride, and/or a combination thereof.
Source/drain regions 110 may be disposed on one or more of active fins 105 on both sides of gate structure 140. The source/drain regions 110 may be provided as source or drain regions of the semiconductor device 100. In some embodiments, the source/drain region 110 may have a raised source/drain shape whose upper surface is disposed at a higher level than the lower surface of the gate structure 140, but the inventive concept is not limited thereto. In some embodiments of the inventive concept, the source/drain region 110 is shown to have a pentagonal shape. However, the source/drain region 110 may have any of various shapes, such as a polygon, a circle, and/or a rectangle.
The source/drain regions 110 may be configured to connect or merge with each other on the active fin 105. In some embodiments of the inventive concept, the source/drain regions 110 are shown configured to be connected to each other on three active fins 105, but the inventive concept is not limited thereto. For example, the source/drain regions 110 may be configured to connect to each other on both active fins 105. In some embodiments, as shown in fig. 4, the source/drain region 110 may be formed on one active fin 105. The source/drain regions 110 may comprise, for example, silicon (Si) or silicon germanium (SiGe).
The source/drain region 110 may have a main growth portion GE and a merged growth portion ME. The main growth portion GE may be a portion that is crystal-grown from the recess region of each active fin 105. The merged growth part ME may be a part where edges of the main growth part GE merge with each other. While the crystallization process is performed, adjacent edges of the main growth portion GE may merge, and the merged portion may vertically extend to form the merged growth portion ME.
The source/drain region 110 may have a lateral protrusion P and a lateral protrusion end E. The lateral protrusion P may be a portion protruding from the source/drain region 110 in an outward direction of the active fin 105. For example, the lateral protrusion end E may be a point at which the horizontal distance between the lateral protrusion P and the active fin 105 is maximized. Lateral protrusions P and lateral protrusion ends E may be formed at both sides of the source/drain region 110.
The source/drain region 110 may have a first surface SUR1 and a second surface SUR 2. The first surface SUR1 may be located at a lower portion of the source/drain region 110 with respect to the lateral protrusion end E, and may be formed to be inclined with respect to the upper surface of the substrate 101. The first surface SUR1 may extend from the lower surface of the source/drain region 110 in an outward and upward direction of the source/drain region 110. The second surface SUR2 may be located at an upper portion of the source/drain region 110 with respect to the lateral protrusion end E. The second surface SUR2 may be uneven. The second surface SUR2 may have a wave shape. The second surface SUR2 may be in contact with the first surface SUR1 to form a lateral protruding end E. The upper end MT of the merged growth part ME may be located on the second surface SUR 2. For example, the lowermost end of the valley region of the second surface SUR2 disposed between the active fins 105 may correspond to the upper end MT of the merged growth portion ME.
Gate structure 140 may be disposed to cross active fin 105 on an upper portion of active fin 105. The gate structure 140 may include a gate insulation layer 142, a first gate electrode 145, a second gate electrode 147, a gate capping layer 148, and a spacer 149.
The gate insulating layer 142 may be disposed between the active fin 105 and the first and second gate electrodes 145 and 147. The gate insulation layer 142 may include an oxide, a nitride, or a high-k dielectric material. A high-k dielectric material may mean having a higher dielectric constant than a silicon oxide film (SiO)2) The dielectric material having a high dielectric constant of (2). The high-k dielectric material may be, for example, any one selected from: aluminum oxide (Al)2O3) Tantalum oxide (Ta)2O3) Titanium oxide (TiO)2) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) Zirconium silicon oxide (ZrSi)xOy) Hafnium oxide(HfO2) Hafnium silicon oxide (HfSi)xOy) Lanthanum oxide (La)2O3) Lanthanum aluminum oxide (LaAl)xOy) Lanthanum hafnium oxide (LaHf)xOy) Hafnium aluminum oxide (HfAl)xOy) And/or praseodymium oxide (Pr)2O3). In some embodiments, the gate insulating layer 142 may be formed only on the lower surfaces of the first and second gate electrodes 145 and 147.
The first gate electrode 145 and the second gate electrode 147 may be sequentially disposed on the gate insulating layer 142. When the semiconductor device 100 is a transistor, a channel region may be formed in the active fin 105 crossing the first gate electrode 145 and the second gate electrode 147. The first gate electrode 145 and the second gate electrode 147 may be made of different materials. The first gate electrode 145 may include, for example, a metal nitride film such as a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN) film. The second gate electrode 147 may include, for example, a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. The first gate electrode 145 may be used as a diffusion break layer with respect to the second gate electrode 147, but the inventive concept is not limited thereto. In some embodiments, the gate structure 140 may include a gate electrode including a single layer, or may include a gate electrode including three or more layers.
A gate capping layer 148 may be disposed on the gate insulating layer 142, the first gate electrode 145, and the second gate electrode 147. An upper surface of the gate cap layer 148 may be substantially coplanar with an upper surface of the spacer 149. For example, the gate capping layer 148 may include at least one of a silicon nitride film and a silicon oxynitride film, but the inventive concept is not limited thereto. Furthermore, in some embodiments, the gate capping layer 148 will be omitted as desired.
Spacers 149 may be disposed on both sides of the gate cap layer 148, the first gate electrode 145, and the second gate electrode 147. The spacer 149 may be disposed in contact with a sidewall of the gate insulating layer 142. Spacers 149 may insulate the source/drain regions 110 from the first gate electrode 145 and the second gate electrode 147. The spacer 149 may be made of at least one selected from an oxide, a nitride, and an oxynitride, and may be composed of a multi-layered film.
The first interlayer insulating layer 153 may be disposed on the isolation layer 107, and may be in contact with portions of the surface of the source/drain region 110 and portions of sidewalls of the gate structure 140. The first interlayer insulating layer 153 may be in contact with a portion of the second surface SUR2 of the source/drain region 110 and the first surface SUR 1. The height of the first interlayer insulating layer 153 may be less than the height of the source/drain region 110. The height of the first interlayer insulating layer 153 may be greater than the height of the lateral protrusion end E of the source/drain region 110 and less than the height of the upper end MT of the merged grown portion ME. The first interlayer insulating layer 153 may be made of an insulating material, and may include at least one of an oxide layer, a nitride layer, and/or an oxynitride layer. For example, the first interlayer insulating layer 153 may be a ton silazane (TOSZ) film or a tetraethyl orthosilicate (TESO) film.
The etch stop layer 160 may cover an upper surface of the first interlayer insulating layer 153, a surface of the source/drain region 110 except for a region in which the contact plug 180 is disposed, and a side surface of the gate structure 140. The etch stop layer 160 may be used to detect an etch end point in a process of etching a portion of the second interlayer insulating layer 155 to form the contact plug 180. For example, the etch stop layer 160 may be made of silicon nitride (Si)3N4) And (4) preparing.
The etch stop layer 160 may have a flat lower surface SUR _ L contacting an upper surface of the first interlayer insulating layer 153 and a waved lower surface contacting an upper surface of the source/drain region 110. In some embodiments, the flat lower surface SUR _ L may be disposed at a higher level than the level LV1 of the lateral protruding end E of the source/drain region 110. Further, the flat lower surface SUR _ L may be disposed at a level lower than the level LV2 of the upper end MT of the merged growth portion ME of the source/drain region 110. In some embodiments, the flat lower surface SUR _ L may be disposed at a level matching or higher than a midpoint LV12 between the level LV1 of the laterally protruding end E of the source/drain region 110 and the level LV2 of the upper end MT of the merged growth portion ME, and matching or lower than the level LV2 of the upper end MT of the merged growth portion ME than the level LV2 of the upper end MT of the merged growth portion ME.
The second interlayer insulating layer 155 may cover the etch stop layer 160. The second interlayer insulating layer 155 may be made of the same material as the first interlayer insulating layer 153, but the inventive concept is not limited thereto.
The contact plug 180 may pass through the etch stop layer 160 and the second interlayer insulating layer 155, and may be disposed on the source/drain region 110. The contact plug 180 may electrically connect the source/drain region 110 and the upper contact plug 190. For example, the contact plug 180 may have an elongated shape when viewed from above.
In some embodiments, the contact plug 180 may be disposed such that the center line CM thereof is misaligned with the center line SDM of the source/drain region 110 in the X-axis. The center line CM of the contact plug 180 may be a line vertically passing through the center point of the contact plug 180 on the X-Y plane. The centerline SDM of the source/drain region 110 may be a line passing vertically through the center point of the source/drain region 110 in the X-Y plane. The contact plug 180 may have a shape extending in the extending direction of the gate structure 140, i.e., the Y direction (second direction), and may have a shape such as a rectangle or an ellipse.
In some embodiments, one end of the contact plug 180 disposed near one sidewall of the gate structure 140 may extend outward from one end of the source/drain region 110 by the first length L1, and the other end thereof may be disposed on the source/drain region 110. One end of the contact plug 180 disposed near the other sidewall of the gate structure 140 may be disposed on the source/drain region 110, and the other end thereof may extend outward from the other end of the source/drain region 110 by a second length L2. However, the inventive concept is not limited thereto, and the contact plugs 180 disposed at both sides of the gate structure 140 may extend in the same direction according to the arrangement of the upper contact plugs 190. The first length L1 and the second length L2 may be changed differently. The first length L1 and the second length L2 may be determined such that the contact plug 180 is connected to the upper contact plugs 190, each upper contact plug 190 being disposed on one side of each source/drain region 110. In fig. 1, the contact plug 180 is disposed at both sides of the gate structure 140, but the inventive concept is not limited thereto. The contact plug 180 may be disposed only on one side of the gate structure 140.
The lower surface of the contact plug 180 may be uneven along the shape of the upper surface of the source/drain region 110. That is, the contact plug 180 may have a wavy lower surface. Since the contact plug 180 has an uneven lower surface, a contact area with the source/drain region 110 may be increased.
The contact plug 180 may include a silicide layer 181, a barrier layer 182, and a conductive layer 184. Silicide layer 181 may be disposed between source/drain region 110 and barrier layer 182 and conductive layer 184. The silicide layer 181 may be a layer formed by siliciding the source/drain region 110 in contact with the contact plug 180, and may be omitted in some embodiments. For example, the silicide layer 181 may have a silicide structure composed of MSixDyComposition of the representation. Here, M may be a metal, and D may be an element having a different composition from M and Si. M may be one selected from Ti, Co, Ni, Ta, Pt, and/or combinations thereof, and D may be one selected from Ge, C, Ar, Kr, Xe, and/or combinations thereof.
Barrier layer 182 may function as a diffusion break layer with respect to the metal material comprising conductive layer 184. The barrier layer 182 may be formed along the upper portion of the source/drain region 110 and the sidewall of the contact plug 180. The barrier layer 182 may be a conductive metal nitride film. For example, the barrier layer 182 may be made of one selected from TiN, TaN, AlN, WN, and/or a combination thereof. Conductive layer 184 may be formed on barrier layer 182. Conductive layer 184 may include a conductive material such as Al, Cu, W, and/or Mo.
In some embodiments, the upper contact plug 190 may be an interconnection line. When the upper contact plug 190 is an interconnection line, a metal via may be formed between the contact plug 180 and the interconnection line.
Fig. 5 is a perspective view illustrating a semiconductor device according to some embodiments of the inventive concept. Fig. 6A is a sectional view taken along line a-a' of fig. 5. Fig. 6B is a sectional view taken along line B-B' of fig. 5. For convenience of description, the second interlayer insulating layer and the upper contact plug will be omitted in fig. 5. Since the semiconductor device of fig. 5, 6A, and 6B is similar to the semiconductor device described with reference to fig. 1 to 4 except for the protective layer, a description of the semiconductor device of fig. 5, 6A, and 6B will be provided based on differences from the above. Hereinafter, it will be understood that like numbers refer to like elements.
Referring to fig. 5, 6A, and 6B, the semiconductor device 100a according to some embodiments may further include a protective layer 151. The protective layer 151 may cover an upper surface of the isolation layer 107, a surface of the source/drain region 110 other than a region in which the contact plug 180 is disposed, and a side surface of the gate structure 140. The protective layer 151 may be disposed under the first interlayer insulating layer 153 and the etch stop layer 160. For example, the protective layer 151 may be made of oxide, but the inventive concept is not limited thereto. The protective layer 151 may protect the source/drain region 110 from impurity doping. The protective layer 151 may protect the source/drain regions 110 from being recessed in a process of etching the first interlayer insulating layer 153, the second interlayer insulating layer 155, and the etch stop layer 160 to form the contact plugs 180.
Fig. 7 is a perspective view illustrating a semiconductor device according to some embodiments of the inventive concept. Fig. 8A is a sectional view taken along line a-a' of fig. 7. Fig. 8B is a sectional view taken along line B-B' of fig. 7. For convenience of description, the second interlayer insulating layer and the upper contact plug will be omitted in fig. 7. Since the semiconductor device of fig. 7, 8A, and 8B is similar to the semiconductor device described with reference to fig. 1 to 4 except for the etch stop layer, a description of the semiconductor device of fig. 7, 8A, and 8B will be provided based on differences from the above. Hereinafter, it will be understood that like numbers refer to like elements.
Referring to fig. 7, 8A and 8B, the semiconductor device 100B may include an etch stop layer 160 and a first interlayer insulating layer 153. The etch stop layer 160 may cover the isolation layer 107, the source/drain region 110, and the side surfaces of the gate structure 140. The etch stop layer 160 may have a sigma (sigma) -shaped cross-section on both sides of the source/drain region 110.
The etch stop layer 160 may include a lower etch stop layer 161 and an upper etch stop layer 163. The lower etch stop layer 161 may cover the isolation layer 107, the source/drain region 110 except for the region in which the contact plug 180 is disposed, and the side surface of the gate structure 140. The lower etch stop layer 161 may have a lower upper surface SUR _ U, a first side surface SID _1, and a second side surface SID _ 2. The first corner E1 may be formed between the lower upper surface SUR _ U and the first side surface SID _ 1. The second corner E2 may be formed between the first side surface SID _1 and the second side surface SID _ 2. For example, the second corner E2 may be disposed at a level matching the level of the laterally protruding end E of the source/drain region 110. The third corner E3 may be formed between the second side surface SID _2 and the flat lower surface SUR _ L of the upper etch stop layer 163, the flat lower surface SUR _ L of the upper etch stop layer 163 being in contact with the upper surface of the first interlayer insulating layer 153.
The upper etch stop layer 163 may cover the lower etch stop layer 161 and the first interlayer insulating layer 153. The upper etch stop layer 163 may be formed in contact with a portion of the lower etch stop layer 161. The upper etch stop layer 163 may be in contact with a portion of the lower etch stop layer 161 disposed at a higher level than the third corner E3. The etch stop layer 160 may include an upper etch stop layer 163 and a lower etch stop layer 161 located at a higher level than the third corner E3. The etch stop layer 160 may include an underlying etch stop layer 161 located at a lower level than the third corner E3. A portion of the etch stop layer 160 disposed at a higher level than the third corner E3 may be thicker than a portion thereof disposed at a lower level than the third corner E3.
In some embodiments, the flat lower surface SUR _ L of the upper etch stop layer 163 may be disposed at a higher level than the lateral protruding end E of the source/drain region 110. The flat lower surface SUR _ L of the upper etch stop layer 163 may be disposed at a higher level than the level LV1' of the second corner E2. Further, the flat lower surface SUR _ L of the upper etch stop layer 163 may be disposed at a level lower than the level LV2 of the upper end MT of the merged growth portion ME of the source/drain region 110. In some embodiments, the flat lower surface SUR _ L of the upper etch stop layer 163 may be disposed at a level matching or higher than the midpoint LV12 'between the LV1' of the second corner E2 and the level LV2 of the upper end MT of the merged growth portion ME.
The sigma (Σ) shape may be formed by connecting the lower upper surface SUR _ U, the first corner E1, the first side surface SID _1, the second corner E2, the second side surface SID _2, the third corner E3 of the lower etch stop layer 161, and the flat lower surface SUR _ L of the upper etch stop layer 163.
The first interlayer insulating layer 153 may be interposed between the lower etch stop layer 161 and the upper etch stop layer 163 at both sides of the source/drain region 110. The first interlayer insulating layer 153 may cover a portion of the lower etch stop layer 161 at both sides of the source/drain region 110. The first interlayer insulating layer 153 may be formed in contact with the first and second side surfaces SID _1 and SID _2 of the lower etch stop layer 161. The first interlayer insulating layer 153 may have a sigma (sigma) -shaped surface along the surface shape of the etch stop layer 160.
Fig. 9 is a perspective view illustrating a semiconductor device according to some embodiments of the inventive concept. Fig. 10 is a sectional view taken along line B-B' of fig. 9. Since the semiconductor device of fig. 9 and 10 is similar to the semiconductor device described with reference to fig. 7, 8A, and 8B except for the protective layer, the description of the semiconductor device of fig. 9 and 10 will be provided based on the differences from the above. In the various embodiments described herein, it will be understood that like numbers refer to like elements.
Referring to fig. 9 and 10, the semiconductor device 100c may further include a protective layer 151. The protective layer 151 may be disposed on a lower portion of the lower etch stop layer 161. The protective layer 151 may cover an upper surface of the isolation layer 107, a surface of the source/drain region 110 other than a region in which the contact plug 180 is disposed, and a side surface of the gate structure 140. For example, the protective layer 151 may be made of oxide, but the inventive concept is not limited thereto. The protective layer 151 may protect the source/drain region 110 from impurity doping. The protective layer 151 may protect the source/drain regions 110 from being recessed in a process of etching the first interlayer insulating layer 153, the second interlayer insulating layer 155, and the etch stop layer 160 to form the contact plugs 180.
Fig. 11 to 24 are views illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Like numbers refer to like elements in fig. 1-30. For the sake of brief description, description of substantially the same contents as those described with reference to fig. 1 to 10 will be omitted.
Referring to fig. 11, a trench TI defining the active fin 105 may be formed by patterning the substrate 101. A pad oxide pattern 122 and a mask pattern 124 may be formed on the substrate 101. The pad oxide pattern 122 may be a layer for protecting the upper surface of the active fin 105, and may be omitted in some embodiments. The mask pattern 124 may be a mask layer for patterning the substrate 101, and may include silicon nitride, a carbon-containing material, and the like. The mask pattern 124 may have a multi-layer structure.
The trench TI may be formed by anisotropically etching the substrate 101 by using the pad oxide pattern 122 and the mask pattern 124. Since the trench TI has a high aspect ratio, its width may gradually decrease toward its lower portion. The active fin 105 may have a shape in which its width gradually decreases toward the upper portion thereof.
Referring to fig. 12, an isolation layer 107 may be formed to fill the trench TI. The isolation layer 107 may be made of an insulating material. After the isolation layer 107 fills the trench TI, a planarization process may be performed. During the planarization process, at least a portion of each of the pad oxide pattern 122 and the mask pattern 124 may be removed. In some embodiments, after a relatively thin liner layer is first formed in the trench TI, the trench TI may be filled with an isolation layer 107.
The isolation layer 107 filling the trench TI may be partially removed and the active fin 105 may protrude from the substrate 101. A portion of the isolation layer 107 may be removed, for example, by a wet etching process using at least a portion of the pad oxide pattern 122 as an etching mask. Active fin 105 may protrude upward by a height H1, and protrusion height H1 may be changed differently. The pad oxide pattern 122 may also be removed during etching.
Referring to fig. 13, a dummy gate insulating layer 132, a dummy gate electrode 135, and a spacer 149 may be formed to extend and cross the active fin 105. For example, the dummy gate insulating layer 132 and the dummy gate electrode 135 may be formed through an etching process using the mask pattern layer 136.
The dummy gate insulating layer 132 and the dummy gate electrode 135 may be formed in a region in which the gate insulating layer 142 and the first and second gate electrodes 145 and 147 (see fig. 2) are to be formed. The dummy gate insulating layer 132 and the dummy gate electrode 135 may be removed during a subsequent process. For example, the dummy gate insulating layer 132 may include silicon oxide, and the dummy gate electrode 135 may include polysilicon.
The spacer 149 may be formed by forming a film having a uniform thickness on the upper portion and sidewalls of the dummy gate insulating layer 132, the dummy gate electrode 135, and the mask pattern layer 136 and anisotropically etching the film. The spacer 149 may have a structure in which a plurality of films are stacked.
Referring to fig. 14, the active fins 105 on both sides of the spacer 149 may be selectively removed. By removing active fin 105, a recess may be formed on both sides of spacer 149. The recess may be formed by partially etching active fin 105 using a separately formed mask layer (not shown) or mask pattern layer 136 and spacer 149 as an etch mask. For example, the recess may be formed by sequentially performing a dry etching process and a wet etching process. Alternatively, after forming the recess, the surface of the recessed active fin 105 may be cured by a separate process. In some embodiments, the upper surface of the recessed active fin 105 is shown as being disposed at the same level as the upper surface of the isolation layer 107, but the inventive concept is not limited thereto. In some embodiments, the upper surface of the recessed active fin 105 may be disposed at a higher or lower level than the upper surface of the isolation layer 107.
Before or after the recess is formed, a process of implanting impurities into the active fin 105 on both sides of the dummy gate electrode 135 may be performed. The process of implanting impurities may be performed using the mask pattern layer 136 and the spacers 149 as a mask.
Referring to fig. 15, source/drain regions 110 may be formed on recessed active fin 105 on both sides of spacer 149. For example, the source/drain regions 110 may be formed using a Selective Epitaxial Growth (SEG) process. The merged growth portion ME may be formed while the source/drain regions 110 formed on the active fin 105 are connected to each other during the growth thereof.
The source/drain regions 110 formed on the active fin 105 may include the same germanium (Ge) concentration or different Ge concentrations. The source/drain regions 110 may grow along a crystallographically stable surface during their growth and may have a pentagonal or hexagonal cross-section along the Y-Z plane. However, the size and shape of the source/drain region 110 are not limited to those shown in the drawings.
The source/drain regions 110 may include impurities. The impurities may be included in-situ during the growth of the source/drain region 110, or may be included by separately implanting ions after the growth. The grown source/drain region 110 may be provided as a source region or a drain region of a semiconductor device.
Referring to fig. 16, a protective layer 151 may be formed to cover an upper surface of the mask pattern layer 136, side surfaces of the spacer 149, surfaces of the source/drain regions 110, and an upper surface of the isolation layer 107. For example, the protective layer 151 may be made of oxide, but the inventive concept is not limited thereto. The protective layer 151 may protect the source/drain region 110 from impurity doping. In addition, the protective layer 151 may protect the source/drain regions 110 from being recessed in a process of etching the first interlayer insulating layer 153, the second interlayer insulating layer 155, and the etch stop layer 160 (see fig. 5 and 9) to form the contact plugs 180. In some embodiments, the protective layer 151 may be omitted.
The lower etch stop layer 161 may be formed on the protective layer 151. The lower etch stop layer 161 may completely cover the upper surface of the protective layer 151. For example, the lower etch stop layer 161 may be deposited by Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).
Referring to fig. 17, a first interlayer insulating layer 153 may be formed on the lower etch stop layer 161. The first interlayer insulating layer 153 may be formed by forming an insulating material layer covering the lower etch stop layer 161 and performing a planarization process that exposes the upper surface of the dummy gate electrode 135. The protection layer 151, the lower etch stop layer 161, and the mask pattern layer 136 on the dummy gate electrode 135 may be removed during a planarization process to expose the upper surface of the dummy gate electrode 135. Alternatively, the mask pattern layer 136 may be removed in a subsequent planarization process of the second interlayer insulating layer 155.
Fig. 19 is a sectional view taken along line a-a' of fig. 18. Referring to fig. 18 and 19, a portion of the first interlayer insulating layer 153 may be removed. The first interlayer insulating layer 153 may be selectively removed with respect to the dummy gate electrode 135, the spacer 149, and the lower etch stop layer 161 to expose portions of the spacer 149 and portions of the lower etch stop layer 161. The first interlayer insulating layer 153 may be partially removed such that the upper surface thereof has a level matching the upper end MT of the merged growth portion ME of the source/drain region 110 or lower than the upper end MT of the merged growth portion ME of the source/drain region 110 and higher than the lateral protrusion end E of the source/drain region 110.
The upper etch stop layer 163 may be formed to cover the exposed upper portion of the spacer 149, the exposed upper portion of the lower etch stop layer 161, and the upper surface of the first interlayer insulating layer 153. The upper etch stop layer 163 may be formed in the same manner as the lower etch stop layer 161.
Referring to fig. 20, a second interlayer insulating layer 155 may be formed on the upper etch stop layer 163. The second interlayer insulating layer 155 may be formed by forming an insulating material covering the upper etch stop layer 163 and performing a planarization process exposing the upper surface of the dummy gate electrode 135. The upper etch stop layer 163 on the dummy gate electrode 135 may be removed through a planarization process to expose the upper surface of the dummy gate electrode 135. When the mask pattern layer 136 is left on the dummy gate electrode 135, the mask pattern layer 136 may be removed in a planarization process.
The dummy gate insulating layer 132 and the dummy gate electrode 135 may be removed through the exposed upper surface of the dummy gate electrode 135. The dummy gate insulating layer 132 and the dummy gate electrode 135 are selectively removed with respect to the active fin 105 and the isolation layer 107 thereunder to form a first opening OP1 for exposing the isolation layer 107 and the active fin 105. The dummy gate insulating layer 132 and the dummy gate electrode 135 may be removed by at least one of a dry etching process and a wet etching process.
Referring to fig. 21, a gate structure 140 may be formed by forming a gate insulating layer 142, first and second gate electrodes 145 and 147, and a gate capping layer 148 in the first opening OP1 (see fig. 20). The gate insulating layer 142 may be conformally formed substantially along the sidewalls and the lower surface of the first opening OP 1. The gate insulation layer 142 may include an oxide, a nitride, or a high-k dielectric material. The first gate electrode 145 and the second gate electrode 147 may include a metal or a semiconductor material. Upper portions of the gate insulating layer 142 and the first and second gate electrodes 145 and 147 may be recessed, and the gate capping layer 148 may be formed to fill the recessed region. The gate cap layer 148 may be formed and a planarization process may be performed.
Referring to fig. 22 and 23, the second opening OP2 may be formed by patterning the second interlayer insulating layer 155. The second opening OP2 may be formed in a region in which the contact plug 180 (see fig. 1, 2, 5, and 9) is to be formed by removing a portion of the second interlayer insulating layer 155 through a separate mask layer 157 such as a photoresist pattern. The upper surface of the upper etch stop layer 163 may be exposed through the second opening OP 2.
Referring to fig. 24, the upper surface of the first interlayer insulating layer 153 may be exposed by removing the upper etch stop layer 163 exposed through the second opening OP 2. The upper surface of the protective layer 151 may be exposed by removing the lower etch stop layer 161 together with the upper etch stop layer 163. In etching the upper and lower etch stop layers 163 and 161, the first interlayer insulating layer 153 and the protective layer 151 may be recessed. The upper and lower etch stop layers 163 and 161 may be removed, and the exposed protective layer 151 may be removed, so that the upper surface of the source/drain region 110 may be exposed through the second opening OP 2. In the process of etching the protection layer 151, a portion of the first interlayer insulating layer 153 and a portion of the source/drain region 110 may be recessed together. Referring to fig. 24 and 10, the contact plug 180 may be formed by sequentially forming a silicide layer 181, a blocking layer 182, and a conductive layer 184 in the second opening OP 2.
Fig. 25 to 30 are views illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Fig. 25 to 30 may be a process performed after the process of fig. 11 to 15.
Referring to fig. 25, a protective layer 151 may be formed to cover the isolation layer 107, the source/drain region 110, the dummy gate structure 130, and the spacer 149. The first interlayer insulating layer 153 may be formed on the protective layer 151. The first interlayer insulating layer 153 may be formed by forming an insulating material layer covering the protective layer 151 and performing a planarization process that exposes the upper surface of the dummy gate electrode 135. The protection layer 151 on the dummy gate electrode 135 may be removed through a planarization process to expose the upper surface of the dummy gate electrode 135. The first interlayer insulating layer 153 may be partially removed such that the upper surface thereof has a level matching the upper end MT of the merged growth portion ME of the source/drain region 110 or lower than the upper end MT of the merged growth portion ME of the source/drain region 110 and higher than the lateral protrusion end E of the source/drain region 110.
Referring to fig. 26, an etch stop layer 160 may be formed to cover an upper surface of the first interlayer insulating layer 153, an exposed upper surface of the protection layer 151, and an exposed upper surface of the dummy gate structure 130. The etch stop layer 160 may be formed by forming a layer of insulating material and performing a planarization process that exposes the upper surface of the dummy gate electrode 135.
Referring to fig. 27, the first opening OP1 may be formed by removing the dummy gate electrode 135 and the dummy gate insulating layer 132 through the exposed upper surface of the exposed dummy gate electrode 135.
Referring to fig. 28, a gate structure 140 may be formed by forming a gate insulating layer 142, first and second gate electrodes 145 and 147, and a gate capping layer 148 in the first opening OP1 (see fig. 27).
Referring to fig. 29 and 30, the second opening OP2 may be formed by patterning the second interlayer insulating layer 155. The second opening OP2 may be formed in a region in which the contact plug 180 (see fig. 1, 2, 5, and 9) is to be formed by removing a portion of the second interlayer insulating layer 155 through a separate mask layer 157 such as a photoresist pattern. The upper surface of the etch stop layer 160 may be exposed through the second opening OP 2. The etch stop layer 160 having the exposed upper surface may be removed, and the upper surface of the first interlayer insulating layer 153 and the upper surface of the protective layer 151 may be exposed. The exposed portion of the protective layer 151 may be removed and the surface of the source/drain region 110 may be partially exposed. A silicide layer 181 may be formed on the exposed surface of the exposed source/drain region 110.
Referring again to fig. 6B, the contact plug 180 may be formed by sequentially forming a barrier layer 182 and a conductive layer 184 in the second opening OP2 (see fig. 30).
According to some embodiments of the inventive concept, an etch stop layer can be provided to prevent an interlayer insulating layer from being excessively recessed in a process of forming a contact plug. The etch stop layer can be used to adjust the depth of a contact hole in which the contact plug is disposed to minimize parasitic capacitance generated between the contact plug and the gate electrode.
Although the embodiments of the present inventive concept have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various modifications may be made without departing from the scope of the inventive concept and without changing its essential characteristics. Accordingly, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.
This application claims priority to korean patent application No. 10-2018-0070820, filed on 20/6/2018, the disclosure of which is incorporated herein by reference in its entirety.
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