阅读说明：本技术 一种闪存及其制备方法 (Flash memory and preparation method thereof ) 是由 刘宪周 于 2019-09-26 设计创作，主要内容包括：本发明提供了一种闪存及其制造方法,所述闪存的制造方法包括以下步骤：提供一半导体衬底,半导体衬底包括相邻的单元区和高电阻多晶硅区,在单元区和高电阻多晶硅区的半导体衬底上均形成有字线结构；对字线结构进行P型离子注入；形成图形化的掩模层,掩模层覆盖了高电阻多晶硅区,并暴露出单元区的字线结构；以图形化的掩模层为掩模,对单元区的字线结构进行N型离子注入,并清除掩模层,以形成闪存。本发明通过在高电阻多晶硅区形成字线结构,使得无需增加掩模板的情况下,可以利用现有的掩模板制备的电阻多晶硅,其降低了生产成本；还通过上述步骤在高电阻多晶硅区形成了表面电阻高,温度系数低的字线结构。(The invention provides a flash memory and a manufacturing method thereof, wherein the manufacturing method of the flash memory comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a unit area and a high-resistance polysilicon area which are adjacent, and word line structures are formed on the semiconductor substrate of the unit area and the high-resistance polysilicon area; performing P-type ion implantation on the word line structure; forming a patterned mask layer, wherein the mask layer covers the high-resistance polysilicon region and exposes the word line structure of the unit region; and taking the patterned mask layer as a mask, carrying out N-type ion implantation on the word line structure of the unit area, and removing the mask layer to form the flash memory. According to the invention, the word line structure is formed in the high-resistance polycrystalline silicon region, so that the resistance polycrystalline silicon prepared by the existing mask plate can be utilized without increasing the mask plate, and the production cost is reduced; and forming a word line structure with high surface resistance and low temperature coefficient on the high-resistance polysilicon region through the steps.)

1. A method for preparing a flash memory is characterized by comprising the following steps:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a unit area and a high-resistance polysilicon area which are adjacent, and word line structures are formed on the semiconductor substrate of the unit area and the high-resistance polysilicon area;

carrying out P-type ion implantation on the word line structures of the unit region and the high-resistance polycrystalline silicon region;

forming a patterned mask layer on the unit region and the high-resistance polysilicon region, wherein the mask layer covers the high-resistance polysilicon region and exposes the word line structure of the unit region; and

and taking the patterned mask layer as a mask, carrying out N-type ion implantation on the word line structure of the unit area, and removing the mask layer to form the flash memory.

2. The method of claim 1, wherein the word line structure comprises a coupling oxide layer, a floating gate, a control gate, a word line, a protection layer and a first oxide layer sequentially formed on the semiconductor substrate, the word line is embedded in the floating gate and the control gate, the protection layer wraps the word line, the protection layer is located on the control gate, and the first oxide layer covers an upper surface of the word line.

3. The method according to claim 2, wherein the ions in the P-type ion implantation are P-type dopant ions, and the P-type dopant ions include at least one of boron ions, boron fluoride ions, gallium ions, and indium ions.

4. The method of claim 3, wherein the P-type ion implantation is performed at a dose of 5E¹³/cm²-1.5E¹⁴/cm²The incident angle of the P-type ion implantation is 89-91 degrees, and the energy is 5Kev-15 Kev.

5. The method of claim 4, wherein the step of performing a P-type ion implantation on the word line structures of the cell region and the high resistance polysilicon region and forming a patterned mask layer on the cell region and the high resistance polysilicon region, the mask layer covering the high resistance polysilicon region and exposing the word line structures of the cell region further comprises:

sequentially forming a first nitride layer, a second oxide layer and a patterned first photoresist layer on the first oxide layer, wherein the patterned first photoresist layer covers the word line structure of the cell region and has a first opening above the word line structure of the high-resistance polysilicon region;

etching the first nitride layer and the second oxide layer at the first opening by using the patterned first photoresist layer as a mask, and exposing the first oxide layer below the opening to form a logic well; and

and removing the residual first photoresist layer, the second oxide layer and the first nitride layer.

6. The method of manufacturing as claimed in claim 5, wherein forming a patterned mask layer on the cell region and the high-resistance polysilicon region, the mask layer covering the high-resistance polysilicon region and exposing the word line structure of the cell region comprises the steps of:

forming a polysilicon layer and a patterned second photoresist layer on the word line structure of the high-resistance polysilicon region, wherein the second photoresist layer covers the high-resistance polysilicon region and is provided with a second opening above the word line structure of the unit region; and

and etching the polycrystalline silicon layer at the second opening by taking the patterned second photoresist layer as a mask, and stopping etching on the first oxide layer to form a patterned polycrystalline silicon layer.

7. The method according to claim 6, wherein the ions implanted in the N-type ion implantation are N-type dopant ions, and the N-type dopant ions include at least one of phosphorus ions, arsenic ions, and antimony ions.

8. The method of claim 7 wherein said N-type ion implantation is performed at a dose of 1E¹⁵/cm²-10E¹⁵/cm²Said N type ionThe angle of incidence during implantation is 89-91 deg. to the surface of the substrate and the energy is 15-30 Kev.

9. A flash memory is characterized by comprising a semiconductor substrate and a high-resistance polysilicon region, wherein a word line structure with N-type heavy doping is formed in the cell region, and a word line structure with P-type light doping is formed in the high-resistance polysilicon region.

10. The flash memory of claim 9 wherein the P-type lightly doped ions comprise at least one of boron ions, boron fluoride ions, gallium ions, and indium ions.

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a flash memory and a preparation method thereof.

Background

Flash memory has become a hot point of research in non-volatile memories due to its advantages of convenience, high storage density, good reliability and the like. Since the first flash memory product appeared in the eighties of the twentieth century, with the development of technology and the storage requirements of various electronic products, flash memory is widely used in mobile and communication devices such as mobile phones, notebooks, palm computers, U disks and the like. Flash memory is a non-volatile memory that operates on the principle of storing data by changing the threshold voltage of a transistor or a memory cell to control the switching of a gate channel so that the data stored in the memory does not disappear due to a power interruption, and is a special structure of an electrically erasable and programmable read only memory. Flash memory has now taken up a large portion of the market share of non-volatile semiconductor memory, becoming the fastest growing non-volatile semiconductor memory.

Generally, the polysilicon gate located in the high resistance region of the flash memory has the problems of low resistance of the polysilicon gate surface, high temperature coefficient, and the like, and cannot meet the design requirements of the flash memory peripheral circuit.

Disclosure of Invention

The invention aims to provide a flash memory and a preparation method thereof, which are used for improving the resistance of the surface of a word line structure of a high-resistance polysilicon area and reducing the temperature coefficient of the word line structure so as to meet the design requirement of a peripheral circuit of the flash memory.

In order to solve the above technical problem, the present invention provides a method for manufacturing a flash memory, comprising the following steps:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a unit area and a high-resistance polysilicon area which are adjacent, and word line structures are formed on the semiconductor substrate of the unit area and the high-resistance polysilicon area;

carrying out P-type ion implantation on the word line structures of the unit region and the high-resistance polycrystalline silicon region;

forming a patterned mask layer on the unit region and the high-resistance polysilicon region, wherein the mask layer covers the high-resistance polysilicon region and exposes the word line structure of the unit region; and

and taking the patterned mask layer as a mask, carrying out N-type ion implantation on the word line structure of the unit area, and removing the mask layer to form the flash memory.

Optionally, the word line structure includes a coupling oxide layer, a floating gate, a control gate, a word line, a protection layer and a first oxide layer, which are sequentially formed on the semiconductor substrate, the word line is embedded in the floating gate and the control gate, the protection layer wraps the word line, the protection layer is located on the control gate, and the first oxide layer covers the upper surface of the word line.

Further, the ions in the P-type ion implantation are P-type doped ions, and the P-type doped ions include at least one of boron ions, boron fluoride ions, gallium ions and indium ions.

Further, the dosage of the P-type ion implantation is 5E¹³/cm²-1.5E¹⁴/cm²The incident angle of the P-type ion implantation is 89-91 degrees, and the energy is 5Kev-15 Kev.

Further, performing P-type ion implantation on the word line structures of the cell region and the high-resistance polysilicon region, and forming a patterned mask layer on the cell region and the high-resistance polysilicon region, where the mask layer covers the high-resistance polysilicon region and exposes the word line structures of the cell region, and further including:

sequentially forming a first nitride layer, a second oxide layer and a patterned first photoresist layer on the first oxide layer, wherein the patterned first photoresist layer covers the word line structure of the cell region and has a first opening above the word line structure of the high-resistance polysilicon region;

etching the first nitride layer and the second oxide layer at the first opening by using the patterned first photoresist layer as a mask, and exposing the first oxide layer below the opening to form a logic well; and

and removing the residual first photoresist layer, the second oxide layer and the first nitride layer.

Further, forming a patterned mask layer on the cell region and the high-resistance polysilicon region, wherein the mask layer covers the high-resistance polysilicon region and exposes the word line structure of the cell region, and the method comprises the following steps:

forming a polysilicon layer and a patterned second photoresist layer on the word line structure of the high-resistance polysilicon region, wherein the second photoresist layer covers the high-resistance polysilicon region and is provided with a second opening above the word line structure of the unit region; and

and etching the polycrystalline silicon layer at the second opening by taking the patterned second photoresist layer as a mask, and stopping etching on the first oxide layer to form a patterned polycrystalline silicon layer.

Furthermore, the ions injected in the N-type ion implantation are N-type doped ions, and the N-type doped ions include at least one of phosphorus ions, arsenic ions and antimony ions.

Further, the dosage of the N-type ion implantation is 1E¹⁵/cm²-10E¹⁵/cm²The incident angle of the N-type ion implantation is 89-91 degrees, and the energy is 15Kev-30 Kev.

The invention also provides a flash memory, which comprises a semiconductor substrate, wherein the semiconductor substrate comprises a unit area and a high-resistance polysilicon area, a word line structure with N-type heavy doping is formed in the unit area, and a word line structure with P-type light doping is formed in the high-resistance polysilicon area.

Optionally, the P-type lightly doped ions include at least one of boron ions, boron fluoride ions, gallium ions, and indium ions.

Compared with the prior art, the method has the following beneficial effects:

the invention provides a flash memory and a manufacturing method thereof, wherein the manufacturing method of the flash memory comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a unit area and a high-resistance polysilicon area which are adjacent, and word line structures are formed on the semiconductor substrate of the unit area and the high-resistance polysilicon area; carrying out P-type ion implantation on the word line structures of the unit region and the high-resistance polycrystalline silicon region; forming a patterned mask layer on the unit region and the high-resistance polysilicon region, wherein the mask layer covers the high-resistance polysilicon region and exposes the word line structure of the unit region; and taking the patterned mask layer as a mask, carrying out N-type ion implantation on the word line structure of the unit area, and removing the mask layer to form the flash memory. According to the invention, the word line structure is formed on the high-resistance polysilicon region, so that the existing mask plate can be utilized to prepare the resistance polysilicon of the high-resistance polysilicon region without increasing the mask plate, and the production cost is reduced. Meanwhile, a word line structure with high surface resistance and low temperature coefficient is formed in the high-resistance polysilicon region through the steps, so that the design requirement of a peripheral circuit of the flash memory is met.

Drawings

FIG. 1 is a diagram illustrating a typical flash memory structure;

FIG. 2 is a schematic flow chart illustrating a method for manufacturing a flash memory according to an embodiment of the present invention;

FIGS. 3a-3e are schematic diagrams of the flash memory of an embodiment of the present invention in various steps;

description of reference numerals:

in fig. 1:

i-a unit region; II-logical area;

10-a semiconductor substrate; 11-a coupling oxide layer; 12-a floating gate; 13-a control gate; 14-word line; 20-high resistance polysilicon gate;

in FIGS. 3a-3 e:

i-a unit region; II-high resistance polysilicon region;

100-a semiconductor substrate; 110. 120-word line architecture; 111-coupling oxide layer; 112-floating gate; 113-a control gate; 114-a word line; 115-a protective layer; 116-a first oxide layer;

210-a first nitride layer; 220-a second oxide layer; 230-a first photoresist layer;

300-a mask layer; 310-a polysilicon layer; 320-a second photoresist layer.

Detailed Description

Fig. 1 is a schematic structural diagram of a typical flash memory. As shown in fig. 1, a typical flash memory manufacturing process in the prior art includes:

step S11: providing a semiconductor substrate 10, wherein the semiconductor substrate 10 comprises a unit region I and a high-resistance polysilicon region II, a word line structure is formed on the semiconductor substrate 10 in the unit region I, and a high-resistance polysilicon gate 20 is formed on the semiconductor substrate 10 in the high-resistance polysilicon region II; the word line structure comprises a coupling oxide layer 11, a floating gate 12, a control gate 13 and a word line 14 which are sequentially formed on the semiconductor substrate 10, wherein the word line 14 is embedded in the floating gate 12 and the control gate 13, the word line 14 is located on the coupling oxide layer 11, and the coupling oxide layer 11 is further formed between the high-resistance polysilicon gate 20 and the semiconductor substrate 10; and the surface of the word line 14 is planarized by a CMP (chemical mechanical planarization or chemical mechanical polishing) process.

Step S12: carrying out N-type ion implantation on the word line 14, wherein the implantation dosage is 1E¹⁵/cm²-10E¹⁵/cm²The implant angle is xx and the energy is 15Kev-30Kev to form a flash memory.

The inventors have studied and found that, in step S11, the structure (high-resistance polysilicon gate) formed on the semiconductor substrate in the logic region is different from the word line structure formed on the semiconductor substrate in the cell region, so that the masks used for the two are different, which results in higher process cost. In addition, the high-resistance polysilicon gate of the flash memory prepared by the process has low surface resistance and high temperature coefficient, and cannot meet the design requirement of a flash memory peripheral circuit.

Based on the above research, the present invention provides a flash memory and a method for manufacturing the same, wherein the method for manufacturing the flash memory comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a unit area and a high-resistance polysilicon area which are adjacent, and word line structures are formed on the semiconductor substrate of the unit area and the high-resistance polysilicon area; carrying out P-type ion implantation on the word line structures of the unit region and the high-resistance polycrystalline silicon region; forming a patterned mask layer on the unit region and the high-resistance polysilicon region, wherein the mask layer covers the high-resistance polysilicon region and exposes the word line structure of the unit region; and taking the patterned mask layer as a mask, carrying out N-type ion implantation on the word line structure of the unit area, and removing the mask layer to form the flash memory. According to the invention, the word line structure is formed on the high-resistance polysilicon region, so that the existing mask plate can be utilized to prepare the resistance polysilicon of the high-resistance polysilicon region without increasing the mask plate, and the production cost is reduced. Meanwhile, a word line structure with high surface resistance and low temperature coefficient is formed in the high-resistance polysilicon region through the steps, so that the design requirement of a peripheral circuit of the flash memory is met.

A flash memory and a method for fabricating the same according to the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.

In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.

Fig. 2 is a schematic flow chart of a method for manufacturing a flash memory according to the present embodiment. As shown in fig. 2, the embodiment provides a method for manufacturing a flash memory, including the following steps:

step S21: providing a semiconductor substrate, wherein the semiconductor substrate comprises a unit area and a high-resistance polysilicon area which are adjacent, and word line structures are formed on the semiconductor substrate of the unit area and the high-resistance polysilicon area;

step S22: carrying out P-type ion implantation on the word line structures of the unit region and the high-resistance polycrystalline silicon region;

step S23: forming a patterned mask layer on the unit region and the high-resistance polysilicon region, wherein the mask layer covers the high-resistance polysilicon region and exposes the word line structure of the unit region; and

step S24: and taking the patterned mask layer as a mask, carrying out N-type ion implantation on the word line structure of the unit area, and removing the mask layer to form the flash memory.

The method for manufacturing the split-gate flash memory disclosed in this embodiment is described in more detail with reference to fig. 2 to 3 e.

As shown in fig. 3a, step S21 is first executed to provide a semiconductor substrate 100, where the semiconductor substrate 100 includes a cell region I and a High resistance polysilicon (HR) region II adjacent to each other, and word line structures 110 and 120 are formed on the semiconductor substrate 100 in the cell region I and the HR region II, where the word line structure 110 is located in the cell region I and the word line structure 120 is located in the HR region II. It can be seen that in this embodiment, a word line structure having the same structure as the cell region I is formed in the HR region to replace the existing high-resistance polysilicon gate, so that the structures in the cell region I and the HR region II can be formed simultaneously, a mask plate specially used for forming the high-resistance polysilicon gate in the HR region II is also saved, and the production cost is reduced.

It should be noted that, for ease of understanding, only one word line structure 110 in the cell region I and one word line structure 120 in the HR region II are shown in this embodiment, but actually, there is not only one word line structure 110 in the cell region I and one word line structure 120 in the HR region II.

Specifically, first, a semiconductor substrate 100 is provided, where the semiconductor substrate 100 may provide an operation platform for a subsequent process, and may be any substrate for carrying components of a semiconductor integrated circuit, which is well known to those skilled in the art, and may be a bare chip, or a wafer processed by an epitaxial growth process, and in detail, the semiconductor substrate 100 may be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium substrate, a silicon-germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator (ge) substrate. The word line structures 110 and 120 include, for example, a coupling oxide layer 111, a floating gate 112, a control gate 113, a word line 114 embedded in the floating gate 112 and the control gate 113, and a protective layer 115 covering the word line 114, where the protective layer 115 is located on the control gate 113, and a material of the protective layer 115 is, for example, an oxide, and covers sidewalls of the word line 114. The material of the coupling oxide layer 111 includes, but is not limited to, silicon dioxide, and preferably silicon dioxide, which is beneficial to increase the interface adhesion between layers, the coupling oxide layer 111 is used to isolate the semiconductor substrate 100 and the floating gate 112, the thickness of the coupling oxide layer can be changed according to specific process requirements, the floating gate 112 can trap or lose electrons, so that the finally formed flash memory can have the functions of storage and erasure, and the thickness of the coupling oxide layer can be determined according to the process requirements.

Next, a first oxide layer 116 is further formed on the word line structures 110 and 120 of the cell region I and the high-resistance polysilicon region II, specifically, for example, a chemical vapor deposition process or a physical vapor deposition process is used to form the first oxide layer 116 on the word line structures 110 and 120 of the cell region I and the high-resistance polysilicon region II, and the first oxide layer 116 covers the upper surface of the word line 114; the first oxide layer 116 is planarized by a CMP process. The first oxide layer 116 is advantageous for preventing the word line 114 from being damaged by a subsequent ion implantation process. The material of the first oxide layer 116 is, for example, silicon oxide, and the thickness of the first oxide layer 116 is, for example

As shown in fig. 3b, next, step S22 is performed to perform P-type ion implantation on the word line structures 110 and 120 in the cell region I and the high resistance polysilicon region II, so as to form a word line structure with high surface resistance and low temperature coefficient in the high resistance polysilicon region, thereby meeting the design requirements of the peripheral circuit of the flash memory.

Specifically, P-type ion implantation is performed on the word line structures 110 and 120 from above the first oxide layer 116 in the cell region I and the high-resistance polysilicon region II.

In this step, the ions in the P-type ion implantation are P-type doped ions (i.e., ions with a P-type conductivity), and the P-type doped ions include boron (B) ions and Boron Fluoride (BF)₂At least one of a + ion, a gallium (Ga) ion and an indium (In) ion, and specifically a boron ion. The dosage of the P-type ion implantation is 5E¹³/cm²-1.5E¹⁴/cm²The incident angle of the P-type ion implantation is 89-91 degrees, and the energy is 5Kev-15 Kev.

As shown in fig. 3c, a first nitride layer 210, a second oxide layer 220 and a patterned first photoresist layer 230 are sequentially formed on the first oxide layer 116, for example, by a chemical vapor deposition process to sequentially form the first nitride layer 210 and the second oxide layer 220 on the first oxide layer 116, the material of the first nitride layer 210 is, for example, silicon nitride, and the thickness of the first nitride layer 210 is, for example, the thickness of the first nitride layer 210

The material of the second oxide layer 220 is, for example, silicon oxide, and the thickness of the second oxide layer 220 is, for example

The patterned first photoresist layer 230 covers the word line structure 110 of the cell region I and has a first opening above the word line structure 120 of the high-resistance polysilicon region II, wherein the thickness of the patterned first photoresist layer 230 is, for example, the

Then, using the patterned first photoresist layer 230 as a mask, the first nitride layer 210 and the second oxide layer 220 at the first opening are etched to expose the first oxide layer 116 under the opening, so as to form a logic well. Here, the preparation is performed by using the existing process, and thus, a detailed description is not required. The related process is performed only on the high-resistance polysilicon region II when the logic well is formed, thereby reducing the influence of the process on the word line structure of the cell region I.

Next, the remaining first photoresist layer 230, second oxide layer 220, and first nitride layer 210 are removed.

As shown in fig. 3d, next, step S23 is performed to form a patterned mask layer 300 on the cell region I and the high-resistance polysilicon region II, where the mask layer 300 covers the high-resistance polysilicon region II and exposes the word line structure 110 of the cell region I. Wherein the mask layer 300 includes a patterned second photoresist layer 320 and a patterned polysilicon layer 310.

The method specifically comprises the following steps:

as shown in fig. 3d, first, a polysilicon layer 310 and a patterned second photoresist layer 320 are formed on the word line structure 120 of the high resistance polysilicon region II, and the second photoresist layer 320 covers the high resistance polysilicon region II and has a second opening above the word line structure 110 of the cell region I.

Then, the patterned second photoresist layer 320 is used as a mask to etch the polysilicon layer 310 at the second opening, and the etching is stopped on the first oxide layer 116 to form the patterned polysilicon layer 310. Wherein the thickness of the polysilicon layer 310 is, for example

The thickness of the patterned second photoresist layer 320 is, for example

As shown in fig. 3e, next, in step S24, using the patterned mask layer 300 as a mask, N-type ion implantation is performed on the word line structure 110 in the cell region I, and the mask layer 300 is removed to form a flash memory. The target of the N-type ion implantation in this step is the word line structure 110 of the cell region I, rather than the polysilicon gate of the resistive polysilicon region II in the prior art, which is beneficial to reducing the temperature coefficient.

Specifically, first, N-type ion implantation is performed on the word line structure 110 in the cell region I by using the patterned second photoresist layer 320 and the patterned polysilicon layer 310 as masks.

In this step, the ions implanted in the N-type ion implantation are N-type dopant ions (i.e., ions having a conductivity type of N-type), which include, for example, at least one of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions, and specifically, phosphorus (P) ions. This step can form a word line with an N-type heavily doped polysilicon gate. The dosage of the N-type ion implantation is 1E¹⁵/cm²-10E¹⁵/cm²The incident angle of the N-type ion implantation is 89-91 degrees, and the energy is 15Kev-30 Kev.

Next, the second photoresist layer 320 and the polysilicon layer 310 located in the high resistance polysilicon region II are removed.

Next, a sidewall spacer is formed on the sidewall of the word line structure 120 of the high resistance polysilicon region II to form a flash memory.

With reference to fig. 3e, the present invention further provides a flash memory, including: the semiconductor device comprises a semiconductor substrate 100, wherein the semiconductor substrate 100 comprises a unit area I and a high-resistance polysilicon area II, a word line structure 110 is formed in the unit area I, and the word line structure 110 is provided with N-type heavy doping; a word line structure 120 is formed on the high-resistance polysilicon region II, a side wall is formed on the side wall of the word line structure 120, the word line structure 120 has P-type light doping, and the high-resistance polysilicon region of the structure has high surface resistance and low temperature coefficient, so that the design requirement of the peripheral circuit of the flash memory is met.

In summary, the present invention provides a flash memory and a method for manufacturing the same, wherein the method for manufacturing the flash memory comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a unit area and a high-resistance polysilicon area which are adjacent, and word line structures are formed on the semiconductor substrate of the unit area and the high-resistance polysilicon area; carrying out P-type ion implantation on the word line structures of the unit region and the high-resistance polycrystalline silicon region; forming a patterned mask layer on the unit region and the high-resistance polysilicon region, wherein the mask layer covers the high-resistance polysilicon region and exposes the word line structure of the unit region; and taking the patterned mask layer as a mask, carrying out N-type ion implantation on the word line structure of the unit area, and removing the mask layer to form the flash memory. According to the invention, the word line structure is formed on the high-resistance polysilicon region, so that the existing mask plate can be utilized to prepare the resistance polysilicon of the high-resistance polysilicon region without increasing the mask plate, and the production cost is reduced. Meanwhile, a word line structure with high surface resistance and low temperature coefficient is formed in the high-resistance polysilicon region through the steps, so that the design requirement of a peripheral circuit of the flash memory is met.

In addition, unless otherwise specified or indicated, the description of the terms "first" and "second" in the specification is only used for distinguishing various components, elements, steps and the like in the specification, and is not used for representing logical relationships or sequential relationships among the various components, elements, steps and the like.

It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.