Shielded cell capacitor array
阅读说明:本技术 屏蔽单元电容器阵列 (Shielded cell capacitor array ) 是由 阿龙·J·卡菲 布里安·G·德罗斯特 于 2019-06-27 设计创作,主要内容包括:集成电路上的电容器阵列包括多个单元电容器。每个单元电容器包括形成在柱结构中的孤立电容器节点。每个单元电容器还包括与孤立电容器节点相邻的共享电容器。共享电容器节点电联接到阵列中的其他单元电容器的共享电容器节点。每个单元电容器还包括屏蔽节点,其联接到低阻抗节点,并且形成在孤立电容器节点附近,以减少导体与孤立节点和共享节点之间形成电容的机会,从而防止不需要的电荷进入共享节点并减少阵列的线性度。(A capacitor array on an integrated circuit includes a plurality of cell capacitors. Each cell capacitor includes an isolated capacitor node formed in a pillar structure. Each cell capacitor also includes a shared capacitor adjacent to the isolated capacitor node. The shared capacitor node is electrically coupled to shared capacitor nodes of other cell capacitors in the array. Each cell capacitor also includes a shield node coupled to the low impedance node and formed near the isolated capacitor node to reduce the chance of a conductor forming a capacitance with the isolated node and the shared node, thereby preventing unwanted charge from entering the shared node and reducing the linearity of the array.)
1. A capacitor array on an integrated circuit, comprising:
a plurality of cell capacitors, each cell capacitor including,
isolated capacitor nodes formed in a vertical structure on two or more metal layers of an integrated circuit and coupled by at least one via between each metal layer; a shared capacitor node formed adjacent to the isolated capacitor node, the shared capacitor node being coupled to shared capacitor nodes of other unit capacitors of the plurality of unit capacitors through a low impedance path; and a shield node formed adjacent to the isolated capacitor node in the at least one metal layer in which the isolated capacitor node is formed, the shield node being coupled to the low impedance node.
2. The capacitor array of claim 1, wherein:
the shared capacitor node is disposed in an Nth metal layer above the N-1 metal layer, wherein a top of the isolated capacitor node is disposed in the N-1 metal layer, wherein N is an integer greater than or equal to 3.
3. The capacitor array of claim 1, wherein:
the shared capacitor node includes two fingers in the same metal layer with a top portion of a capacitor orphan node disposed between the two fingers of the shared capacitor node in the same metal layer.
4. The capacitor array of claim 1, wherein the shared capacitor node forms a ring around the orphan capacitor node in the same metal layer, a top of the orphan capacitor node being disposed in the metal layer.
5. The capacitor array of claim 1, wherein the shield node forms a ring around the isolated capacitor node and is disposed at a different metal layer than the shared capacitor node.
6. The capacitor array of any of claims 1-5, wherein a conductor electrically connected to a base of the orphan capacitor node terminates below the shield node.
7. The capacitor array of any of claims 1-5, wherein routing conductors into the array to connect to respective isolated capacitor nodes is provided in a single metal layer.
8. The capacitor array of claim 7, wherein respective ones of the conductors enter the array on each of four sides of the array in the single metal layer.
9. The capacitor array of claim 7, wherein the shielding node is formed in a metal layer closer to the single metal layer than an nth metal layer that provides the shared capacitor node, where N is an integer of at least 4.
10. The capacitor array of any of claims 1-5, wherein the array is a binary weighted capacitor array having a common centroid placement for at least higher weighted capacitor values, thereby eliminating linear process gradients in the x and y directions for higher weighted capacitance values.
11. The capacitor array of any one of claims 1 to 5, further comprising a plurality of dummy cell capacitors formed on a periphery of the array, the dummy cell capacitors coupled to the low impedance node.
12. A method of manufacturing a capacitor array, comprising:
forming a plurality of cell capacitors, wherein forming each cell capacitor comprises,
forming an isolated capacitor node in a vertical structure comprising two or more metal layers of an integrated circuit and one or more vias between each of the two or more metal layers; forming a shared capacitor node adjacent to a first portion of the isolated capacitor node in an nth metal layer, N being three or an integer greater than three;
forming a shielding node in at least one metal layer except the nth metal layer; and
a shield conductor is formed to be coupled to shield the low impedance node.
13. The method of fabricating a capacitor array of claim 12, further comprising:
the top of the isolated capacitor node in the (N-1) th metal layer is formed.
14. The method of fabricating a capacitor array of claim 12, further comprising forming the shared capacitor node as two fingers in a same metal layer, wherein a top of an orphan capacitor node is disposed therein, the top of the orphan capacitor node being disposed between the two fingers in the same metal layer.
15. The method of fabricating a capacitor array of claim 12, further comprising forming the shared capacitor node as a ring structure surrounding the isolated capacitor node in the same metal layer, with a top portion of the isolated capacitor node formed therein.
16. The method of fabricating a capacitor array of claim 12, further comprising forming a shield node in a ring around the isolated capacitor node in a different metal layer than the nth metal layer.
17. The method of fabricating a capacitor array of any of claims 12-16, further comprising:
routing conductors to the capacitor array using a single metal layer to couple to respective isolated capacitor nodes; and
the conductors connected to the respective isolated capacitor nodes below the respective shield nodes are terminated.
18. The method of fabricating a capacitor array of claim 17, further comprising forming conductors into the capacitor array on every four sides of the capacitor array in the single metal layer.
19. The method of fabricating a capacitor array of claim 17, further comprising: a shield node is formed in a metal layer closer to the single metal layer than an nth metal layer in which the shared capacitor node is disposed, where N is four or an integer greater than four.
20. The method of fabricating a capacitor array of any one of claims 12 to 16, further comprising aggregating cell capacitors in the capacitor array to form a binary weighted capacitor array having a common centroid placement for higher weighted aggregate capacitor values, thereby eliminating linear process gradients in the x and y directions for higher weighted aggregate capacitor values.
21. A capacitor array, comprising:
a plurality of cell capacitors, each cell capacitor including,
an isolated capacitor node formed on a plurality of metal layers of an integrated circuit with at least one via between each of the plurality of metal layers; a shared capacitor node adjacent to the isolated capacitor node in at least one of a vertical or horizontal direction; and a shield node formed by at least two fingers, the shield node being adjacent to the isolated capacitor node on at least one of the plurality of metal layers and on a different metal layer than the shared capacitor node.
Technical Field
Embodiments described herein relate to capacitors, and more particularly, to cell capacitors used in capacitor arrays in integrated circuits.
Background
Capacitor arrays are used in a variety of applications, such as digital-to-analog converters (DACs). Capacitive DACs are commonly used for high performance data converters. In an integrated circuit, a capacitor array is formed by using cell capacitors and, if necessary, aggregating the cell capacitors to form different capacitor weights for the array. However, designers are reluctant to move to geometries with smaller cell capacitance values (e.g., less than 1 femtofarad (fF)) due to the greater risk of differential and integral non-linearities resulting from cell capacitor mismatch.
Thus, the improved cell capacitors may result in a more accurate capacitor array for DACs and other applications using capacitor arrays.
Disclosure of Invention
Accordingly, in one embodiment, a capacitor array on an integrated circuit, comprising: a plurality of cell capacitors, each cell capacitor including, an isolated capacitor node, formed in a vertical structure on two or more metal layers of an integrated circuit and coupled through at least one via between each metal layer. Each cell capacitor further includes a shared capacitor node formed adjacent to the isolated capacitor node, the shared capacitor node coupled to shared capacitor nodes of other of the plurality of cell capacitors through a low impedance path. Each cell capacitor further includes a shield node formed adjacent to the isolated capacitor node in at least one metal layer in which the isolated capacitor node is formed, the shield node being coupled to the low impedance node.
In another embodiment, a method of manufacturing a capacitor array includes: forming a plurality of cell capacitors, wherein forming each cell capacitor comprises forming an isolated capacitor node in a vertical structure comprising two or more metal layers of an integrated circuit and one or more vias between each of the two or more metal layers. Forming each cell capacitor further comprises: forming a shared capacitor node adjacent to a first portion of the isolated capacitor node in the nth metal layer, N being three or an integer greater than three. Forming a shielding node in at least one metal layer except the nth metal layer; and forming a shield conductor to couple to shield the low impedance node.
In another embodiment, a capacitor array includes: a plurality of cell capacitors. Each cell capacitor includes an isolated capacitor node formed on a plurality of metal layers of the integrated circuit with at least one via between each of the plurality of metal layers. Each cell capacitor further includes a shared capacitor node adjacent to the isolated capacitor node in at least one of a vertical or horizontal direction. Each cell capacitor also includes a shield node formed by at least two fingers, the shield node being adjacent to the isolated capacitor node on at least one of the plurality of metal layers and on a different metal layer than the shared capacitor node.
Drawings
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
Fig. 1A shows a top view of a first prior art cell capacitor.
Fig. 1B shows a north-south cross-section of a cell capacitor showing isolated nodes.
Fig. 1C shows an east-west cross section of a cell capacitor showing isolated nodes and shared nodes.
Fig. 2A shows a top view of a second prior art cell capacitor.
Fig. 2B shows a north-south cross-section of a cell capacitor showing a shared node and an isolated node.
Fig. 2C shows an east-west cross section of the cell capacitor, showing isolated nodes and shared nodes.
Fig. 3A shows a top view of a third prior art cell capacitor.
Fig. 3B shows a north-south cross-section of a cell capacitor showing isolated nodes and shared nodes.
Fig. 3C shows an east-west cross section of the cell capacitor showing isolated nodes and shared nodes.
Fig. 4A shows a top view of a fourth prior art cell capacitor.
Fig. 4B shows a north-south cross-section of a cell capacitor showing isolated nodes and shared nodes.
Fig. 4C shows an east-west cross section of the cell capacitor, showing isolated nodes and shared nodes.
Fig. 5A illustrates a top view of a cell capacitor according to an embodiment.
Fig. 5B shows a north-south cross-section of a cell capacitor, showing isolated nodes.
Fig. 5C shows an east-west cross section of a cell capacitor showing a shared node, a shield node, and an isolated node.
Fig. 5D shows an east-west cross-section of a cell capacitor showing termination of a conductor to an isolated node under a shield node.
Fig. 5E schematically shows how the capacitor array has isolated nodes and shared nodes.
Fig. 6A illustrates a top view of a cell capacitor according to an embodiment.
Fig. 6B shows a north-south cross-section of a cell capacitor showing a shared node and an isolated node.
Fig. 6C shows an east-west cross section of a cell capacitor showing a shared node, a shield node, and an isolated node.
Fig. 6D shows an east-west cross-section of the cell capacitor showing the termination of the conductor to the isolated node below the shield node.
Fig. 7A illustrates a top view of a cell capacitor according to an embodiment.
Fig. 7B shows a north-south cross-section of a cell capacitor showing the shared node, the shield node, and the isolated node.
Fig. 7C shows an east-west cross section of a cell capacitor showing a shared node, a shield node, and an isolated node.
Fig. 7D shows a north-south cross-section of the cell capacitor showing the termination of the conductor to the isolated node below the shield node.
Fig. 7E shows an east-west cross-section of the cell capacitor showing the termination of the conductor to the isolated node below the shield node.
Fig. 8A illustrates a top view of a cell capacitor according to an embodiment.
Fig. 8B shows a north-south cross-section of a cell capacitor showing the shared node, the shield node, and the isolated node.
Fig. 8C shows an east-west cross section of a cell capacitor showing a shared node, a shield node, and an isolated node.
Fig. 8D shows a north-south cross-section of the cell capacitor showing the termination of the conductor to the isolated node below the shield node.
Fig. 8E shows an east-west cross-section of the cell capacitor showing the termination of the conductor to the isolated node below the shield node.
Fig. 9 shows a perspective view of an embodiment of a cell capacitor.
Fig. 10 shows a perspective view of another embodiment of a cell capacitor.
Fig. 11 shows a perspective view of another embodiment of a cell capacitor.
Fig. 12 shows a four-bit binary-weighted capacitor array.
Fig. 13 shows a top view of a four-bit binary-weighted capacitor array showing the routing of conductors to isolated nodes of the array.
FIG. 14 shows a top view of a four-bit binary array showing the shield nodes on the second metal layer and the routing on the first metal layer.
Fig. 15 shows a six-bit binary-weighted array formed from four-bit binary-weighted arrays.
The use of the same reference symbols in different drawings indicates similar or identical items.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Although manufacturing variations may be a source of non-linearity in the capacitor array, systematic irregularities in the layout may result in significant non-linearity, especially for cell capacitors with low capacitance. As further explained herein, irregularities in layout and routing may negatively impact cell capacitor uniformity, and thus addressing such irregularities may improve cell capacitor matching and thus improve the linearity of the capacitor array and applications such as capacitor DACs. This irregularity typically occurs when cell capacitors are connected together (or aggregated) to form each DAC tap (e.g., for a binary coded capacitor array, bit 0(b0) results in one cell capacitor, b1 results in two cell capacitors, b2 results in four cell capacitors, etc.). The mismatch of capacitor DAC cell capacitors with low capacitance cell capacitors will have a more pronounced effect than higher capacitance cell capacitors. A lower capacitance cell capacitor design that remains matched would allow higher performance circuits to be more power efficient. In addition, using smaller cell capacitors reduces the overall area (i.e., cost) of the design.
FIGS. 1A-4C illustrate various prior art approaches to cell capacitor design. Fig. 1A shows a top view of a cell capacitor with a
Fig. 2A shows a second prior art approach with a wider metal area formed on top of the cell capacitor to form the top of the shared
Fig. 3A shows another embodiment of a prior art cell capacitor array, in which the top of the shared
Fig. 4A shows another embodiment of a prior art cell capacitor array, in which a wider metal area forms the top plate of the cell capacitor's shared
Routing to the isolated node may result in parasitic capacitance being formed between the shared node and the conductor of the isolated node, and in unwanted charge being injected into the shared node as the conductor of the isolated node switch. The unwanted charge causes non-linearity of the capacitor array. To address this issue, embodiments embed shielding into the cell capacitors such that the wiring (also referred to herein as a conductor) to each cell capacitor in the array does not cause parasitic capacitance to form between the wiring of the shared (output) node and the isolated node of the cell capacitor. In capacitor DAC applications, this wiring is used for DAC taps into the weighting array. In addition, the embodiments described herein with embedded shielding alleviate the routing limitations caused by the shared nodes encapsulating isolated nodes.
Some exemplary cell capacitors that incorporate embedded shielding are shown below. Referring to fig. 5A-5D, one embodiment provides an improved cell capacitor that is well suited for small capacitance values of the cell capacitor. Fig. 5A shows a top view of a
Fig. 5E schematically illustrates how the shared node 503 (as shown by capacitor plate 530) of all cell capacitors is coupled to the
Fig. 6A shows another embodiment which provides an improved cell capacitor that is well suited for small cell capacitance values. Fig. 6A shows a top view of a
Fig. 6D shows the routing of a
Fig. 7A shows another embodiment, which provides an improved cell capacitor, which is well suited for small cell capacitance values. Fig. 7A shows a top view of a
Fig. 7D shows a north-south cross-section of the
Fig. 7E shows an east-west cross-section of the
Fig. 8A shows another embodiment which provides an improved cell capacitor well suited for small cell capacitance values. Fig. 8A shows a top view of a
Fig. 8D shows a north-south cross-section of the
Fig. 8E shows an east-west cross-section of the
Fig. 9 shows a perspective view of a cell capacitor similar to that shown in fig. 5A to 5D. Fig. 9 shows isolated nodes 901 as finger structures having a shorter length than the shared node 903 and the shield node 905. In other embodiments, the length and shape of the isolated nodes may be different. As shown in fig. 9, the shared node 903 is formed by two fingers on either side of the top of the isolated node. A shield node 905 is formed on either side of the isolated node and below the shared node. Fig. 9 shows a via 902 that couples different metal layers of isolated nodes (in black). Although two vias connecting each layer of isolated nodes are shown, other embodiments may have more or fewer vias. The example of fig. 9 shows three metal layers for isolated nodes, but other embodiments may form pillar structures of isolated nodes in other numbers of metal layers (e.g., four, five, or six). The shared node and the shield node may each be formed on one or more metal layers. In the embodiments of fig. 5A to 5D and fig. 9, the lateral capacitance between the shared node and the isolated node dominates the capacitance of the cell capacitor.
Fig. 10 shows a perspective view of a cell capacitor similar to that shown in fig. 9, except that isolated nodes 1001 are formed in four metal layers (M1-M4) joined by vias 1002. The shared node 1003 is formed at M4 and the shield node 1005 is formed at M2 and is closer to the isolated node wiring on M1 than M4 forming the shared node. Positioning the shield node closer to the isolated node wiring helps reduce the additional capacitance formed between the isolated node wiring and the shared node.
The cell capacitors described herein provide reduced parasitic capacitance between the wiring to the isolated node and the shared node. This achieves better linearity. The cell capacitors described herein allow the use of 0.1fF cell capacitors, even as low as.075 fF cell capacitors.
Fig. 11 shows a perspective view of a cell capacitor similar to that shown in fig. 6A to 6D. As shown in fig. 11, the shared
The cell capacitors with embedded shields can be aggregated into capacitors of different sizes to form a binary coded capacitor array that can be used in a DAC, for example. The use of embedded shielding helps to ensure that the wiring for the DAC taps is used to drive the binary coded capacitors in the array, with minimal impact on the linearity of the data converter. Fig. 12 shows a top view of the cell capacitor of fig. 5A aggregated with binary weighting to form a four-bit binary-weighted capacitor array that may be used in a DAC or other application.
The bit labels of the array are underneath the pillar structures of the isolated nodes. Thus, a single cell capacitor forms bit 0. Two cell capacitors form
Fig. 13 shows a top view of the four bit array of fig. 12 with some of the array structure removed to more easily see the wiring on M1 and connected to the various cell capacitors. The wiring shown has the same cross-hatch pattern as the isolated nodes.
FIG. 14 shows another top view of the four-bit array of FIG. 12 at the M2 level, showing the shield nodes. Fig. 14 shows the shield nodes associated with each cell capacitor, as well as
Fig. 15 shows how the four-bit binary-weighted array structure of fig. 12 is utilized to form a 6-bit capacitor array. Fig. 15 shows the routing of the drive array entering the array from four sides. Note that some cells are not contiguous. For example, it can be seen that b2 is formed by four cell capacitors, two on the top and two on the bottom, driven by four
The flexibility of the structure of the cell capacitors and the routing to isolated nodes allows for common centroid placement of the capacitor arrays. Common centroid placement allows cancellation of linear process gradients in the x-y direction. Still referring to fig. 15, the 32 cell capacitors driven by bit b5 are formed symmetrically in the x and y directions around the center of the array. Thus, the common centroid placement of FIG. 15 helps ensure that linear process gradients are eliminated in the x-y direction. Similarly, bits b4, b3, and b2 have a common centroid placement. It can be seen that
Thus, various embodiments for cell capacitors and their use in capacitor arrays have been described. The description of the invention set forth herein is illustrative, and is not intended to limit the scope of the invention as set forth in the following claims. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope and spirit of the invention as set forth in the following claims.
- 上一篇:一种医用注射器针头装配设备
- 下一篇:一种集成碳化硅晶体管及其制造方法