阅读说明：本技术 半导体器件
(Semiconductor device with a plurality of transistors
) 是由 洪世基
金柱然
金辰昱 于 2019-04-10 设计创作，主要内容包括：本发明提供了一种半导体器件,所述半导体器件包括：衬底,所述衬底具有第一区域和第二区域；第一栅电极层,所述第一栅电极层位于所述第一区域上,并且包括第一导电层；以及第二栅电极层,所述第二栅电极层位于所述第二区域上,并且包括所述第一导电层、位于所述第一导电层上的第二导电层以及位于所述第二导电层上的阻挡金属层,其中,所述第一栅电极层的上表面位于比所述第二栅电极层的上表面低的水平高度上。(The present invention provides a semiconductor device, including: a substrate having a first region and a second region; a first gate electrode layer over the first region and including a first conductive layer; and a second gate electrode layer which is located over the second region and includes the first conductive layer, a second conductive layer located over the first conductive layer, and a barrier metal layer located over the second conductive layer, wherein an upper surface of the first gate electrode layer is located at a lower level than an upper surface of the second gate electrode layer.)
1. A semiconductor device, comprising:
a substrate having a first region and a second region;
a first gate electrode layer over the first region and including a first conductive layer; and
a second gate electrode layer over the second region and including the first conductive layer, a second conductive layer over the first conductive layer, and a barrier metal layer over the second conductive layer,
wherein an upper surface of the first gate electrode layer is located at a lower level than an upper surface of the second gate electrode layer.
2. The semiconductor device according to claim 1, wherein a thickness of the first gate electrode layer is smaller than a thickness of the second gate electrode layer.
3. The semiconductor device according to claim 1, wherein a width of the second gate electrode layer is equal to or narrower than a width of the first gate electrode layer.
4. The semiconductor device according to claim 1, wherein the first conductive layer in the first gate electrode layer has a flat upper surface, and the first conductive layer in the second gate electrode layer has a curved upper surface.
5. The semiconductor device according to claim 1, wherein the first conductive layer in the second gate electrode layer has a U-shape.
6. The semiconductor device according to claim 1, wherein a width of an upper portion of the second conductive layer in the second gate electrode layer is wider than a width of a lower portion of the second conductive layer.
7. The semiconductor device according to claim 1, wherein the first conductive layer comprises a material having a work function larger than that of the second conductive layer.
8. The semiconductor device according to claim 1, wherein the first conductive layer comprises TiN and the second conductive layer comprises TiAlC.
9. The semiconductor device of claim 1, further comprising a first gate dielectric layer disposed between the first gate electrode layer and the substrate and a second gate dielectric layer disposed between the second gate electrode layer and the substrate.
10. The semiconductor device of claim 9, wherein at least one of the first and second gate dielectric layers comprises at least one of lanthanum, gadolinium, ruthenium, yttrium, and scandium.
11. The semiconductor device of claim 1, further comprising a gate capping layer on an upper surface of the first gate electrode layer and on an upper surface of the second gate electrode layer.
12. The semiconductor device of claim 11, wherein a thickness of the gate capping layer is greater over the first gate electrode layer than over the second gate electrode layer.
13. The semiconductor device according to claim 1, wherein a first transistor including the first gate electrode layer and a second transistor including the second gate electrode layer are p-type MOSFETs, and an operating voltage of the first transistor is lower than an operating voltage of the second transistor.
14. The semiconductor device of claim 1, wherein:
the substrate further comprises a third region which is,
the semiconductor device further includes a third gate electrode layer which is located over the third region and includes the first conductive layer, the second conductive layer located over the first conductive layer, and the barrier metal layer located over the second conductive layer, and
the thickness of the first conductive layer of the second gate electrode layer is different from the thickness of the first conductive layer of the third gate electrode layer.
15. The semiconductor device of claim 1, wherein:
the substrate further comprises a third region which is,
the semiconductor device further includes a third gate electrode layer located on the third region and including the first conductive layer, the second conductive layer located on the first conductive layer, and the barrier metal layer located on the second conductive layer, an
First to third gate dielectric layers respectively between one of the first to third gate electrode layers and the substrate, and
the first and second gate dielectric layers comprise the same material, and the third gate dielectric layer comprises a material different from the material of the first and second gate dielectric layers.
16. The semiconductor device according to claim 15, wherein a second transistor including the second gate electrode layer and a third transistor including the third gate electrode layer are p-type MOSFETs, and an operating voltage of the second transistor is lower than an operating voltage of the third transistor.
17. The semiconductor device of claim 1, wherein:
the substrate further comprises a third region which is,
the semiconductor device further includes a third gate electrode layer which is located over the third region and includes the first conductive layer, the second conductive layer located over the first conductive layer, the barrier metal layer located over the second conductive layer, and an upper metal layer located over the barrier metal layer, and
the width of the third gate electrode layer is wider than the width of the first gate electrode layer.
18. The semiconductor device according to claim 17, wherein the first to third transistors respectively including the first to third gate electrode layers are p-type MOSFETs.
19. The semiconductor device of claim 1, wherein:
the substrate further comprises a third region which is,
the semiconductor device further includes a third gate electrode layer which is located over the third region and includes the second conductive layer and the barrier metal layer located over the second conductive layer, and
the first transistor and the second transistor, which comprise a first gate electrode layer and a second gate electrode layer, respectively, are p-type MOSFETs, and the third transistor, which comprises the third gate electrode layer, is an n-type MOSFET.
20. The semiconductor device according to claim 1, wherein the first conductive layer in the first gate electrode layer comprises two layers comprising the same material but having different crystallinities.
21. A semiconductor device, comprising:
a substrate having a first region and a second region;
a first gate electrode layer over the first region and including a first conductive layer; and
a second gate electrode layer located over the second region and including a first conductive layer and a second conductive layer located over the first conductive layer and having a work function lower than that of the first conductive layer,
wherein the first conductive layer in the first gate electrode layer has a substantially constant width, and the second conductive layer in the second gate electrode layer has a shape in which an upper width is wider than a lower width.
22. The semiconductor device according to claim 21, wherein the first gate electrode layer is formed of the first conductive layer.
23. The semiconductor device according to claim 21, wherein the first gate electrode layer and the second gate electrode layer have substantially the same width.
24. The semiconductor device according to claim 21, wherein the second gate electrode layer further comprises a barrier metal layer on the second conductive layer and an upper metal layer on the barrier metal layer, the second gate electrode layer having a wider width than the first gate electrode layer.
25. A semiconductor device, comprising:
a semiconductor substrate including a first region and a second region having impurities of the same conductivity type;
a first gate electrode layer over the first region and including a first conductive layer; and
a second gate electrode layer over the second region and including the first conductive layer and a second conductive layer over the first conductive layer,
wherein a thickness of the second gate electrode layer is larger than a thickness of the first gate electrode layer, and an operating voltage of a first transistor including the first gate electrode layer is different from an operating voltage of a second transistor including the second gate electrode layer.
Technical Field
The present disclosure relates to semiconductor devices.
Background
As the demand for high performance, high speed, and/or versatility of semiconductor devices increases, the integration of semiconductor devices increases. With the trend toward higher integration of semiconductor devices, the size reduction of transistors in the semiconductor devices is accelerating, and methods of forming transistors having various operating voltages and reduced sizes are being studied. In addition, in order to overcome the limitation of the operation characteristics due to the size reduction of a planar metal oxide semiconductor fet (mosfet), efforts have been made to develop a semiconductor device including a fin field effect transistor (FinFET) having a channel with a three-dimensional structure.
Disclosure of Invention
According to an aspect of the embodiment, a semiconductor device includes: a substrate having a first region and a second region; a first gate electrode layer provided over the first region and including a first conductive layer; and a second gate electrode layer which is provided over the second region and includes a first conductive layer, a second conductive layer provided over the first conductive layer, and a barrier metal layer provided over the second conductive layer, wherein an upper surface of the first gate electrode layer is located at a lower level than an upper surface of the second gate electrode layer.
According to another aspect of the embodiments, a semiconductor device includes: a substrate having a first region and a second region; a first gate electrode layer provided over the first region and including a first conductive layer; and a second gate electrode layer which is provided over the second region and includes a first conductive layer and a second conductive layer which is provided over the first conductive layer and has a work function lower than that of the first conductive layer, wherein the first conductive layer in the first gate electrode layer has a substantially constant width, and the second conductive layer in the second gate electrode layer has a shape in which an upper width is wider than a lower width.
According to still another aspect of the embodiment, a semiconductor device includes: a semiconductor substrate having a first region and a second region having impurities of the same conductivity type; a first gate electrode layer provided over the first region and including a first conductive layer; and a second gate electrode layer which is provided over the second region and includes the first conductive layer and a second conductive layer provided over the first conductive layer, wherein a thickness of the second gate electrode layer is larger than a thickness of the first gate electrode layer, and an operating voltage of a first transistor including the first gate electrode layer is different from an operating voltage of a second transistor including the second gate electrode layer.
Drawings
Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, wherein:
fig. 1 illustrates a top view of a semiconductor device according to an exemplary embodiment;
FIG. 2A illustrates a cross-sectional view of the semiconductor device of FIG. 1 taken along lines I-I ', II-II ', III-III ', IV-IV ', and V-V ', respectively;
FIG. 2B illustrates a cross-sectional view of the semiconductor device of FIG. 1 taken along lines A-A ', B-B ', C-C ', D-D ', and E-E ', respectively;
fig. 3A to 3C illustrate partial enlarged views of a portion of a semiconductor device according to an exemplary embodiment;
fig. 4 and 5 illustrate cross-sectional views of a semiconductor device according to an exemplary embodiment;
fig. 6 illustrates a cross-sectional view of a semiconductor device according to an exemplary embodiment;
fig. 7 illustrates a cross-sectional view of a semiconductor device according to an exemplary embodiment;
fig. 8 illustrates a flow chart of a method of manufacturing a semiconductor device according to an exemplary embodiment;
fig. 9A to 9L illustrate cross-sectional views of stages in a method of manufacturing a semiconductor device according to an exemplary embodiment;
fig. 10 illustrates a block diagram of an electronic apparatus including a semiconductor device according to an exemplary embodiment; and
fig. 11 illustrates a schematic diagram of a system including a semiconductor device, according to an example embodiment.
Detailed Description
Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.
Fig. 1 is a top view illustrating a semiconductor device according to an exemplary embodiment. FIG. 2A is a cross-sectional view illustrating the semiconductor device of FIG. 1 cut along lines I-I ', II-II ', III-III ', IV-IV ', and V-V ', respectively; fig. 2B is a cross-sectional view illustrating the semiconductor device of fig. 1 taken along lines a-a ', B-B ', C-C ', D-D ', and E-E ', respectively. For convenience of explanation, only main components of the semiconductor device are illustrated in fig. 1, 2A, and 2B.
Referring to fig. 1, 2A and 2B, the semiconductor device 100 may include: substrate 101 having first through fifth regions R1, R2, R3, R4, and R5, active fin 105, source/drain regions 150, interface layer 112, first and second gate dielectric layers 114 and 115, gate spacer layer 116, and first through fourth gate electrode layers GE1, GE2, GE3, and GE 4. The semiconductor device 100 may further include an isolation layer 107, a gate capping layer 140, and an interlayer insulating layer 190.
The semiconductor device 100 may include a fin field effect transistor (FinFET) element in which the active fin 105 has a fin structure. The FinFET element may include first to fifth transistors 10, 20, 30, 40, and 50 having an active fin 105 and first to fourth gate electrode layers GE1, GE2, GE3, and GE4 crossing each other. For example, the first to fifth transistors 10, 20, 30, 40 and 50 may be p-type Metal Oxide Semiconductor (MOS) field effect transistors (MOSFETs). The first to fifth transistors 10, 20, 30, 40, and 50 may be transistors driven at threshold voltages different from each other, and may constitute the same or different circuits in the semiconductor device 100.
The substrate 101 may have different first to fifth regions R1, R2, R3, R4, and R5. The first to fifth regions R1, R2, R3, R4, and R5 may be regions in which the first to fifth transistors 10, 20, 30, 40, and 50 are respectively disposed. The first to fifth regions R1, R2, R3, R4, and R5 may be disposed to be spaced apart from or adjacent to each other in the semiconductor device 100.
The substrate 101 may have an upper surface extending in the X-direction and the Y-direction. The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may comprise silicon, germanium, or silicon germanium. The substrate 101 may be provided as, for example, a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer, among others.
The isolation layer 107 may define the active fin 105 in the substrate 101, as illustrated in fig. 2B. The isolation layer 107 may be formed, for example, by a Shallow Trench Isolation (STI) process. According to an embodiment, the isolation layer 107 may include a region extending deeper into a lower portion of the substrate 101 between adjacent active fins 105. According to an embodiment, the isolation layer 107 may have a curved upper surface having a relatively higher level when closer to the active fin 105, and the shapes of the upper surface and the lower surface of the isolation layer 107 are not limited to the shapes illustrated in the drawings. The isolation layer 107 may be made of an insulating material. The isolation layer 107 may be, for example, an oxide, a nitride, or a combination thereof.
The active fin 105 may be defined in the substrate 101 by an isolation layer 107 and may be arranged to extend in one direction (e.g., in an X-direction). The active fin 105 may have, for example, a line shape or a stripe shape extending in the X direction (fig. 1), and may protrude from the substrate 101 (e.g., protrude above the substrate 101) between the isolation layers 107 to have a width in the Y direction (fig. 2B). Although fig. 1 illustrates a pair of active fins 105 respectively disposed in the first to fifth regions R1, R2, R3, R4, and R5, the arrangement and number of active fins 105 are not limited thereto. For example, one or three or more active fins 105 may be provided in each of the first to fifth regions R1, R2, R3, R4, and R5.
The active fin 105 may be part of the substrate 101 and may include an epitaxial layer grown from the substrate 101. As illustrated in fig. 2A, active fin 105 may be partially recessed at both sides of first to fourth gate electrode layers GE1, GE2, GE3, and GE4, and source/drain regions 150 may be disposed on recessed active fin 105. For example, as illustrated in fig. 1, each of first-fourth gate electrode layers GE1, GE2, GE3, and GE4 may extend in the Y direction to intersect active fin 105, and two source/drain regions 150 may be provided on each recessed active fin 105 located on opposite sides of each of first-fourth gate electrode layers GE1, GE2, GE3, and GE4, for example (fig. 2A). Accordingly, as illustrated in fig. 2B, the active fin 105 may have a relatively high height at lower portions of the first to fourth gate electrode layers GE1, GE2, GE3, and GE 4. In an exemplary embodiment, the active fin 105 may include an impurity.
Source/drain regions 150 may be disposed on active fin 105 on, for example, both sides of each of first through fourth gate electrode layers GE1, GE2, GE3, and GE 4. The source/drain region 150 may be provided as a source region or a drain region of the first to fifth transistors 10, 20, 30, 40 and 50. Source/drain region 150 may have a raised source/drain shape with an upper surface positioned higher than lower surfaces of first-fourth gate electrode layers GE1, GE2, GE3, and GE 4. According to embodiments, the source/drain regions 150 may be connected to each other, or may merge over two or more active fins 105 to form one source/drain region 150.
The source/drain region 150 may be formed of an epitaxial layer and may include impurities. For example, source/drain regions 150 may comprise p-type doped silicon germanium (SiGe). When the source/drain regions 150 include silicon germanium (SiGe), stress may be applied to channel regions of the first to fifth transistors 10, 20, 30, 40 and 50, which are part of the active fin 105 formed of silicon (Si), to improve hole mobility. In an exemplary embodiment, the source/drain region 150 may include a plurality of regions having different concentrations of elements and/or doping elements.
Interface layer 112 and first and second gate dielectric layers 114 and 115 may be disposed between active fin 105 and first-fourth gate electrode layers GE1, GE2, GE3, and GE 4. The first gate dielectric layer 114 may be disposed in the first, second, fourth, and fifth regions R1, R2, R4, and R5, and the second gate dielectric layer 115 may be disposed in the third region R3. First and second gate dielectric layers 114 and 115 may be disposed to cover lower surfaces and both side surfaces of first to fourth gate electrode layers GE1, GE2, GE3, and GE 4. In an exemplary embodiment, first gate dielectric layer 114 and second gate dielectric layer 115 may be formed only on lower surfaces of first to fourth gate electrode layers GE1, GE2, GE3 and GE 4.
The interfacial layer 112 may be made of a dielectric material, such as a silicon oxide film, a silicon oxynitride, or a combination thereof. First gate dielectric layer 114 and second gate dielectric layer 115 may comprise an oxide, nitride, or high-k material. A high-k material may refer to a material having a higher dielectric constant than silicon oxide (SiO)2) The dielectric material of (4). The high dielectric constant material may be alumina (Al)2O3) Tantalum oxide (Ta)2O3) Titanium oxide (TiO)2) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) Zirconium silicon oxide (ZrSi)xOy) Hafnium oxide (HfO)2) Hafnium silicon oxide (HfSi)xOy) Lanthanum oxide (La)2O3) Lanthanum aluminum oxide (LaAl)xOy) Lanthanum hafnium oxide (LaHf)xOy) Hafnium aluminum oxide (HfAl)xOy) And praseodymium oxide (Pr)2O3) Any one of them. The first gate dielectric layer 114 and the second gate dielectric layer 115 may include materials different from each other. The second gate dielectric layer 115 may be made of the same material as the first gate dielectric layer 114, and may further include an element for increasing a threshold voltage of the transistor. For example, the second gate dielectric layer 115 may further include a rare earth element, such as lanthanum (La), gadolinium (Gd), ruthenium (Ru), yttrium (Y), and scandium (Sc). These elements may increase the threshold voltage, for example by forming an electric dipole.
The gate spacer layer 116 may be disposed at both sides of the first to fourth gate electrode layers GE1, GE2, GE3, and GE 4. Gate spacer layer 116 may insulate source/drain regions 150 from first-fourth gate electrode layers GE1, GE2, GE3, and GE 4. According to an embodiment, the gate spacer layer 116 may be a multi-layer structure. The gate spacer layer 116 may be made of oxide, nitride, or oxynitride, and may be formed as a low-k film, among others.
First through fourth gate electrode layers GE1, GE2, GE3, and GE4 may be disposed across active fin 105 at an upper portion of active fin 105 and extend in one direction, for example, in the Y direction. Channel regions of first to fifth transistors 10, 20, 30, 40, and 50 may be formed in portions of active fin 105 that intersect first to fourth gate electrode layers GE1, GE2, GE3, and GE 4. The first gate electrode layer GE1 may be disposed in the first region R1, the second gate electrode layer GE2 may be disposed in the second region R2 and the third region R3, the third gate electrode layer GE3 may be disposed in the fourth region R4, and the fourth gate electrode layer GE4 may be disposed in the fifth region R5. The first to fourth gate electrode layers GE1, GE2, GE3, and GE4 may have first to fifth lengths L1, L2, L3, L4, and L5 in the channel direction (i.e., in the X direction) in the first to fifth regions R1, R2, R3, R4, and R5, respectively. The first to fifth lengths L1, L2, L3, L4, and L5 may be equal to or correspond to channel lengths of the first to fifth transistors 10, 20, 30, 40, and 50. The first through fourth lengths L1, L2, L3, L4 may be substantially the same as or similar to each other and may be shorter than the fifth length L5. For example, the first to fourth lengths L1, L2, L3 and L4 may be 50nm or less, and the fifth length L5 may be 50nm to 300 nm.
First-fourth gate electrode layers GE1, GE2, GE3, and GE4 may include first conductive layer 120a, second conductive layer 120b, third conductive layer 120c, and fourth conductive layer 120d, respectively, which have different thicknesses. In detail, the first gate electrode layer GE1 may include the preliminary first conductive layer 120P and the first conductive layer 120 a. The second gate electrode layer GE2 may include a second conductive layer 120b, a fifth conductive layer 132, and a barrier metal layer 134. The third gate electrode layer GE3 may include a third conductive layer 120c, a fifth conductive layer 132, and a barrier metal layer 134. Fourth gate electrode layer GE4 may include preliminary first conductive layer 120P, fourth conductive layer 120d, fifth conductive layer 132, barrier metal layer 134, and upper metal layer 136. The relative thickness of each of the first to fourth gate electrode layers GE1, GE2, GE3, and GE4 is not limited to the relative thickness shown in the drawings, and various changes may be made in the embodiments.
An upper surface of first gate electrode layer GE1 may be located at a first height H1 in the Z-direction from an upper surface of active fin 105. Upper surfaces of second through fourth gate electrode layers GE2, GE3, and GE4 may be located at second through fourth heights H2, H3, and H4 in the Z direction from the upper surface of active fin 105. Second height H2 and third height H3 may be higher than first height H1. The fourth height H4 may also be higher than the first height H1, but is not limited thereto. For example, the upper surface of first gate electrode layer GE1 may be located at a lower level than the upper surfaces of second through fourth gate electrode layers GE2, GE3, and GE 4. Accordingly, the thickness of first gate electrode layer GE1 may be less than the thickness of second through fourth gate electrode layers GE2, GE3, and GE 4. Second height H2 and third height H3 may be substantially the same, and fourth height H4 may be the same or similar to second height H2 and third height H3, but is not limited thereto. For example, the fourth height H4 may be lower than the second height H2 and the third height H3.
The first to fourth conductive layers 120a, 120b, 120c, and 120d may have a first work function, and may be, for example, layers containing a metal element. The first to fourth conductive layers 120a, 120b, 120c and 120d may be made of the same material and may have different thicknesses from each other. The first to fourth conductive layers 120a, 120b, 120c, and 120d may include a material having a higher work function than the fifth conductive layer 132. For example, each of the first to fourth conductive layers 120a, 120b, 120c and 120d may include TiN, TaN, W, WCN or a combination thereof. The preliminary first conductive layer 120P may be formed of the same material as the first to fourth conductive layers 120a, 120b, 120c and 120d, but may be slightly different in crystallinity and physical properties due to the heat treatment, so that its interface with the first conductive layer 120a and the fourth conductive layer 120d may be recognized.
In first gate electrode layer GE1, first conductive layer 120a may be disposed on preliminary first conductive layer 120P and may completely fill the space defined by first gate dielectric layer 114 and gate capping layer 140 and preliminary first conductive layer 120P. For example, as illustrated in fig. 2A, the first conductive layer 120a may have a constant width in the X direction. The first conductive layer 120a may have a flat upper surface, and the upper surface may be in contact with the gate capping layer 140.
In the second gate electrode layer GE2, a second conductive layer 120b may be disposed on the first gate dielectric layer 114 in the second region R2 and the second gate dielectric layer 115 in the third region R3, respectively. Second conductive layer 120b may be arranged in a U-shape or the like, and may not completely fill the space defined by first and second gate dielectric layers 114 and 115 and gate capping layer 140. For example, as illustrated in fig. 2A, the second conductive layer 120b may cover the bottom and inner sidewalls of each of the first and second gate dielectric layers 114 and 115, and may leave a space for the fifth conductive layer 132 at the center thereof. The second conductive layer 120b may include a region having an upper width smaller than a lower width, for example, a total width of a top portion of the second conductive layer 120b may be smaller than a total width of a bottom portion of the second conductive layer 120b in the X direction (fig. 2A). Width may refer to a width (e.g., distance) measured from the sides (e.g., inner sidewalls) of first gate dielectric layer 114 and second gate dielectric layer 115 in the X-direction. As illustrated, the second conductive layer 120b may have a curved upper surface (e.g., an outer surface facing the fifth conductive layer 132), and may have an upper surface with a concave region.
In the third gate electrode layer GE3, the third conductive layer 120c may be disposed on the first gate dielectric layer 114, may be arranged in a U-shape or the like, and may not completely fill the space defined by the first gate dielectric layer 114 and the gate capping layer 140. The third conductive layer 120c may include a region having an upper width smaller than a lower width. Specifically, the thickness of the third conductive layer 120c may be smaller than the thickness of the second conductive layer 120b of the second gate electrode layer GE2 in the upper region having a relatively large thickness, for example, the total width of the top of the second conductive layer 120b may be greater than the total width of the top of the third conductive layer 120c in the X direction (fig. 2A). The third conductive layer 120c may have a curved upper surface, and may have an upper surface having a concave area.
In fourth gate electrode layer GE4, fourth conductive layer 120d may be conformally disposed on preliminary first conductive layer 120P, and may not completely fill the space defined by first gate dielectric layer 114 and gate capping layer 140. The thickness of fourth conductive layer 120d may be greater than, for example, the thickness of each of second conductive layer 120b of second gate electrode layer GE2 and third conductive layer 120c of third gate electrode layer GE 3. The fourth conductive layer 120d may have a stepped upper surface, and may have an upper surface having a concave area.
The fifth conductive layer 132 may have a second work function lower than the first work function, and may be, for example, a layer containing a metal element. For example, the fifth conductive layer 132 may include an alloy containing aluminum (Al), a conductive metal carbide containing Al, a conductive metal nitride containing Al, or a combination thereof, and may include TiAl, TiAlC, TiAlN, or a combination thereof.
Fifth conductive layer 132 in second gate electrode layer GE2 and third gate electrode layer GE3 may be disposed on second conductive layer 120b and third conductive layer 120c and may have a curved upper surface with a concave region. Fifth conductive layer 132 may be conformally formed along second conductive layer 120b and third conductive layer 120c, for example, along the outer curved surface of each of second conductive layer 120b and third conductive layer 120 c. For example, since the top width of each of second conductive layer 120b and third conductive layer 120c is less than the respective bottom width, the conformal structure of fifth conductive layer 132 at the top may define a concave region in the center of the top of each of second gate electrode layer GE2 and third gate electrode layer GE 3.
In detail, in the second gate electrode layer GE2, due to the relatively narrow space, the fifth conductive layer 132 may be configured to, for example, completely fill a space between opposite surfaces of a lower portion (e.g., a bottom portion) of the second conductive layer 120b, and for example, the fifth conductive layer 132 may have a Y shape. In third gate electrode layer GE3, since a space between opposing surfaces of a lower portion (e.g., a bottom portion) of third conductive layer 120c is wider than that in second gate electrode layer GE2, fifth conductive layer 132 may be configured to fill the space only partially, for example, and fifth conductive layer 132 may have a U-shape, for example. Accordingly, fifth conductive layer 132 in second gate electrode layer GE2 and third gate electrode layer GE3 may have a U-shape, a Y-shape, or the like. The fifth conductive layer 132 may have a shape in which the width of the upper portion is wider than that of the lower portion. In this case, the width may refer to a distance from one end to the other end in the X direction (e.g., between opposite ends of the fifth conductive layer 132 in the X direction), and may refer to a distance between both ends (e.g., opposite ends) of the fifth conductive layer 132 including the barrier metal layer 134 between both ends of the fifth conductive layer 132 in an upper region of the fifth conductive layer 132.
Fifth conductive layer 132 in fourth gate electrode layer GE4 may be conformally disposed on fourth conductive layer 120 d. Fifth conductive layer 132 in fourth gate electrode layer GE4 may not completely fill the space between opposing surfaces of fourth conductive layer 120d, e.g., fifth conductive layer 132 in fourth gate electrode layer GE4 may have a U-shape along an outer surface of fourth conductive layer 120d (fig. 2A).
The barrier metal layer 134 may include a material different from that of the fifth conductive layer 132, and may include, for example, TiN, TaN, W, WCN, or a combination thereof. The upper metal layer 136 may include a material different from that of the barrier metal layer 134, and may include, for example, TiN, TaN, W, WCN, or a combination thereof. According to an embodiment, the barrier metal layer 134 and the upper metal layer 136 are not necessarily made of a metal material, but may be made of a semiconductor material, such as polysilicon.
Barrier metal layer 134 in second gate electrode layer GE2 and third gate electrode layer GE3 may be disposed on fifth conductive layer 132 and may completely fill a concave region between fifth conductive layers 132, e.g., barrier metal layer 134 may completely fill a concave region defined by fifth conductive layer 132 above second gate electrode layer GE2 and third gate electrode layer GE 3. The barrier metal layer 134 may have a flat upper surface in contact with the gate capping layer 140. Barrier metal layer 134 in second gate electrode layer GE2 and third gate electrode layer GE3 may have a narrower width in the lower portion than in the upper portion. In particular, the barrier metal layer 134 in the third gate electrode layer GE3 may have a relatively thin and long protrusion at a lower portion. The specific shape of barrier metal layer 134 in second gate electrode layer GE2 and third gate electrode layer GE3 may vary according to the second to fourth lengths L2, L3, and L4 of second gate electrode layer GE2 and third gate electrode layer GE3, and the thicknesses of second to fifth conductive layers 120b, 120c, 120d, and 132, and the like.
In fourth gate electrode layer GE4, barrier metal layer 134 may almost or completely fill the space between the opposite surfaces of fifth conductive layer 132. Upper metal layer 136 may be disposed at least on barrier metal layer 134 of fourth gate electrode layer GE4 and may extend to an upper portion of fifth conductive layer 132 and fourth conductive layer 120 d. The upper metal layer 136 may have a non-uniform thickness, but is not limited thereto.
The first to fifth transistors 10, 20, 30, 40 and 50 may all be MOSFETs of the same conductivity type, may have threshold voltages different from each other, and thus have operating voltages different from each other. For example, the first to fifth transistors 10, 20, 30, 40 and 50 may all be p-type MOSFETs. The first transistor 10 may have the lowest threshold voltage and operating voltage, and the threshold voltage and operating voltage of the second transistor 20 may be higher than those of the first transistor 10. The threshold voltage and the operating voltage of the third transistor 30 may be higher than those of the second transistor 20, and the threshold voltage and the operating voltage of the fourth transistor 40 may be higher than those of the third transistor 30. The threshold voltage and the operating voltage of the fifth transistor 50 may be higher than those of the fourth transistor 40. In this specification, the magnitudes of the threshold voltage and the operating voltage may be compared in absolute values. The difference in threshold voltage and operating voltage between the first transistor 10, the second transistor 20, and the fourth transistor 40 may be determined by the difference in the structures of the first to third gate electrode layers GE1, GE2, and GE 3. Also, the difference in threshold voltage and operating voltage between the second transistor 20 and the third transistor 30 may be due to the difference between the first gate dielectric layer 114 and the second gate dielectric layer 115.
In the embodiment in which the first to fourth conductive layers 120a, 120b, 120c, and 120d are made of TiN and the fifth conductive layer 132 is made of TiAlC, the threshold voltage in the structure of the first transistor 10 is reduced by about 47mV as compared to the threshold voltage in the structure of the second transistor 20. In addition, the threshold voltage in the structure of the transistor including the first gate electrode layer GE1 and the second gate dielectric layer 115 was reduced by about 60mV compared to the structure of the third transistor 30. It can be seen that the threshold voltage of the p-type MOSFET can be relatively reduced without the fifth conductive layer 132 in the first gate electrode layer GE 1.
In an exemplary embodiment, semiconductor device 100 may further include a sixth transistor having second gate dielectric layer 115 and third gate electrode layer GE3 and/or a seventh transistor having second gate dielectric layer 115 and fourth gate electrode layer GE 4. In this case, the threshold voltage and the operating voltage of the sixth transistor may be higher than those of the fourth transistor 40, and the threshold voltage and the operating voltage of the seventh transistor may be higher than those of the fifth transistor 50. Even in the case where the transistors have relatively long channel lengths, four or more transistors having different threshold voltages and operating voltages may be provided by different combinations of the first and second gate dielectric layers 114 and 115 and the first to fifth conductive layers 120a, 120b, 120c, 120d, and 132, similarly to the first to fourth transistors 10, 20, 30, and 40.
In an exemplary embodiment, the semiconductor device 100 may not include at least one of the second to fifth transistors 20, 30, 40, and 50. For example, the semiconductor device 100 may include only the first transistor 10 and the second transistor 20, or may include only the first transistor 10 and the fourth transistor 40. As described above, the type of transistor included in the semiconductor device 100 may be variously selected according to the range of operating voltage required in the semiconductor device 100.
The gate capping layer 140 may be disposed to fill a region between the gate spacer layers 116 on the first to fourth gate electrode layers GE1, GE2, GE3 and GE 4. The gate capping layer 140 may have a first thickness T1 in the Z direction on the first gate electrode layer GE1, and may have a second thickness T2 in the Z direction greater than the first thickness T1 on the second to fourth gate electrode layers GE2, GE3, and GE4 (fig. 2A). The thickness of the gate capping layer 140 may be variously changed according to embodiments.
An interlayer insulating layer 190 may be disposed to cover upper surfaces of the isolation layer 107, the source/drain regions 150, and the first to fourth gate electrode layers GE1, GE2, GE3, and GE 4. The interlayer insulating layer 190 may include, for example, at least one of oxide, nitride, and oxynitride, and may include a low dielectric material.
Fig. 3A to 3C are partial enlarged views illustrating a portion of a semiconductor device according to an exemplary embodiment. Fig. 3A to 3C illustrate regions corresponding to the region "a" of fig. 2A.
Referring to fig. 3A, the second gate electrode layer GE2 of fig. 2A is shown on an enlarged scale. Second gate electrode layer GE2 may have an upper surface that is the same height as first gate dielectric layer 114.
In second gate electrode layer GE2, fifth conductive layer 132 may have a first width W1 in an upper region and a second width W2 narrower than first width W1 in a lower region. The barrier metal layer 134 may be disposed to be surrounded by the fifth conductive layer 132 at an upper portion of the fifth conductive layer 132. The barrier metal layer 134 may also have an upper width wider than a lower width. The barrier metal layer 134 may be disposed only in a region where the fifth conductive layer 132 has a relatively wide width, and may not extend downward.
Referring to fig. 3B, the upper surface of second gate electrode layer GE2a may be located at a higher level than the upper surface of first gate dielectric layer 114 a. Second conductive layer 120b of second gate electrode layer GE2a may cover an upper surface of first gate dielectric layer 114a in an edge region of second gate electrode layer GE2 a. Accordingly, the profiles of the fifth conductive layer 132 and the barrier metal layer 134 may be changed accordingly.
The reduced height first gate dielectric layer 114a may be formed such that a portion of the first gate dielectric layer 114a is etched along with the first layer 122 and the second layer 124 during the process described below with reference to fig. 9H.
Referring to fig. 3C, unlike fig. 3A and 3B, second gate electrode layer GE2B may have a non-planar upper surface. The second gate electrode layer GE2b may have a curved upper surface, and the gate capping layer 140 may have a concave upper surface having a greater thickness toward the central portion. The shape of the upper surface of second gate electrode layer GE2b may be formed by changing an etching rate, which is changed due to the flow of the etchant changed according to the region, during the process described below with reference to fig. 9L.
As described above with reference to fig. 3A to 3C, the shapes of the respective layers constituting the second gate electrode layer GE2 and the shape of the peripheral layer may be variously changed in the embodiment. Similarly, in the other gate electrode layers GE1, GE3, and GE4 described above with reference to fig. 2A, the shapes of the respective layers constituting the gate electrode layers GE1, GE3, and GE4 and the relative configuration with the peripheral layers may be changed variously in the embodiment.
Fig. 4 and 5 are cross-sectional views illustrating a semiconductor device according to an exemplary embodiment.
Referring to fig. 4, in the semiconductor device 100a, the substrate 101 may have first to fifth regions R1, R2, R3, R4, and R5 a. The semiconductor device 100a may include first to fifth transistors 10, 20, 30, 40, and 50a disposed in the first to fifth regions R1, R2, R3, R4, and R5a, respectively, and including first to third gate electrode layers GE1, GE2, and GE 3.
The first to fourth transistors 10, 20, 30 and 40 may be the same as the first to fourth transistors 10, 20, 30 and 40 of fig. 2A, respectively. Therefore, it can be understood that, compared to the semiconductor device 100 of fig. 2A, the semiconductor device 100a includes the fifth transistor 50a instead of the fifth transistor 50. According to an embodiment, the semiconductor device 100a may further include the fifth transistor 50 of fig. 2A.
The first to fifth transistors 10, 20, 30, 40 and 50a may be p-type MOSFETs. The first to fifth transistors 10, 20, 30, 40 and 50a may have threshold voltages different from each other and thus may have operating voltages different from each other. The fifth transistor 50a may have a higher threshold voltage and a higher operating voltage than the fourth transistor 40. Accordingly, the threshold voltage and the operating voltage may increase from the first transistor 10 to the fifth transistor 50 a.
The fifth transistor 50a may have the same gate electrode layer GE3 as the fourth transistor 40. Unlike the fourth transistor 40, the fifth transistor 50a may have a second gate dielectric layer 115. Accordingly, the fifth transistor 50a may have a higher threshold voltage and a higher operating voltage than the fourth transistor 40.
Referring to fig. 5, in the semiconductor device 100b, the substrate 101 may have first to fifth regions R1, R2b, R3b, R4, and R5. The semiconductor device 100b may include first to fifth transistors 10, 20b, 30b, 40, and 50 disposed in the first to fifth regions R1, R2b, R3b, R4, and R5, respectively, and including first to fourth gate electrode layers GE1, GE2, GE3, and GE 4.
The first transistor 10, the fourth transistor 40, and the fifth transistor 50 may be the same as the first transistor 10, the fourth transistor 40, and the fifth transistor 50 of fig. 2A, respectively, and the third transistor 30b may be the same as the second transistor 20 of fig. 2A. Therefore, it can be understood that, compared to the semiconductor device 100 of fig. 2A, the semiconductor device 100b includes the second transistor 20b instead of the third transistor 30 of fig. 2A. According to an embodiment, the semiconductor device 100b may further include the fifth transistor 50a of fig. 4.
The first to fifth transistors 10, 20b, 30b, 40 and 50 may be p-type MOSFETs. The first to fifth transistors 10, 20b, 30b, 40 and 50 may have threshold voltages different from each other and thus may have operating voltages different from each other. The first transistor 10 may have the lowest threshold voltage and operating voltage, and the threshold voltage and operating voltage of the second transistor 20b may be higher than those of the first transistor 10. The threshold voltage and the operating voltage of the third transistor 30b may be higher than those of the second transistor 20b, and the threshold voltage and the operating voltage of the fourth transistor 40 may be higher than those of the third transistor 30 b. The threshold voltage and the operating voltage of the fifth transistor 50 may be higher than those of the fourth transistor 40.
The second transistor 20b may have the same gate electrode layer GE1 as the first transistor 10. Unlike the first transistor 10, the second transistor 20b may have a second gate dielectric layer 115. Accordingly, the threshold voltage and the operating voltage of the second transistor 20b may be higher than those of the first transistor 10.
Fig. 6 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment.
Referring to fig. 6, unlike the semiconductor device 100 of fig. 2A, the semiconductor device 100c may not include the gate capping layer 140. Accordingly, the first to fourth gate electrode layers GE1c, GE2c, GE3c, and GE4c in the first to fifth transistors 10c, 20c, 30c, 40c, and 50c may have a relatively larger thickness than the first to fourth gate electrode layers in the semiconductor device 100 of fig. 2A.
The barrier metal layers 134 in the second gate electrode layer GE2c and the third gate electrode layer GE3c may be arranged to be long in the vertical direction at the center portion. The upper metal layer 136 in the fourth gate electrode layer GE4c may be arranged to fill a space between the opposite surfaces of the barrier metal layer 134 at a central portion thereof. Accordingly, in exemplary embodiments, the gate capping layer 140 may be provided at various thicknesses, and may be omitted.
Fig. 7 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment.
Referring to fig. 7, the semiconductor device 100d may include: substrate 101 having sixth through ninth regions R6, R7, R8, and R9, active fin 105, source/drain regions 150, first and second gate dielectric layers 114 and 115, gate spacer layer 116, and fifth and sixth gate electrode layers GE5 and GE 6. The semiconductor device 100d may further include an isolation layer 107, a gate capping layer 140, and an interlayer insulating layer 190.
Semiconductor device 100d may include sixth- ninth transistors 60, 70, 80, and 90 arranged around active fin 105 and fifth gate electrode layer GE5 and sixth gate electrode layer GE6 crossing each other. For example, the sixth to ninth transistors 60, 70, 80 and 90 may all be n-type MOSFETs. The sixth to ninth transistors 60, 70, 80 and 90 may be transistors driven at threshold voltages different from each other. In an exemplary embodiment, the semiconductor devices 100, 100a, 100b, and 100c described above with reference to fig. 1 to 6 may further include the semiconductor device 100d, or may further include at least one of the sixth to ninth transistors 60, 70, 80, and 90 of the semiconductor device 100 d.
Sixth transistor 60 may include second gate dielectric layer 115 and fifth gate electrode layer GE5, and seventh transistor 70 may include first gate dielectric layer 114 and fifth gate electrode layer GE 5. Eighth transistor 80 may include second gate dielectric layer 115 and sixth gate electrode layer GE6, and ninth transistor 90 may include first gate dielectric layer 114 and sixth gate electrode layer GE 6. Fifth gate electrode layer GE5 and sixth gate electrode layer GE6 may have substantially the same width in the channel direction (i.e., in the X direction). The width may be substantially the same as or similar to the first through fourth lengths L1, L2, L3, and L4 of fig. 1. The upper surfaces of fifth gate electrode layer GE5 and sixth gate electrode layer GE6 may be flat and may be located at substantially the same height as each other.
The fifth gate electrode layer GE5 may include a sixth conductive layer 120e, a fifth conductive layer 132, and a barrier metal layer 134. The sixth gate electrode layer GE6 may include a seventh conductive layer 120f, a fifth conductive layer 132, and a barrier metal layer 134. The thicknesses of sixth conductive layer 120e and seventh conductive layer 120f in fifth gate electrode layer GE5 and sixth gate electrode layer GE6 may be different from each other. The thickness of sixth conductive layer 120e in fifth gate electrode layer GE5 may be less than the thickness of seventh conductive layer 120f in sixth gate electrode layer GE 6. The thickness of seventh conductive layer 120f in sixth gate electrode layer GE6 may be less than the thickness of sixth conductive layer 120e in third gate electrode layer GE3 of fig. 2A. Accordingly, the thicknesses of barrier metal layer 134 in fifth gate electrode layer GE5 and sixth gate electrode layer GE6 may be different from each other. In addition, according to an embodiment, the fifth gate electrode layer GE5 may further include an upper metal layer 136 on the barrier metal layer 134 (see fig. 2A).
The sixth to ninth transistors 60, 70, 80 and 90 may have threshold voltages different from each other, and thus may have operating voltages different from each other. The sixth transistor 60 may have the lowest threshold voltage and operation voltage, and the threshold voltage and operation voltage of the seventh transistor 70 may be higher than the threshold voltage and operation voltage of the sixth transistor 60. The threshold voltage and the operating voltage of the eighth transistor 80 may be higher than those of the seventh transistor 70, and the threshold voltage and the operating voltage of the ninth transistor 90 may be higher than those of the eighth transistor 80. The difference in threshold voltage and operating voltage between sixth- ninth transistors 60, 70, 80, and 90 may be due to the structural differences of fifth gate electrode layer GE5 and sixth gate electrode layer GE6, and first gate dielectric layer 114 and second gate dielectric layer 115.
Fig. 8 is a flowchart illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment. Fig. 9A to 9L are diagrams illustrating process operations in a method of manufacturing a semiconductor device according to an exemplary embodiment.
Referring to fig. 8 and 9A, the active fin 105 may be formed by patterning the substrate 101 having the first to fifth regions R1, R2, R3, R4, and R5, and then forming the sacrificial gate structure 180 and the source/drain region 150 on the substrate 101 (S110). In addition, in this operation, the gate spacer layer 116 and the interlayer insulating layer 190 may also be formed.
The first to fifth regions R1, R2, R3, R4, and R5 may be PMOS transistor regions. The substrate 101 may include a conductive region, such as a well structure doped with impurities. The active fin 105 may be defined by forming an isolation layer 107 (see fig. 2B), and may have a shape protruding from the substrate 101. The active fin 105 may include an impurity region, and may include, for example, an n-type impurity region.
Through subsequent processes, a sacrificial gate structure 180 may be formed in a region where the interface layer 112, the first and second gate dielectric layers 114 and 115, and the first to fourth gate electrode layers GE1, GE2, GE3, and GE4 are disposed. Sacrificial gate structure 180 may include a sacrificial gate insulating layer 182, a sacrificial gate electrode layer 185, and a sacrificial gate capping layer 186. The sacrificial gate insulating layer 182 and the sacrificial gate covering layer 186 may be insulating layers, and the sacrificial gate electrode layer 185 may be a conductive layer, but is not limited thereto. For example, the sacrificial gate insulating layer 182 may include silicon oxide, the sacrificial gate electrode layer 185 may include polysilicon, and the sacrificial gate capping layer 186 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.
A gate spacer layer 116 may be formed on both sidewalls of the sacrificial gate structure 180. The gate spacer layer 116 may be made of a low dielectric material and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.
After removing a portion of active fin 105 on both sides of gate spacer layer 116, source/drain regions 150 may be formed on recessed active fin 105. The source/drain regions 150 may be formed using, for example, a Selective Epitaxial Growth (SEG) process. The source/drain regions 150 may include a semiconductor material doped with impurities, such as Si, SiGe, or SiC. Specifically, the source/drain region 150 may include p-type impurities. The impurities may be doped in-situ during the formation of the source/drain regions 150, or the impurities may be implanted separately after growth. The source/drain region 150 may be grown along a crystallization-stable surface during the growth process, and may have, for example, a pentagon, a hexagon, or the like as a cross section in the Y direction, but is not limited thereto.
The interlayer insulating layer 190 may be formed by depositing an insulating material to cover the sacrificial gate structure 180 and the source/drain regions 150, and then exposing the upper surface of the sacrificial gate structure 180 through a planarization process. The interlayer insulating layer 190 may include, for example, at least one of oxide, nitride, and oxynitride, and may include a low dielectric material.
Referring to fig. 8 and 9B, the sacrificial gate structure 180 may be removed, thereby forming an opening OP (S120). The sacrificial gate structure 180 may be removed selectively with respect to the underlying isolation layer 107 and the active fin 105 to form an opening OP that exposes the isolation layer 107, the active fin 105, and the gate spacer layer 116. The removal process of the sacrificial gate structure 180 may be performed using at least one of a dry etching process and a wet etching process.
Referring to fig. 8 and 9C, an interface layer 112 and first and second gate dielectric layers 114 and 115 may be formed in the opening OP (S130). The interface layer 112 and the first and second gate dielectric layers 114 and 115 may be formed to have substantially the same thickness in the first to fifth regions R1, R2, R3, R4, and R5. The interface layer 112 may be formed on the upper surface of the active fin 105 exposed to the lower surface of the opening OP. According to an embodiment, the interfacial layer 112 may be formed by oxidizing a portion of the active fin 105.
The first gate dielectric layer 114 and the second gate dielectric layer 115 may be substantially conformally formed along the sidewalls and the lower surface of the opening OP. The process of forming the first gate dielectric layer 114 and the process of forming the second gate dielectric layer 115 may be separately performed. The first layer may be formed using, for example, an Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD) processA gate dielectric layer 114 and a second gate dielectric layer 115. First gate dielectric layer 114 and second gate dielectric layer 115 may comprise, for example, an oxide, nitride, or high-k material. The second gate dielectric layer 115 may be formed to further include elements not included in the first gate dielectric layer 114. For example, the first gate dielectric layer 114 may include hafnium oxide (HfO)2) And the second gate dielectric layer 115 may include hafnium lanthanum oxide (LaHf)xOy)。
Referring to fig. 8 and 9D, a preliminary first conductive layer 120P and a heat treatment sacrificial layer SL may be formed in the opening OP, and then a heat treatment process may be performed (S140).
The preliminary first conductive layer 120P may be the same material as the first to fourth conductive layers 120a, 120b, 120c and 120d formed in a subsequent process, but is not limited thereto. For example, the preliminary first conductive layer 120P may include TiN, TaN, W, WCN, or a combination thereof. The heat treatment sacrificial layer SL may be, for example, polysilicon. Regrowth of the interface layer 112 is prevented by forming the preliminary first conductive layer 120P and the heat treatment sacrificial layer SL and performing a heat treatment process. The holes in the first gate dielectric layer 114 and the second gate dielectric layer 115 may be removed through a heat treatment process.
Referring to fig. 8 and 9E, the heat-treated sacrificial layer SL may be removed, and then the preliminary first conductive layer 120P may be removed from the second to fourth regions R2, R3, and R4 (S150).
The heat-treatment sacrificial layer SL may be selectively removed with respect to the preliminary first conductive layer 120P by, for example, a wet etching process. After forming separate mask layers on the first and fifth regions R1 and R5, the preliminary first conductive layer 120P may be removed only in the second to fourth regions R2, R3, and R4. Accordingly, the preliminary first conductive layer 120P may remain in the first and fifth regions R1 and R5.
Referring to fig. 8 and 9F, the first layer 122 of the first, second, and fourth conductive layers 120a, 120b, and 120d may be formed in the first to third and fifth regions R1, R2, R3, and R5 (S160).
The first layer 122 may be a layer in which a part of the first conductive layer 120a, the second conductive layer 120b, and the fourth conductive layer 120d is formed by a subsequent process. The first through third layers 122, 124, and 126 may all be the same material, including the second layer 124 and the third layer 126 described below with reference to fig. 9G through 9I. The first to fourth conductive layers 120a, 120b, 120c and 120d may be finally formed of at least one of the first to third layers 122, 124 and 126.
The first layer 122 may be completely formed in the first to fifth regions R1, R2, R3, R4, and R5 and then removed only in the fourth region R4. The first layer 122 in the first and fifth regions R1 and R5 may be conformally formed on the preliminary first conductive layer 120P. The first layer 122 may be the same material as the preliminary first conductive layer 120P. In this case as well, since the preliminary first conductive layer 120P is a layer subjected to heat treatment, the boundary between the first layer 122 and the preliminary first conductive layer 120P can be distinguished due to a difference in crystallinity or the like. The first layer 122 in the second region R2 may be conformally formed on the first gate dielectric layer 114. The first layer 122 in the third region R3 may be conformally formed on the second gate dielectric layer 115.
Referring to fig. 8 and 9G, the second layers 124 of the first to fourth conductive layers 120a, 120b, 120c and 120d may be formed in the first to fifth regions R1, R2, R3, R4 and R5 (S170).
The second layer 124 may be a layer in which a portion of the first to fourth conductive layers 120a, 120b, 120c, and 120d is formed by a subsequent process. The second layer 124 may be entirely formed in the first to fifth regions R1, R2, R3, R4, and R5. The thickness of the second layer 124 may be the same or different than the thickness of the first layer 122, but is not limited to the thickness shown, and may vary in various embodiments.
The second layer 124 in the first, second, third, and fifth regions R1, R2, R3, and R5 may be conformally formed on the first layer 122. The second layer 124 may be the same material as the first layer 122 and may not distinguish the boundaries. The second layer 124 in the fourth region R4 may be conformally formed on the first gate dielectric layer 114.
Referring to fig. 8 and 9H, the first layer 122 and the second layer 124 may be partially removed from the second to fourth regions R2, R3, and R4 (S180).
First, a coating layer CL may be formed on the second layer 124 to fill a lower portion of the opening OP to a predetermined height. The coating CL may include a carbonaceous material, and may be formed of, for example, an Amorphous Carbon Layer (ACL) or a carbon-based spin-on hard mask (C-SOH) layer.
Next, a mask layer ML may be formed on the first and fifth regions R1 and R5, and the first and second layers 122 and 124 on the upper portion of the coating layer CL in the second to fourth regions R2, R3, and R4 may be removed to a first depth D1. The first depth D1 may be in the range of about 20% to 70% of the total depth of the opening OP. The underlying first layer 122 and second layer 124 covered by the coating CL may not be removed. The first layer 122 and the second layer 124 may be removed in the second region R2 and the third region R3, and the second layer 124 may be removed in the fourth region R4. Therefore, a space for gap filling of layers subsequently formed in the second to fourth regions R2, R3, and R4 can be ensured.
The first gate dielectric layer 114 and the second gate dielectric layer 115 may remain without being removed during the removal process of the first layer 122 and the second layer 124, but is not limited thereto. According to an embodiment, in this operation, the first gate dielectric layer 114 and the second gate dielectric layer 115 on the upper portion of the coating layer CL may also be removed together. In this case, as described above with reference to fig. 3B, a structure in which the upper surfaces of the first and second gate dielectric layers 114 and 115 are covered with the second and third conductive layers 120B and 120c by a subsequent process may be formed.
After the removal process of the first layer 122 and the second layer 124, the coating layer CL and the mask layer ML may be removed. The coating layer CL and the mask layer ML may be removed, for example, by an ashing or stripping process.
Referring to fig. 8 and 9I, the third layer 126 of the first to fourth conductive layers 120a, 120b, 120c and 120d may be formed in the first to fifth regions R1, R2, R3, R4 and R5 (S190).
The third layer 126 may be a layer in which a part of the first conductive layers 120a, 120b, 120c, and 120d is formed by a subsequent process. The third layer 126 may be formed on the entire first to fifth regions R1, R2, R3, R4, and R5. The thickness of the third layer 126 may be the same as or different from the thickness of the second layer 124, but is not limited to the illustrated thicknesses, and may vary in various embodiments.
The third layer 126 may be the same material as the second layer 124 and may not distinguish the boundaries. In the first region R1, the third layer 126 may completely fill the space between the opposing surfaces of the second layer 124. For example, in the first region R1, the third layer 126 may completely fill the opening OP. In the second to fourth regions R2, R3, and R4, the third layer 126 may be conformally formed on the first and second gate dielectric layers 114 and 115 and the second layer 124. In the second to fourth regions R2, R3, and R4, the third layer 126 may be formed along the first and second layers 122 and 124 having a relatively low height, and may have a curvature according to the first and second layers 122 and 124. In the fifth region R5, the third layer 126 may be conformally formed on the second layer 124.
By forming the third layer 126, the first to fourth conductive layers 120a, 120b, 120c, and 120d including at least one of the first to third layers 122, 124, and 126 may be formed in the first to fifth regions R1, R2, R3, R4, and R5. The first conductive layer 120a of the first region R1 may include first to third layers 122, 124 and 126, the second conductive layer 120b of the second region R2 and the third region R3 may include the first to third layers 122, 124 and 126, the third conductive layer 120c of the fourth region R4 may include the second layer 124 and the third layer 126, and the fourth conductive layer 120d of the fifth region R5 may include the first to third layers 122, 124 and 126.
Referring to fig. 8 and 9J, a fifth conductive layer 132, a barrier metal layer 134, and an upper metal layer 136 may be sequentially formed on the first to fourth conductive layers 120a, 120b, 120c, and 120d (S200).
The fifth conductive layer 132 may be formed of a material having a work function lower than that of the first to fourth conductive layers 120a, 120b, 120c, and 120 d. For example, the fifth conductive layer 132 may include TiAl, TiAlC, TiAlN, or a combination thereof. The barrier metal layer 134 may be made of a different material from the fifth conductive layer 132, and may include, for example, TiN, TaN, or a combination thereof. The upper metal layer 136 may be made of a different material from the barrier metal layer 134, and may include, for example, W or WCN.
In the first region R1, the fifth conductive layer 132, the barrier metal layer 134, and the upper metal layer 136 may be stacked over the opening OP. In the second to fourth regions R2, R3, and R4, the fifth conductive layer 132 and the barrier metal layer 134 may be formed in the opening OP, and the upper metal layer 136 may be formed over the opening OP. In the fifth region R5, the fifth conductive layer 132, the barrier metal layer 134, and the upper metal layer 136 may be formed in the opening OP.
Referring to fig. 9K, the first to fourth conductive layers 120a, 120b, 120c and 120d, the fifth conductive layer 132, the barrier metal layer 134 and the upper metal layer 136 on the interlayer insulating layer 190 may be removed.
The removal process of the first to fourth conductive layers 120a, 120b, 120c and 120d, the fifth conductive layer 132, the barrier metal layer 134 and the upper metal layer 136 may be performed by a Chemical Mechanical Polishing (CMP) process. If the first gate dielectric layer 114 remains on the interlayer insulating layer 190 in the first and fifth regions R1 and R5, it may be removed together in the process. By this operation, only the first to fourth conductive layers 120a, 120b, 120c and 120d, the fifth conductive layer 132, the barrier metal layer 134 and the upper metal layer 136 in the opening OP may remain.
Referring to fig. 8 and 9L, portions of the first and second gate dielectric layers 114 and 115, the first to fourth conductive layers 120a, 120b, 120c and 120d, the fifth conductive layer 132, the barrier metal layer 134 and the upper metal layer 136 may be removed (S210).
The second depth D2 and the third depth D3 may be removed from the upper surface of the interlayer insulating layer 190 by the first and second gate dielectric layers 114 and 115, the first to fourth conductive layers 120a, 120b, 120c and 120D, the fifth conductive layer 132, the barrier metal layer 134 and the upper metal layer 136. The first to fourth gate electrode layers GE1, GE2, GE3, and GE4 may be finally formed in the first to fifth regions R1, R2, R3, R4, and R5.
The second depth D2 and the third depth D3 may be shallower than the first depth D1 in fig. 9H, but are not limited thereto. The second depth D2 of the first region R1 may be deeper than the third depth D3 of the second to fifth regions R2, R3, R4, and R5. Since only the first conductive layer 120a and the preliminary first conductive layer 120P exist in the opening OP of the first region R1, an etching rate under a specific etching condition may be different from that in the second to fifth regions R2, R3, R4, and R5 having the fifth conductive layer 132 and the barrier metal layer 134. Accordingly, the first conductive layer 120a and the preliminary first conductive layer 120P may be recessed to the second depth D2, which is a relatively deep depth.
Next, referring to fig. 8 and 2A, a gate capping layer 140 filling the opening OP on the first to fourth gate electrode layers GE1, GE2, GE3 and GE4 may be formed (S220). Accordingly, the first to fifth transistors 10, 20, 30, 40 and 50 can be finally formed.
Fig. 10 is a block diagram illustrating an electronic apparatus including a semiconductor device according to an exemplary embodiment.
Referring to fig. 10, an electronic device 1000 according to an embodiment may include a communication unit 1010, an input unit 1020, an output unit 1030, a memory 1040, and a processor 1050.
The communication unit 1010 may include a wired/wireless communication module, and may include a wireless internet module, a short-range communication module, a Global Positioning System (GPS) module, a mobile communication module, and the like. The wired/wireless communication module included in the communication unit 1010 may be connected to an external communication network according to various communication standards to transmit and receive data.
The input unit 1020 may include a mechanical switch, a touch screen, a voice recognition module, and the like, as a module provided by a user to control the operation of the electronic device 1000. Further, the input unit 1020 may include: a mouse operated by a trackball or laser pointer method, or a finger mouse device, and may further include various sensor modules through which a user may input data.
The output unit 1030 may output information processed in the electronic device 1000 in the form of voice or images, and the memory 1040 may store programs or data for processing and controlling the processor 1050. The processor 1050 may transfer instructions to the memory 1040 to write or read data, depending on the desired operation.
The memory 1040 may be embedded in the electronic device 1000 or may communicate with the processor 1050 through a separate interface. When communicating with the processor 1050 over a separate interface, the processor 1050 may write data to or read data from the memory 1040 through various interface standards, such as Secure Digital (SD), Secure Digital High Capacity (SDHC), secure digital extended capacity (SDXC), MICRO SD, Universal Serial Bus (USB), and the like.
The processor 1050 may control the operation of each part included in the electronic device 1000. The processor 1050 may perform control and processing related to voice communication, video communication, data communication, etc., or may also perform control and processing for multimedia reproduction and management. In addition, the processor 1050 may process an input transmitted from a user through the input unit 1020 and may output a result through the output unit 1030. In addition, as described above, the processor 1050 can write data required for controlling the operation of the electronic device 1000 to the memory 1040, or read the data from the memory 1040. At least one of the processor 1050 and the memory 1040 may include a semiconductor device according to various embodiments as described above with reference to fig. 1-7.
Fig. 11 is a schematic diagram illustrating a system including a semiconductor device according to an example embodiment.
Referring to fig. 11, the system 2000 may include a controller 2100, an input/output device 2200, a memory 2300, and an interface 2400. System 2000 may be a mobile system or a system that transmits or receives information. The mobile system may be a Personal Digital Assistant (PDA), a portable computer, a web tablet, a wireless telephone, a mobile telephone, a digital music player, or a memory card.
The controller 2100 may execute a program and may control the system 2000. The controller 2100 may be, for example, a microprocessor, a digital signal processor, a microcontroller, or the like.
Input/output device 2200 may be used to input or output data to system 2000. The system 2000 may be connected to an external device, such as a personal computer or a network, using the input/output device 2200, thereby exchanging data with the external device. The input/output device 2200 may be, for example, a key, a keyboard, or a display.
The memory 2300 may store code and/or data for the operation of the controller 2100 and/or may store data processed in the controller 2100.
The interface 2400 may be a data transmission path between the system 2000 and another external device. The controller 2100, the input/output device 2200, the memory 2300, and the interface 2400 may communicate with each other through a bus 2500.
At least one of the controller 2100 or the memory 2300 may include a semiconductor device according to various embodiments as described above with reference to fig. 1-7.
By way of summary and review, according to embodiments of the present disclosure, semiconductor devices with improved electrical characteristics are provided. That is, for example, the structure of the gate electrode layer of the transistor may be changed in each transistor, thereby providing transistors having the same channel length but different operating voltages.
Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless specifically stated otherwise, as would be apparent to one of ordinary skill in the art at the time of filing the present application. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as set forth in the appended claims.
