阅读说明：本技术 具有掩埋沟道阵列晶体管的极低温半导体器件 (Very low temperature semiconductor device with buried channel array transistors ) 是由 刘敏秀 朴峸慜 于 2019-04-10 设计创作，主要内容包括：一种具有掩埋沟道阵列晶体管的极低温半导体器件包括：隔离区,其对衬底中具有第一P型离子浓度的有源区进行限定；衬底中的栅极结构；以及离子注入区,其在栅极结构下方的有源区中并且具有第二P型离子浓度,其中,栅极结构包括：栅极电介质层,其共形地设置在栅极沟槽的内侧壁上；下栅电极,其设置在栅极电介质层上；以及上栅电极,其设置在下栅电极上,其中,下栅电极具有比上栅电极相对更低的功函数。(An extremely low temperature semiconductor device having a buried channel array transistor comprising: an isolation region defining an active region having a first P-type ion concentration in the substrate; a gate structure in the substrate; and an ion implantation region in the active region under the gate structure and having a second P-type ion concentration, wherein the gate structure includes: a gate dielectric layer conformally disposed on inner sidewalls of the gate trench; a lower gate electrode disposed on the gate dielectric layer; and an upper gate electrode disposed on the lower gate electrode, wherein the lower gate electrode has a relatively lower work function than the upper gate electrode.)

1. An extremely low temperature semiconductor device comprising:

an isolation region defining an active region having a first P-type ion concentration in the substrate;

a gate structure disposed in the substrate; and

an ion implantation region in the active region under the gate structure and having a second P-type ion concentration,

wherein the gate structure comprises:

a gate dielectric layer conformally disposed on inner sidewalls of the gate trench; and

a lower gate electrode disposed on the gate dielectric layer and an upper gate electrode disposed on the lower gate electrode,

wherein the lower gate electrode has a relatively lower work function than the upper gate electrode.

2. The very low temperature semiconductor device of claim 1, wherein the lower gate electrode comprises polysilicon doped with N-type ions.

3. The very low temperature semiconductor device of claim 2, wherein the lower gate electrode is conformally disposed on the gate dielectric layer.

4. The very low temperature semiconductor device of claim 2, further comprising an intermediate gate electrode disposed between the lower gate electrode and the upper gate electrode.

5. The very low temperature semiconductor device of claim 4, wherein the intermediate gate electrode comprises a barrier metal.

6. The very low temperature semiconductor device of claim 4, wherein the middle gate electrode is conformally disposed on the lower gate electrode.

7. The very low temperature semiconductor device of claim 1, wherein the upper gate electrode comprises a metal, metal alloy, or metal compound.

8. The very low temperature semiconductor device of claim 7, wherein the upper gate electrode fills the gate trench and has a rail-like shape.

9. The very low temperature semiconductor device of claim 1, further comprising a blanket gate electrode that covers an upper surface of the upper gate electrode.

10. The very low temperature semiconductor device of claim 9, wherein the blanket gate electrode comprises a lower blanket gate electrode and an upper blanket gate electrode disposed over the lower blanket gate electrode.

11. The very low temperature semiconductor device of claim 10, wherein the lower capped gate electrode comprises a barrier metal and the upper capped gate electrode comprises polysilicon doped with N-type ions.

12. An extremely low temperature semiconductor device comprising:

an isolation region defining an active region in a substrate;

a gate structure disposed in the substrate; and

an ion implantation region in the active region under the gate structure,

wherein the gate structure comprises:

a gate dielectric layer conformally disposed on inner sidewalls of the gate trench; and

a lower gate electrode disposed on the gate dielectric layer, an intermediate gate electrode disposed on the lower gate electrode, and an upper gate electrode disposed on the intermediate gate electrode,

wherein the lower gate electrode has a relatively low work function and the upper gate electrode has a relatively low resistance.

13. The very low temperature semiconductor device of claim 12 wherein the active region has a relatively low concentration of P-type ions and the ion implanted region has a relatively high concentration of P-type ions.

14. The very low temperature semiconductor device of claim 12, wherein the lower gate electrode comprises polysilicon doped with N-type ions.

15. The very low temperature semiconductor device of claim 12 wherein the intermediate gate electrode comprises titanium nitride.

16. The very low temperature semiconductor device of claim 12, wherein the upper gate electrode comprises a metal.

17. The very low temperature semiconductor device of claim 12 wherein the lower gate electrode is conformally disposed to surround the bottom and side surfaces of the middle gate electrode.

18. The very low temperature semiconductor device of claim 17, wherein the middle gate electrode is conformally disposed to surround a bottom surface and side surfaces of the upper gate electrode.

19. The very low temperature semiconductor device of claim 12, further comprising an overlying gate electrode overlying an upper surface of the upper gate electrode,

wherein the upper and lower gate electrodes comprise the same material.

20. The very low temperature semiconductor device of claim 19, further comprising a lower blanket gate electrode disposed between the upper surface of the upper gate electrode and the upper blanket gate electrode,

wherein the lower blanket gate electrode comprises the same material as the middle gate electrode.

Technical Field

The present disclosure generally relates to very low temperature semiconductor devices. More particularly, the present disclosure relates to an extremely low temperature semiconductor device including a buried channel array transistor.

Background

Recently, an extremely low temperature semiconductor device having a buried channel array transistor has been proposed as a next generation semiconductor device. The extremely low temperature semiconductor device has excellent characteristics such as high speed operation, low power consumption, miniaturization of patterns, improvement of integration, increase of data retention time, and extension of refresh period. However, the following problems may occur: such as data corruption due to row hammer phenomena attributable to increased word line access, and such as increased threshold voltages when the device is operating in a very low temperature range.

Disclosure of Invention

Example embodiments of the present disclosure include very low temperature semiconductor devices each including a gate electrode having a plurality of work functions for decreasing a threshold voltage and a buried channel array transistor having an ion implantation region for increasing the threshold voltage, and methods for forming the very low temperature semiconductor devices.

The present disclosure is not limited to the above-described embodiments, and other embodiments not mentioned may be clearly understood by those skilled in the art from the following description.

According to one embodiment of the present disclosure, an extremely low temperature semiconductor device may include: an isolation region defining an active region having a first P-type ion concentration in the substrate; a gate structure disposed in the substrate; and an ion implantation region having a second P-type ion concentration and disposed in the active region under the gate structure. The gate structure may include: a gate dielectric layer conformally disposed on inner sidewalls of the gate trench; a lower gate electrode disposed on the gate dielectric layer; and an upper gate electrode disposed on the lower gate electrode. The lower gate electrode may have a relatively lower work function than the upper gate electrode.

The lower gate electrode may include polysilicon doped with N-type ions.

The lower gate electrode may be conformally disposed on the gate dielectric layer in a liner shape.

The very low temperature semiconductor device may further include an intermediate gate electrode disposed between the lower gate electrode and the upper gate electrode.

The intermediate gate electrode may include a barrier metal.

The middle gate electrode may be conformally disposed on the lower gate electrode in a liner shape.

The upper gate electrode may include a metal, a metal alloy, or a metal compound.

The upper gate electrode may fill the gate trench and have a horizontally extending track shape.

The very low temperature semiconductor device may further include a capping gate electrode covering an upper surface of the upper gate electrode.

The capping gate electrode may include a lower capping gate electrode and an upper capping gate electrode disposed on the lower capping gate electrode.

The lower capping gate electrode may include a barrier metal, and the upper capping gate electrode may include polysilicon doped with N-type ions.

According to one embodiment of the present disclosure, an extremely low temperature semiconductor device may include: an isolation region defining an active region in a substrate; a gate structure disposed in the substrate; and an ion implantation region disposed in the active region under the gate structure. The gate structure may include: a gate dielectric layer conformally disposed on inner sidewalls of the gate trench; a lower gate electrode disposed on the gate dielectric layer; a middle gate electrode disposed on the lower gate electrode; and an upper gate electrode disposed on the middle gate electrode. The lower gate electrode may have a relatively low work function, and the upper gate electrode may have a relatively low resistance.

The active region may have a relatively low concentration of P-type ions, and the ion implantation region may have a relatively high concentration of P-type ions.

The lower gate electrode may include polysilicon doped with N-type ions.

The intermediate gate electrode may comprise titanium nitride.

The upper gate electrode may include a metal.

The lower gate electrode may be conformally disposed to surround the bottom surface and the side surface of the middle gate electrode.

The middle gate electrode may be conformally disposed to surround the bottom surface and the side surface of the upper gate electrode.

The very low temperature semiconductor device may further include an upper capping gate electrode covering an upper surface of the upper gate electrode. The upper capping gate electrode and the lower gate electrode may include the same material.

The very low temperature semiconductor device may further include a lower capping gate electrode disposed between an upper surface of the upper gate electrode and the upper capping gate electrode. The lower cover gate electrode and the intermediate gate electrode may include the same material.

Details of other embodiments are included in the detailed description and the accompanying drawings.

Drawings

Fig. 1A to 1F are sectional views illustrating very low temperature semiconductor devices according to various embodiments of the present invention.

Fig. 2A to 2Q, fig. 3A to 3D, fig. 4A to 4E, fig. 5A to 5E, fig. 6A to 6D, and fig. 7A to 7I are sectional views illustrating a method for forming a semiconductor device.

Fig. 8A is a diagram conceptually illustrating a memory module according to an embodiment, and fig. 8B and 8C are block diagrams conceptually illustrating an electronic system according to an embodiment of the present disclosure.

Detailed Description

Various embodiments will be described in more detail below with reference to the accompanying drawings. However, embodiments of the present disclosure may have different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the claims to those skilled in the art.

Like reference numerals refer to like elements throughout the specification. Thus, although the same or similar reference numbers may not be mentioned or described in the corresponding figures, they may be described with reference to other figures. Further, although elements are not denoted by reference numerals, the elements may be described with reference to other drawings.

Fig. 1A to 1F are sectional views illustrating very low temperature semiconductor devices 100A to 100F according to various embodiments of the present disclosure.

Referring to fig. 1A, a very low temperature semiconductor device 100A according to one embodiment may include an isolation region ISO disposed in a substrate 10 having an active region ACT, a gate structure 70 disposed in the active region ACT of the substrate 10, a lower interlayer dielectric layer 75, an interlayer dielectric layer 89 and a bit line structure 80 disposed on the lower interlayer dielectric layer 75, a storage structure 90, and an upper interlayer dielectric layer 99.

The substrate 10 may include a silicon wafer, an epitaxially grown single crystal silicon layer, a silicon-on-insulator (SOI), or a compound semiconductor layer. For purposes of illustration, the substrate 10 will be described below in a manner consistent with a silicon wafer. The substrate 10 may be doped with P-type ions such as boron (B) at a low concentration.

The isolation region ISO may include a Shallow Trench Isolation (STI) region. For example, the isolation region ISO may include an insulating material filling an isolation trench provided in the substrate 10.

The active region ACT may include a well region corresponding to the body region, and source/drain regions 15 adjacent to a surface thereof. The body region of the active region ACT may include P-type ions, and the source/drain region 15 may include N-type ions.

The gate structure 70 may have a shape or geometry that conforms to a shape or geometry that is buried in the substrate 10 or that extends into the substrate 10. The gate structure 70 may include a gate dielectric layer 20, a lower gate electrode 30, an upper gate electrode 50, and a gate capping layer 65 disposed in a gate trench (e.g., "Tg" as shown in fig. 2C). The ion implantation region 17 may be located below the gate trench Tg in the active region ACT.

The gate dielectric layer 20 may be configured as a layer lining the inner walls of the gate trench Tg. The gate trench Tg may be a cylindrical well or as a trough-like element extending through the substrate in a straight direction. In either example, the gate dielectric layer 20 may have a cup-like cross-sectional shape as shown in fig. 1A, which follows the same cross-sectional shape as the gate trench Tg. The gate dielectric layer 20 may include a silicon oxide layer, or a metal oxide layer having a high dielectric constant, such as a hafnium oxide layer (HfO)_x))。

The lower gate electrode 30 may have a track-like shape or a plug-like shape in the gate trench Tg. The bottom surface and the side surface of the lower gate electrode 30 may be surrounded by the gate dielectric layer 20 or in contact with the gate dielectric layer 20. The upper surface of the lower gate electrode 30 may be located at a relatively lower level than the bottom surface of the source/drain region 15. The lower gate electrode 30 may include a conductor having a relatively low work function. For example, the lower gate electrode 30 may include polysilicon doped with N-type ions such As phosphorus (P) or arsenic (As).

In the very low temperature range, the threshold voltage of the channel region of gate structure 70 is typically greater than the threshold voltage of the same device at room temperature. However, when the threshold voltage rises, the size and effectiveness of the channel are reduced, and it may be difficult to generate the channel. For this reason, the operation speed of the semiconductor device is reduced, and at the same time, the power consumption of the semiconductor device is increased. In one embodiment, the lower gate electrode 30 includes polysilicon doped with N-type ions having a relatively low work function to compensate for an increase in the threshold voltage of the channel region under very low temperature conditions. The lower gate electrode 30 includes polysilicon doped with N-type ions having a lower work function and can be turned on at a lower voltage level. In other words, the threshold voltage can be effectively reduced in the extremely low temperature range as compared with the device having the lower gate electrode 30 (the material of which has a relatively high work function).

The upper gate electrode 50 may have a track-like shape or a plug-like shape on the lower gate electrode 30 in the gate trench Tg. The side surface of the upper gate electrode 50 may be surrounded by the gate dielectric layer 20. The upper surface of the upper gate electrode 50 may be located at a relatively higher level than the bottom surface of the source/drain region 15. The upper gate electrode 50 may include a conductor having a higher work function than the lower gate electrode 30. In some embodiments, the upper gate electrode 50 may include a conductor having a lower resistance than the lower gate electrode 30. For example, the upper gate electrode 50 may include a metal, a metal compound, or a metal alloy. As a non-limiting example, the upper gate electrode 50 may include tungsten (W). In other embodiments, upper gate electrode 50 may comprise a conductor having a higher work function and lower resistance than lower gate electrode 30 and remain capable of forming an ohmic contact. For example, as a non-limiting example, the upper gate electrode 50 may include a barrier metal, such as titanium nitride (TiN).

The lower gate electrode 30 having polysilicon doped with N-type ions has relatively high resistance compared to the upper gate electrode 50. Therefore, the resistance of the gate structure 70 may increase. However, because the gate structure 70 also includes an upper gate electrode 50 that has a relatively low resistance compared to the lower gate electrode 30, any increase in the resistance of the gate structure 70 due to the lower gate electrode 30 may be compensated in whole or in part with the upper gate electrode 50.

A gate capping layer 65 may be disposed on the upper gate electrode 50 to completely fill the gate trench Tg. Portions of the side surfaces of gate capping layer 65 may be surrounded by gate dielectric layer 20. The gate capping layer 65 may include silicon nitride or silicon oxide. In one embodiment, the gate capping layer 65 may include silicon nitride.

The ion implantation region 17 may include P-type ions doped at a higher concentration than that of the well region of the active region ACT. In other words, the active region ACT may have a relatively low P-type ion concentration, and the ion implantation region 17 may have a relatively high P-type ion concentration. The gate structure 70 and the source/drain regions 15 may form a buried channel array transistor structure. In the buried channel array transistor structure, a channel region may be formed in the active region ACT along the contour of the gate dielectric layer 20, i.e., common to the gate dielectric layer 20 or adjacent to the gate dielectric layer 20. The well region of the active region ACT and the ion implantation region 17 may include P-type ions, and the source/drain region 15 may include N-type ions.

The ion implantation region 17 may increase the threshold voltage of the channel region by increasing the P-type ion concentration in the channel region. However, polysilicon doped with N-type ions having a low work function (such as may be used in the lower gate electrode 30) may result in an effect of excessively lowering the threshold voltage. The following materials that can be used in the lower gate electrode 30 have not been fully developed in conjunction with acceptable fabrication processes: the material results in a lower threshold voltage in the very low temperature range without excessively reducing the threshold voltage. Niobium (Nb) or zinc (Zn) may be considered for a material capable of lowering the threshold voltage to a limited extent without impairing the desired functional characteristics. However, such materials may be difficult to obtain or to use as the lower gate electrode because stable fabrication processes have not been developed for these materials, which also results in a higher unit price for the device. Therefore, in the extremely low temperature range, the expected increase in threshold voltage can be solved by the lower gate electrode having a relatively low work function, while the risk of excessively decreasing the threshold voltage can be mitigated by increasing the threshold voltage to a desired size using the ion implantation region 17.

An underlying interlayer dielectric layer 75 may be disposed on the substrate 10, the isolation region ISO, and the gate structure 70. The lower interlayer dielectric layer 75 may include one of a silicon nitride layer, a silicon oxide layer, or a combination thereof. As an example, the lower interlayer dielectric layer 75 may include the same material as the gate capping layer 65.

Bit line structure 80 may include a lower bit line 81, an upper bit line 83, and a bit line capping spacer 85. The lower bit line 81 may be coupled to a central portion of the source/drain regions 15 of the active region ACT in the substrate 10 by vertically penetrating the lower interlayer dielectric layer 75. The lower bit line 81 may have a rail-like, pillar-like, or plug-like geometry. The lower bit line 81 may have an upper portion protruding in an upward direction with respect to an upper surface of the lower interlayer dielectric layer 75. The lower bit line 81 may be a single layer including doped polysilicon, metal silicide, or metal compound, or a multi-layer including any combination thereof. The upper bit line 83 may have a rail-like shape. The upper bit line 83 may include a metal or metal compound coupled to the lower bit line 81. Bit line capping spacers 85 may conformally cap the side and upper surfaces of upper bit lines 83 and the exposed portions of lower bit lines 81 extending from lower inter-layer dielectric layer 75. The bit line capping spacers 85 may include silicon nitride.

An inter-layer dielectric layer 89 may be disposed to surround the exposed side surfaces of the bit line structure 80. An upper surface of inter-level dielectric layer 89 may be substantially coplanar with an upper surface of bit line structure 80.

The storage structure 90 may include a storage contact plug 91, a lower storage electrode 93, and a storage dielectricLayer 95 and upper storage electrode 97. The storage contact plug 91 may be coupled to the source/drain region 15 of the active region ACT of the substrate 10. The storage contact plug 91 may penetrate the interlayer dielectric layer 89 and the lower interlayer dielectric layer 75 to interface with the source/drain region 15. The storage contact plug 91 may have a columnar geometry. The lower storage electrode 93 may have a cylindrical shape. The storage contact plug 91 and the lower storage electrode 93 may include a conductor such as doped polysilicon, a metal silicide, a metal compound, a metal alloy, or any combination thereof. A storage dielectric layer 95 may be conformally disposed on a surface of the lower storage electrode 93 and on upper surfaces of the interlayer dielectric layer 89 and the bit line structure 80. The storage dielectric layer 95 may include silicon oxide, silicon nitride, metal oxide (such as hafnium oxide (HfO))_x) A high-k material, or any combination thereof. The upper storage electrode 97 may be disposed on the storage dielectric layer 95 to fill a region between the lower storage electrodes 93. The upper storage electrode 97 may include doped polysilicon, metal silicide, metal compound, metal alloy, or any combination thereof.

An upper interlayer dielectric layer 99 may be disposed on the storage structure 90 and may be substantially flat or planar. The upper interlayer dielectric layer 99 may include silicon nitride or silicon oxide.

Referring to fig. 1B, a very low temperature semiconductor device 100B according to one embodiment may include an isolation region ISO located in a substrate 10 having an active region ACT, a gate structure 70 buried in the active region ACT of the substrate 10, a lower interlayer dielectric layer 75, an interlayer dielectric layer 89 and a bit line structure 80 disposed on the lower interlayer dielectric layer 75, a storage structure 90, and an upper interlayer dielectric layer 99.

The gate structure 70 may include a gate dielectric layer 20, a lower gate electrode 30, an upper gate electrode 50, an overlying gate electrode 60, and a gate capping layer 65 disposed in a gate trench (e.g., "Tg" as shown in fig. 2C). The ion implantation region 17 may be located below the gate trench Tg of the active region ACT.

The gate dielectric layer 20 may be conformally disposed on the inner sidewalls of the gate trench Tg in a liner shape. The gate dielectric layer 20 may be configured asA layer lining the inner walls of the gate trench Tg. The gate trench Tg may be a cylindrical well or as a trough-like element extending through the substrate in a straight direction. The gate dielectric layer 20 may include a silicon oxide layer, or a metal oxide layer having a high dielectric constant, such as a hafnium oxide layer (HfO)_x))。

The lower gate electrode 30 may have a rail-like or plug-like shape on a portion of the gate dielectric layer 20 in the gate trench Tg, and may be disposed to have an upper surface lower than the bottom surface of the source/drain region 15. The bottom surface and the side surface of the lower gate electrode 30 may be surrounded by the gate dielectric layer 20 or in contact with the gate dielectric layer 20. The lower gate electrode 30 may include a conductor having a relatively low work function. For example, the lower gate electrode 30 may include polysilicon doped with N-type ions.

The upper gate electrode 50 may have a rail-like or plug-like shape on the lower gate electrode 30 in the gate trench Tg, and may be disposed to have an upper surface lower than the bottom surface of the source/drain region 15. The upper gate electrode 50 may include a conductor having a relatively higher work function than the lower gate electrode 30. In addition, the upper gate electrode 50 may include a conductor having a lower resistance than the lower gate electrode 30. For example, the upper gate electrode 50 may include a metal, a metal compound, or a metal alloy. Specifically, as a non-limiting example, the upper gate electrode 50 may include tungsten (W). In some embodiments, the upper gate electrode 50 may comprise a conductor having a relatively higher work function and a relatively lower resistance than the lower gate electrode 30, and remains capable of forming an ohmic contact. For example, as a non-limiting example, the upper gate electrode 50 may include a barrier metal, such as titanium nitride (TiN).

The capping gate electrode 60 may have a track-like or plug-like shape on the upper gate electrode 50 in the gate trench Tg. The cover gate electrode 60 may comprise polysilicon, for example doped with N-type ions. The capping gate electrode 60 may prevent or reduce ion diffusion or ion migration between the upper gate electrode 50 and the gate capping layer 65. The capping gate electrode 60 may also improve adhesion of the upper gate electrode 50 to the gate capping layer 65. For example, when the upper gate electrode 50 includes a metal and the gate capping layer 65 includes silicon oxide, oxygen atoms may migrate from the gate capping layer 65 and diffuse into the upper gate electrode 50, causing the metal to oxidize. Alternatively, metal atoms may migrate from the upper gate electrode 50 and diffuse into the gate capping layer 65, causing an electromigration phenomenon. In addition, when the adhesion between the upper gate electrode 50 and the gate capping layer 65 is poor, layer separation or delamination defect may occur. The inclusion of the blanket gate electrode 60 may prevent or limit the effects of these phenomena.

A gate capping layer 65 may be disposed on the capping gate electrode 60 to fill the gate trench Tg. For the embodiments described herein with reference to fig. 1B, components, features, and configurations of very low temperature semiconductor device 100B that are the same as or similar to components, features, and configurations of very low temperature semiconductor device 100A described above, detailed descriptions thereof may be applicable here and will not be repeated.

In fig. 1B, a cover gate electrode 60 having a relatively low work function is located in a region of the gate trench Tg common to the source/drain region 15 or a region near the source/drain region 15. As a result, Gate Induced Drain Leakage (GIDL) may be mitigated.

Referring to fig. 1C, a very low temperature semiconductor device 100C according to one embodiment may include an isolation region ISO in a substrate 10 having an active region ACT, a gate structure 70 in the active region ACT of the substrate 10, a lower interlayer dielectric layer 75, an interlayer dielectric layer 89 and a bit line structure 80 disposed on the lower interlayer dielectric layer 75, a storage structure 90, and an upper interlayer dielectric layer 99.

The gate structure 70 may include a gate dielectric layer 20, a lower gate electrode 30, an intermediate gate electrode 40, an upper gate electrode 50, and a gate cap layer 65 disposed in a gate trench (e.g., "Tg" as shown in fig. 2C). The ion implantation region 17 may be located below the gate trench Tg of the active region ACT.

The gate dielectric layer 20 may be conformally disposed on the inner sidewalls of the gate trench Tg in a liner shape. The gate dielectric layer 20 may include a silicon oxide layer, or a metal oxide layer having a high dielectric constant, such as a hafnium oxide layer (HfO)_x))。

The lower gate electrode 30 may have a track-like shape or a plug-like shape on a portion of the gate dielectric layer 20 in the gate trench Tg, and may be disposed to have an upper surface lower than the bottom surface of the source/drain region 15. The lower gate electrode 30 may include a conductor having a relatively low work function. For example, the lower gate electrode 30 may include polysilicon doped with N-type ions.

The intermediate gate electrode 40 may have a track-like shape or a plug-like shape on the lower gate electrode 30 in the gate trench Tg, and may be disposed to have an upper surface lower than the bottom surface of the source/drain region 15. The middle gate electrode 40 may include a conductor capable of forming an ohmic contact that prevents a physical and chemical reaction between the lower gate electrode 30 and the upper gate electrode 50. For example, the intermediate gate electrode 40 may include a barrier metal such as titanium nitride (TiN). The work function of the middle gate electrode 40 may be relatively higher than that of the lower gate electrode 30 and relatively lower than that of the upper gate electrode 50. The resistance of the middle gate electrode 40 may be relatively lower than the resistance of the lower gate electrode 30 and relatively higher than the resistance of the upper gate electrode 50.

The upper gate electrode 50 may have a track-like or plug-like shape or geometry on the middle gate electrode 40 in the gate trench Tg. The upper gate electrode 50 may include a conductor having a relatively high work function and a relatively low resistance as compared to both the middle gate electrode 40 and the lower gate electrode 30. For example, the upper gate electrode 50 may include a metal.

A gate capping layer 65 may be disposed on the upper gate electrode 50 to fill the gate trench Tg. The gate cap 65 may comprise a dielectric material that is not physically and chemically reactive with the upper gate electrode 50. For example, the gate capping layer 65 may include silicon nitride. For the embodiments described herein with reference to fig. 1C, components, features, and configurations of very low temperature semiconductor device 100C that are the same as or similar to components, features, and configurations of very low temperature semiconductor device 100A described above, detailed descriptions thereof may be applicable here and will not be repeated.

Referring to fig. 1D, a very low temperature semiconductor device 100D according to an embodiment may include: an isolation region ISO in the substrate 10 having the active region ACT, a gate structure 70 in the active region ACT of the substrate 10, a lower interlayer dielectric layer 75, an interlayer dielectric layer 89 and a bit line structure 80 disposed on the lower interlayer dielectric layer 75, a storage structure 90, and an upper interlayer dielectric layer 99. The gate structure 70 may include a gate dielectric layer 20, a lower gate electrode 31, an upper gate electrode 50, and a gate capping layer 65 disposed in a gate trench (e.g., "Tg" as shown in fig. 2C). The ion implantation region 17 may be located below the gate trench Tg of the active region ACT.

The gate dielectric layer 20 may be conformally disposed on the sidewalls of the gate trench Tg in a liner shape. The gate dielectric layer 20 may include a silicon oxide layer, or a metal oxide layer having a high dielectric constant, such as a hafnium oxide layer (HfO)_x))。

The lower gate electrode 31 may be conformally disposed on at least a portion of the gate dielectric layer 20 in the gate trench Tg. As an example, as shown in fig. 1D, both the gate dielectric layer 20 and the lower gate electrode 31 may have a cup-like or bowl-like cross-sectional shape. The lower gate electrode 31 may include a conductor having a relatively low work function. For example, the lower gate electrode 31 may include polysilicon doped with N-type ions.

The upper gate electrode 50 may have a track-like or plug-like shape on the lower gate electrode 31 in the gate trench Tg. The upper gate electrode 50 may include a conductor having a relatively high work function and a relatively low resistance. For example, the upper gate electrode 50 may include a metal. In some embodiments, the upper gate electrode 50 may include a conductor having a lower resistance than the lower gate electrode 31. For example, the upper gate electrode 50 may include a metal, a metal compound, or a metal alloy. Specifically, as a non-limiting example, the upper gate electrode 50 may include tungsten (W). In other embodiments, the upper gate electrode 50 may include a conductor having a higher work function and lower resistance than the lower gate electrode 31, and remains capable of forming an ohmic contact. For example, as a non-limiting example, the upper gate electrode 50 may include a barrier metal, such as titanium nitride (TiN).

A gate capping layer 65 may be disposed on the upper gate electrode 50 to fill the gate trench Tg. The gate cap 65 may comprise a dielectric material that is not physically and chemically reactive with the upper gate electrode 50. For example, the gate capping layer 65 may include silicon nitride. When the upper gate electrode 50 includes a blocking metal, the gate capping layer 65 may include silicon oxide.

The upper surfaces of the lower gate electrode 31 and the upper gate electrode 50 may be located at a relatively higher level than the bottom or lowest portion of the source/drain region 15. The channel region of the gate structure 70 extends in the substrate 10 in a region spaced apart from the lower gate electrode 31 by the gate dielectric layer 20. For the embodiments described herein with reference to fig. 1D, components, features, and configurations of very low temperature semiconductor device 100D that are the same as or similar to components, features, and configurations of very low temperature semiconductor device 100A described above, detailed descriptions thereof may be applicable here and will not be repeated.

In fig. 1D, the lower gate electrode 31 having a relatively low work function is located in a region of the gate trench Tg common to the source/drain regions 15 or a region near the source/drain regions 15, and thus Gate Induced Drain Leakage (GIDL) may be reduced or prevented.

Referring to fig. 1E, an extremely low temperature semiconductor device 100E according to an embodiment may include: an isolation region ISO in the substrate 10 having the active region ACT, a gate structure 70 disposed in the active region ACT of the substrate 10, a lower interlayer dielectric layer 75, an interlayer dielectric layer 89 and a bit line structure 80 disposed on the lower interlayer dielectric layer 75, a storage structure 90, and an upper interlayer dielectric layer 99. The gate structure 70 may include a gate dielectric layer 20, a lower gate electrode 31, an upper gate electrode 50, an overlying gate electrode 60, and a gate capping layer 65 disposed in a gate trench (e.g., "Tg" as shown in fig. 2C).

The lower gate electrode 31 may include a conductor having a relatively low work function. For example, the lower gate electrode 31 may include polysilicon doped with N-type ions.

The upper gate electrode 50 may include a conductor having a relatively high work function and a relatively low resistance. For example, the upper gate electrode 50 may include a metal. The upper gate electrode 50 may include a conductor capable of forming an ohmic contact with the lower gate electrode 31. For example, the upper gate electrode 50 may include a barrier metal such as titanium nitride (TiN). The upper gate electrode 50 may have a higher work function and a lower resistance than the lower gate electrode 31.

The blanket gate electrode 60 may comprise polysilicon doped with N-type ions. The capping gate electrode 60 may prevent or mitigate ion diffusion or migration between the upper gate electrode 50 and the gate capping layer 65. The capping gate electrode 60 may also improve adhesion of the upper gate electrode 50 to the gate capping layer 65. A detailed description of the blanket gate electrode 60 is provided above with reference to fig. 1B.

In fig. 1E, a cover gate electrode 60 having a relatively low work function is located in a region of the gate trench Tg common to the source/drain regions 15 or a region near the source/drain regions 15, so that Gate Induced Drain Leakage (GIDL) may be reduced or prevented. For the embodiments described herein with reference to fig. 1E, components, features, and configurations of very low temperature semiconductor device 100E that are the same as or similar to the components, features, and configurations of very low temperature semiconductor device 100A described above, detailed descriptions thereof may be applicable here and will not be repeated.

Referring to fig. 1F, a very low temperature semiconductor device 100F according to one embodiment may include an isolation region ISO in a substrate 10 having an active region ACT, a gate structure 70 in the active region ACT of the substrate 10, a lower interlayer dielectric layer 75, an interlayer dielectric layer 89 and a bit line structure 80 disposed on the lower interlayer dielectric layer 75, a storage structure 90, and an upper interlayer dielectric layer 99. The gate structure 70 may include a gate dielectric layer 20, a lower gate electrode 31, an intermediate gate electrode 41, an upper gate electrode 50, a lower capping gate electrode 42, an upper capping gate electrode 32, and a gate capping layer 65 located in a gate trench (see "Tg" shown in fig. 2C).

The gate dielectric layer 20 may be conformally disposed on the sidewalls of the gate trench Tg. The gate dielectric layer 20 may include a silicon oxide layer, or a metal oxide layer having a high dielectric constant, such as a hafnium oxide layer (HfO)_x))。

The lower gate electrode 31 may be conformally disposed on at least a portion of the gate dielectric layer 20 in the gate trench Tg. The lower gate electrode 31 may include a conductor having a relatively low work function. For example, the lower gate electrode 31 may include polysilicon doped with N-type ions. The middle gate electrode 41 may be conformally disposed on at least a portion of the lower gate electrode 31. The middle gate electrode 41 may include a conductor capable of forming an ohmic contact that prevents a physical and chemical reaction between the lower gate electrode 31 and the upper gate electrode 50. For example, the intermediate gate electrode 41 may include a barrier metal such as titanium nitride (TiN). The work function of the middle gate electrode 41 may be relatively higher than that of the lower gate electrode 31 and relatively lower than that of the upper gate electrode 50. The resistance of the middle gate electrode 41 may be relatively lower than the resistance of the lower gate electrode 31 and relatively higher than the resistance of the upper gate electrode 50.

The upper gate electrode 50 may have a rail-like or plug-like shape on the middle gate electrode 41. The upper gate electrode 50 may include a conductor having a relatively high work function and a relatively low resistance. For example, the upper gate electrode 50 may include a metal. In addition, the upper gate electrode 50 may include a conductor having a relatively lower resistance than the lower gate electrode 31 and the middle gate electrode 41. For example, the upper gate electrode 50 may include a metal, a metal compound, or a metal alloy. Specifically, as a non-limiting example, the upper gate electrode 50 may include tungsten (W).

The lower coverage gate electrode 42 may have a rail-like or plate-like shape on the upper gate electrode 50 to cover the upper surface of the upper gate electrode 50. The lower capping gate electrode 42 may include the same material as that included in the middle gate electrode 41. The lower cover gate electrode 42 and the intermediate gate electrode 41 may be coupled to each other. Thus, the upper gate electrode 50 may be surrounded or encapsulated by the middle gate electrode 41 and the lower overlying gate electrode 42.

The upper capping gate electrode 32 may have a rail-like or plate-like shape on the lower capping gate electrode 42. The upper capping gate electrode 32 may include the same material as that used in the lower gate electrode 31. The upper capping gate electrode 32 may be coupled to the lower gate electrode 31. Accordingly, the coupling structure of the middle gate electrode 41 and the lower cover gate electrode 42 may be surrounded by the lower gate electrode 31 and the upper cover gate electrode 32.

According to various embodiments disclosed herein, very low temperature semiconductor devices 100A to 100F may include: a gate structure 70 having an effect of reducing a threshold voltage of the buried gate channel array transistor; and an ion implantation region 17 having an effect of increasing the same threshold voltage. Therefore, the extremely low temperature semiconductor devices 100A to 100F may have threshold voltages appropriately adjusted to have good operation performance in an extremely low temperature range, as compared with other devices.

According to embodiments disclosed herein, the lower gate electrodes 30 and 31 having a relatively low work function may be located near or near the channel region. When a material having a low work function is located near the channel region, the threshold voltage may be maximized by using a material in the lower gate electrode. When a material having a high work function is located near the channel region, the threshold voltage cannot be sufficiently lowered.

According to various embodiments, Gate Induced Drain Leakage (GIDL) may be mitigated when the upper capping gate electrode 32 and the lower gate electrode 31 having a relatively low work function are located near the source/drain regions 15.

Fig. 2A to 2Q are sectional views illustrating a method for forming or manufacturing a semiconductor device.

Referring to fig. 2A, the method may include: an isolation region ISO is formed that defines the active region ACT in the substrate 10. The substrate 10 may include a single crystal silicon layer lightly doped with P-type ions such as boron (B). Forming the isolation region ISO may include performing a Shallow Trench Isolation (STI) process.

Referring to fig. 2B, the method may include: a buffer layer 11 is formed on a surface of the substrate 10, and source/drain regions 15 are formed in an active region ACT of the substrate 10 by an ion implantation process. The step of forming the buffer layer 11 may include thinly oxidizing the surface of the substrate 10 or thinly depositing silicon oxide on the surface of the substrate 10. The step of forming the source/drain regions 15 may include performing an ion implantation process to implant N-type ions, such As phosphorus (P) or arsenic (As), in the active region ACT of the substrate 10. Subsequently, the buffer layer 11 may be removed.

Referring to fig. 2C, the method may include forming a first mask pattern M1 on a surface of the substrate 10 and a surface of the isolation region ISO through a photolithography process, and forming a gate trench Tg through an etching process using the first mask pattern M1 as an etching mask. Although not shown in the sectional views of fig. 2A to 2Q, the gate trench Tg may be formed as a cylindrical well, or as a groove-like element extending through the substrate 10 in a straight direction, and may have the same sectional configuration in either case. The first mask pattern M1 may include one of photoresist, silicon oxide, silicon nitride, a spin-on hard mask (SOH), or a combination thereof.

Referring to fig. 2D, the method may include: the ion implantation region 17 is formed by an ion implantation process of implanting boron (B) in the active region ACT of the substrate 10, particularly at the bottom of the exposed gate trench Tg. The step of forming the ion implantation region 17 may include implanting boron fluoride ions (BF) into the active region ACT by a local channel ion implantation method₃ ⁺And BF₂ ²⁺). The local channel ion implantation method may include: boron fluoride ions are implanted into the active region ACT of the substrate 10 at an acceleration energy of about 20 to 30KeV to an ion concentration of about 1E12(1 x 10)¹²) To 1E13 (1X 10)¹³) Ion/cm². The ion implantation energy and the ion implantation concentration of the boron fluoride ions for increasing the threshold voltage of the channel may be adjusted and changed in various ways according to the operating conditions and the operating characteristics of the channel. Subsequently, the first mask pattern M1 may be removed.

Thereafter, a cleaning process for curing the surface of the substrate 10 exposed in the gate trench Tg may be performed. The cleaning process may include extremely thin stripping of the surface of the substrate 10 exposed in the gate trench Tg. In some embodiments, the ion implantation region 17 may have a pocket or bowl shape surrounding the bottom of the gate trench Tg. In other words, the ion implantation region 17 may be formed not only on the bottom surface of the gate trench Tg but also partially on the sidewall of the gate trench Tg. However, the ion implantation region 17 may be spaced apart from the source/drain region 15.

Referring to fig. 2E, the method may include conformally forming a gate dielectric layer 20 on the inner sidewalls and bottom surface of the gate trench Tg. The step of forming the gate dielectric layer 20 may include a silicon oxidation process. That is, the surface of the substrate 10 exposed in the gate trench Tg may be oxidized. In some embodiments, the method may include disposing, for example, hafnium oxide (HfO) on the substrate 10 exposed in the gate trench Tg by a deposition process_x) A high-k dielectric layer of layers to form gate dielectric layer 20. Silicon oxidation processA thermal oxidation process may be included. Therefore, since diffusion can be performed simultaneously in the silicon oxidation process, it may not be necessary to diffuse boron fluoride ions (BF) in the active region ACT₃ ⁺And BF₂ ²⁺) A separate heat treatment process (e.g., an annealing process). That is, the heat treatment process may only need to be performed once. Since it is desirable to perform the heat treatment process as little as possible, the characteristic deterioration of the extremely low temperature semiconductor device attributable to the frequent heat treatment process can be reduced or reduced.

Referring to fig. 2F, the method may include forming a lower gate electrode material layer 30a on the gate dielectric layer 20 inside the gate trench Tg and on the surface of the substrate 10 through a deposition process. The lower gate electrode material layer 30a may include a conductor having a relatively low work function. For example, the lower gate electrode material layer 30a may include polysilicon doped with N-type ions. Thus, the deposition process may include an N-type doping process and an N-type deposition process for depositing doped silicon. Since the N-type ions may be supplied in a gaseous form during the deposition process, it may not be necessary to perform a separate N-type doping process.

Referring to fig. 2G, the method may include forming the lower gate electrode 30 by removing an upper portion of the lower gate electrode material layer 30a through an etch-back process. Since the upper portion of the lower gate electrode material layer 30a is removed, the upper surface of the lower gate electrode 30 may be located at a half or less of the depth of the gate trench Tg. For example, the upper surface of the lower gate electrode 30 may be located at a lower level than the bottom of the source/drain region 15.

Referring to fig. 2H, the method may include forming an upper gate electrode material layer 50a in the gate trench Tg and on the surface of the substrate 10 through a deposition process. The upper gate electrode material layer 50a may include a conductor having a relatively higher work function than the lower gate electrode 30.

The upper gate electrode material layer 50a may include a material capable of forming an ohmic contact with the lower gate electrode 30. For example, the upper gate electrode material layer 50a may include a barrier metal. As an example, the upper gate electrode material layer 50a may include titanium nitride (TiN).

In some embodiments of the present disclosure, the upper gate electrode material layer 50a may include a material having a higher work function than the lower gate electrode 30, the work function being high enough to change the threshold voltage of the device at low or very low temperatures. For example, the upper gate electrode material layer 50a may include a metal, a metal compound, or a metal alloy. For example, the upper gate electrode material layer 50a may include tungsten (W).

Referring to fig. 2I, the method may include forming the upper gate electrode 50 by removing an upper portion of the upper gate electrode material layer 50a through an etch-back process. An upper portion of the upper gate electrode material layer 50a is removed so that an upper surface of the upper gate electrode 50 may be located in the gate trench Tg. The upper surface of the upper gate electrode 50 may be located at a higher level than the bottom surface of the source/drain region 15.

Referring to fig. 2J, the method may include: the gate structure 70 is formed by forming a dielectric gate capping layer 65 to fill the gate trench Tg through a deposition process, and an underlying interlayer dielectric layer 75 is formed to be stacked on the upper surface of the substrate 10. The gate structure 70 may include a gate dielectric layer 20, a lower gate electrode 30, an upper gate electrode 50, and a gate capping layer 65. For example, the gate capping layer 65 may include silicon nitride, and the lower interlayer dielectric layer 75 may include silicon oxide. In some embodiments of the present disclosure, the gate capping layer 65 and the lower interlayer dielectric layer 75 may be the same material. For example, the gate capping layer 65 and the lower interlayer dielectric layer 75 may be silicon nitride or silicon oxide. When the gate capping layer 65 and the lower interlayer dielectric layer 75 are the same material, the gate capping layer 65 and the lower interlayer dielectric layer 75 may be continuously formed during a single process. When the gate capping layer 65 and the lower inter-layer dielectric layer 75 are the same material, a Chemical Mechanical Polishing (CMP) process may be performed to planarize an upper surface of the lower inter-layer dielectric layer 75. During the CMP process, a gate structure 70 including a gate dielectric layer 20, a lower gate electrode 30, an upper gate electrode 50, and a gate capping layer 65 may be formed.

Referring to fig. 2K, the method may include: a second mask pattern M2 is formed on the lower interlayer dielectric layer 75 through a photolithography process, and a bit line trench Tb is formed through an etching process using the second mask pattern M2 as an etching mask. The bit line trench Tb may expose the source/drain regions 15 in the active region ACT. Subsequently, the second mask pattern M2 may be removed. In some embodiments of the present disclosure, the bit line trench Tb may have a hole-like or well-like shape. That is, the bit line trench Tb may have a hole-like or well-like shape instead of a trench-like shape. In this case, the bit line trench Tb may be referred to as a bit line contact hole.

Referring to fig. 2L, the method may include: a conductive lower line material layer 81a is formed in the bit line trench Tb and on the lower interlayer dielectric layer 75 through a deposition process, and a conductive upper line material layer 83a is formed on the lower bit line material layer 81 a. The lower bit line material layer 81a may be a single layer including doped polysilicon, metal silicide, or metal compound, or it may be a multi-layer including any combination of the above materials. The upper bitline material layer 83a may include a metal or a metal compound.

Referring to fig. 2M, the method may include forming the lower bit line 81 and the upper bit line 83 by successively patterning the upper line material layer 83a and the lower line material layer 81a through an etching process. The lower bit line 81 may have a line shape extending horizontally in a one-dimensional manner, or a plug-like or pillar-like shape. The upper bit line 83 may have a line shape extending horizontally in a one-dimensional manner.

Referring to fig. 2N, the method may include: the bit line stack 80 is formed by providing a bit line cover spacer 85 surrounding the exposed surface of the lower bit line 81 and the exposed surface of the upper bit line 83. The method may include forming an inter-level dielectric layer 89, the inter-level dielectric layer 89 being formed on the lower inter-level dielectric layer 75 and on a side surface of the bit line stack 80. The step of forming the bit line capping spacers 85 may include conformally forming a dielectric layer, such as a silicon nitride layer, on the exposed surfaces of the lower bit lines 81, the exposed surfaces of the upper bit lines 83, and the exposed surfaces of the lower interlayer dielectric layer 75, and performing an etch-back process. The step of forming inter-layer dielectric layer 89 may include depositing silicon oxide on bit line stack 80 and lower inter-layer dielectric layer 75, and then performing a CMP process. The upper surface of the bit line capping spacer 85 may be substantially coplanar with the upper surface of the inter-level dielectric layer 89.

Referring to fig. 2O, the method may include forming a third mask pattern M3 on the inter-layer dielectric layer 89 through a photolithography process. The mask pattern M3 may protect, for example, the bit line stack 80. The method can comprise the following steps: a storage contact hole H exposing the source/drain regions 15 of the active region ACT is formed by vertically penetrating the interlayer dielectric layer 89 through an etching process using the third mask pattern M3 as an etching mask. Subsequently, the third mask pattern M3 may be removed.

Referring to fig. 2P, the method may include: a storage contact plug 91 is formed to fill the storage contact hole H, and a lower storage electrode 93 is formed on the storage contact plug 91. The storage contact plug 91 may have a cylindrical shape, and the lower storage electrode 93 may have a cylindrical shape. The storage contact plug 91 and the lower storage electrode 93 may include a conductive material. For example, the storage contact plug 91 and the lower storage electrode 93 may include doped polysilicon, metal silicide, metal compound, metal alloy, or any combination thereof.

Referring to fig. 2Q, the method may include conformally forming a storage dielectric layer 95 on an exposed surface of the lower storage electrode 93 through a deposition process. The method may include forming the storage structure 90 by forming an upper storage electrode 97 on the storage dielectric layer 95. The storage dielectric layer 95 may include silicon oxide, silicon nitride, such as hafnium oxide (HfO)_x) Or a high-k material, or any combination thereof. The upper storage electrode 97 may include doped polysilicon, metal silicide, metal compound, metal alloy, or any combination thereof.

Subsequently, referring back to fig. 1A, the method may include forming an upper interlayer dielectric layer 99 on the storage structure 90 through a deposition process. The upper interlayer dielectric layer 99 may include a dielectric material such as silicon nitride or silicon oxide.

Fig. 3A to 3D are sectional views illustrating a method for forming an extremely low temperature semiconductor device.

Referring to fig. 3A, the method may include: through the series of processes described above and with reference to fig. 2A to 2I, the isolation region ISO defining the active region ACT in the substrate 10 is formed, the source/drain regions 15 are formed, the gate trench Tg is formed, the ion implantation region 17 is formed in the gate trench Tg, the gate dielectric layer 20 is formed in the gate trench Tg, the lower gate electrode 30 is formed on the gate dielectric layer 20, and the upper gate electrode 50 is formed on the lower gate electrode 30. The upper surface of the upper gate electrode 50 may be located at a lower level than the bottom surface of the source/drain region 15.

Referring to fig. 3B, the method may include forming a cover gate electrode material layer 60a on the upper gate electrode 50 in the gate trench Tg and on the surface of the substrate 10. The capping gate electrode material layer 60a may include a conductor having a relatively lower work function than the upper gate electrode 50. For example, the capping gate electrode material layer 60a may include the same material as the lower gate electrode 30. Specifically, the capping gate electrode material layer 60a may include polysilicon doped with N-type ions.

Referring to fig. 3C, the method may include forming the cover gate electrode 60 by removing an upper portion of the cover gate electrode material layer 60a through an etch-back process. An upper surface of the cover gate electrode 60 may be located in the gate trench Tg. For example, the upper surface of the cover gate electrode 60 may be located at a higher level than the bottom or lowest portion of the source/drain region 15.

Referring to fig. 3D, the method may include: the gate structure 70 is formed by forming a dielectric gate capping layer 65 to fill the gate trench Tg through a deposition process, and an underlying interlayer dielectric layer 75 is formed to be stacked on the upper surface of the substrate 10. The gate structure 70 may include a gate dielectric layer 20, a lower gate electrode 30, an upper gate electrode 50, an overlying gate electrode 60, and a gate capping layer 65.

Subsequently, the method may comprise: through a series of processes described above and with reference to fig. 2K-2Q, bit line stack 80 is formed, inter-level dielectric layer 89 is formed, and storage structure 90 is formed. Referring again to fig. 1B, the method may further include forming an upper interlayer dielectric layer 99 on the storage structure 90.

Fig. 4A to 4E are sectional views illustrating a method for forming a semiconductor device.

Referring to fig. 4A, the method may include: through a series of processes described above with reference to fig. 2A to 2G, isolation regions ISO defining active regions ACT in the substrate 10 are formed, source/drain regions 15 are formed, gate trenches Tg are formed, ion implantation regions 17 are formed in the active regions ACT exposed at the bottoms of the gate trenches Tg, a gate dielectric layer 20 is formed in the gate trenches Tg, a lower gate 30 is formed on the gate dielectric layer 20, and an intermediate gate electrode material layer 40a is formed on the lower gate electrode 30 in the gate trenches Tg. An intermediate gate electrode material layer 40a may also be formed on the surface of the substrate 10. The intermediate gate electrode material layer 40a may include a conductor having a relatively higher work function than the lower gate electrode 30. The intermediate gate electrode material layer 40a may include a conductor capable of forming an ohmic contact with the lower gate electrode 30. For example, the intermediate gate electrode material layer 40a may include a barrier metal. Specifically, as an example, the intermediate gate electrode material layer 40a may include titanium nitride (TiN).

Referring to fig. 4B, the method may include forming the intermediate gate electrode 40 by removing an upper portion of the intermediate gate electrode material layer 40a through an etch-back process. The intermediate gate electrode 40 may be located approximately in the middle of the gate trench Tg. The upper surface of the intermediate gate electrode 40 may be located at a lower level than the bottom or lowermost region of the source/drain region 15.

Referring to fig. 4C, the method may include forming an upper gate electrode material layer 50a on the surface of the substrate 10 and forming an upper gate electrode material layer 50a on the intermediate gate electrode 40 to fill the gate trench Tg. The upper gate electrode material layer 50a may include a conductor having a relatively higher work function than the middle gate electrode 40. For example, the upper gate electrode material layer 50a may include: a metal, a metal compound or a metal alloy. Specifically, as an example, the upper gate electrode material layer 50a may include tungsten (W).

Referring to fig. 4D, the method may include forming the upper gate electrode 50 by removing an upper portion of the upper gate electrode material layer 50a through an etch-back process. The upper gate electrode 50 may be located in the gate trench Tg. The upper surface of the upper gate electrode 50 may be located at a higher level than the bottom surface of the source/drain region 15 or above the bottom surface of the source/drain region 15.

Referring to fig. 4E, the method may include: the gate structure 70 is formed by forming a dielectric gate capping layer 65 to fill the gate trench Tg through a deposition process, and an underlying interlayer dielectric layer 75 is formed to be stacked or formed on the upper surface of the substrate 10. The gate structure 70 may include a gate dielectric layer 20, a lower gate electrode 30, an intermediate gate electrode 40, an upper gate electrode 50, and a gate capping layer 65.

Subsequently, the method may comprise: through a series of processes described above and with reference to fig. 2K-2Q, bit line stack 80 is formed, inter-level dielectric layer 89 is formed, and storage structure 90 is formed. Referring again to fig. 1C, the method may further include forming an upper interlayer dielectric layer 99 on the storage structure 90.

Fig. 5A to 5E are sectional views illustrating a method for forming an extremely low temperature semiconductor device.

Referring to fig. 5A, the method may include: through the series of processes described above and with reference to fig. 2A to 2E, the isolation region ISO defining the active region ACT in the substrate 10 is formed, the source/drain regions 15 are formed, the gate trench Tg is formed, the ion implantation region 17 is formed in the gate trench Tg, the gate dielectric layer 20 is formed in the gate trench Tg, and the lower gate electrode material layer 31a is formed on the gate dielectric layer 20 in the gate trench Tg. The lower gate electrode material layer 31a may also be formed on the upper surface of the substrate 10. The lower gate electrode material layer 31a may include a conductor having a relatively low work function. For example, the lower gate electrode material layer 31a may include polysilicon doped with N-type ions.

Referring to fig. 5B, the method may include forming an upper gate electrode material layer 50a on the lower gate electrode material layer 31a and filling the gate trench Tg. The upper gate electrode material layer 50a may include a conductor having a relatively higher work function than the lower gate electrode material layer 31 a. For example, the upper gate electrode material layer 50a may include a conductor capable of forming an ohmic contact with the lower gate electrode material layer 31 a. For example, the upper gate electrode material layer 50a may include a barrier metal. Specifically, as an example, the upper gate electrode material layer 50a may include titanium nitride (TiN).

In some embodiments, the upper gate electrode material layer 50a may comprise a material having a higher work function than the lower gate electrode material layer 31a, the work function being high enough to change the threshold voltage of the device at low or very low temperatures. The upper gate electrode material layer 50a may include a metal, a metal compound, or a metal alloy. For example, the upper gate electrode material layer 50a may include tungsten (W).

Referring to fig. 5C, the method may include: the upper gate electrode 50 is formed in the gate trench Tg by removing an upper portion of the upper gate electrode material layer 50a through an etch-back process. An upper portion of the upper gate electrode material layer 50a is removed so that an upper surface of the upper gate electrode 50 may be located in the gate trench Tg. The upper surface of the upper gate electrode 50 may be located at a higher level than the bottom surface or lowermost region of the source/drain region 15 or above the bottom surface or lowermost region of the source/drain region 15.

Referring to fig. 5D, the method may include: the lower gate electrode 31 is formed in the gate trench Tg by removing a portion of the lower gate electrode material layer 31a through an etch-back process. The lower gate electrode 31 may have a cross section of a cup shape in common with the bottom surface and the side surface of the upper gate electrode 50. The upper surface of the lower gate electrode 31 and the upper surface of the upper gate electrode 50 may be located at substantially similar levels.

Referring to fig. 5E, the method may include: the gate structure 70 is formed by forming a dielectric gate capping layer 65 to fill the gate trench Tg through a deposition process, and an underlying interlayer dielectric layer 75 is formed to be stacked on the upper surface of the substrate 10. The gate structure 70 may include a gate dielectric layer 20, a cup-shaped lower gate electrode 31, an upper gate electrode 50, and a gate capping layer 65.

Subsequently, the method may comprise: through a series of processes described above and with reference to fig. 2K-2Q, bit line stack 80 is formed, inter-level dielectric layer 89 is formed, and storage structure 90 is formed. Referring again to fig. 1D, the method may further include forming an upper interlayer dielectric layer 99 on the storage structure 90.

Fig. 6A to 6D are sectional views illustrating a method for forming an extremely low temperature semiconductor device according to an embodiment.

Referring to fig. 6A, the method may include: through the series of processes described above with reference to fig. 2A to 2E and 5A to 5C, the isolation region ISO defining the active region ACT in the substrate 10 is formed, the source/drain regions 15 are formed, the gate trench Tg is formed, the ion implantation region 17 is formed, the gate dielectric layer 20 is formed, the lower gate electrode material layer 31a is conformally formed, the upper gate electrode material layer 50a is formed, and the upper gate electrode 50 is formed in the gate trench Tg by removing an upper portion of the upper gate electrode material layer 50a through an etch-back process. However, unlike the method shown in fig. 5C, the upper surface of the upper gate electrode 50 in fig. 6A may be located at a lower level than the bottom surface of the source/drain region 15 or below the bottom surface of the source/drain region 15.

The lower gate electrode material layer 31a may include a conductor having a relatively low work function. For example, the lower gate electrode material layer 31a may include polysilicon doped with N-type ions. The upper gate electrode 50 may include a conductor having a relatively higher work function than the lower gate electrode material layer 31 a. For example, the upper gate electrode 50 may include a conductor capable of forming an ohmic contact with the lower gate electrode material layer 31 a. For example, the upper gate electrode 50 may include a barrier metal. Specifically, as an example, the upper gate electrode 50 may include titanium nitride (TiN). In some embodiments, the upper gate electrode 50 may comprise a material having a work function sufficiently high compared to the lower gate electrode material layer 31a, the work function being sufficiently high to change the threshold voltage of the device at low or very low temperatures. The upper gate electrode 50 may include a metal, a metal compound, or a metal alloy. Specifically, as an example, the upper gate electrode 50 may include tungsten (W).

Referring to fig. 6B, the method may include: a cover gate electrode material layer 60a is formed on the upper gate electrode 50 and the lower gate electrode material layer 31a, and the gate trench Tg is filled. The capping gate electrode material layer 60a may include a conductor having a relatively lower work function than the upper gate electrode 50. For example, the capping gate electrode material layer 60a may include the same material as the lower gate electrode material layer 31 a. Specifically, the capping gate electrode material layer 60a may include polysilicon doped with N-type ions. When the lower gate electrode material layer 31a and the cover gate electrode material layer 60a include the same material, an interface between the lower gate electrode material layer 31a and the cover gate electrode material layer 60a is represented by a dotted line in fig. 6B.

Referring to fig. 6C, the method may include: the cover gate electrode 60 and the lower gate electrode 31 are formed in the gate trench Tg by removing an upper portion of the cover gate electrode material layer 60a and an upper portion of the lower gate electrode material layer 31a, respectively, through an etch-back process. The resulting combination of the lower gate electrode 31 and the cover gate electrode 60 may surround the upper gate electrode 50. The lower gate electrode 31 may surround the bottom surface and the side surfaces of the upper gate electrode 50, and the cover gate electrode 60 may cover the upper surface of the upper gate electrode 50.

Referring to fig. 6D, the method may include: the gate structure 70 is formed by forming a dielectric gate capping layer 65 to fill the gate trench Tg through a deposition process, and an underlying interlayer dielectric layer 75 is formed to be stacked on the upper surface of the substrate 10. The gate structure 70 may include a gate dielectric layer 20, a cup-shaped lower gate electrode 31, an upper gate electrode 50, a capping gate electrode 60, and a gate capping layer 65.

Subsequently, the method may comprise: through a series of processes described above and with reference to fig. 2K-2Q, bit line stack 80 is formed, inter-level dielectric layer 89 is formed, and storage structure 90 is formed. Referring again to fig. 1E, the method may further include forming an upper interlayer dielectric layer 99 on the storage structure 90.

Fig. 7A to 7I are sectional views illustrating a method for forming an extremely low temperature semiconductor device.

Referring to fig. 7A, the method may include: through a series of processes described above with reference to fig. 2A to 2E and 5A, an isolation region ISO defining an active region ACT in the substrate 10 is formed, source/drain regions 15 are formed, a gate trench Tg is formed, an ion implantation region 17 is formed, a gate dielectric layer 20 is formed, a lower gate electrode material layer 31a of a liner-like shape is conformally formed on the gate dielectric layer 20, and an intermediate gate electrode material layer 41a is conformally formed as a liner on the lower gate electrode material layer 31. The lower gate electrode material layer 31a may include a conductor having a relatively low work function. For example, the lower gate electrode material layer 31a may include polysilicon doped with N-type ions. The intermediate gate electrode material layer 41a may include a conductor having a relatively higher work function than the lower gate electrode material layer 31 a. For example, the intermediate gate electrode material layer 41a may include a conductor capable of forming an ohmic contact with the lower gate electrode material layer 31 a. For example, the intermediate gate electrode material layer 41a may include a barrier metal. Specifically, as an example, the intermediate gate electrode material layer 41a may include titanium nitride (TiN).

Referring to fig. 7B, the method may include forming an upper gate electrode material layer 50a on the intermediate gate electrode material layer 41a to fill the gate trench Tg. The upper gate electrode material layer 50a may include a conductor having a higher work function than the middle gate electrode material layer 41 a. The upper gate electrode material layer 50a may include a metal, a metal compound, or a metal alloy. Specifically, for example, the upper gate electrode material layer 50a may include tungsten (W).

Referring to fig. 7C, the method may include: the upper gate electrode 50 is formed in the gate trench Tg by removing an upper portion of the upper gate electrode material layer 50a through an etch-back process. An upper portion of the upper gate electrode material layer 50a is removed so that an upper surface of the upper gate electrode 50 may be located in the gate trench Tg. The upper surface of the upper gate electrode 50 may be located at a lower level than the source/drain region 15 or below the source/drain region 15.

Referring to fig. 7D, the method may include: the intermediate gate electrode 41 is formed in a cup shape by removing an upper portion of the intermediate gate electrode material layer 41a through an etch-back process to surround the bottom surface and the side surfaces of the upper gate electrode 50. The upper surface of the middle gate electrode 41 may be located at a substantially similar level as the upper surface of the upper gate electrode 50.

Referring to fig. 7E, the method may include: a lower capping gate electrode material layer 42a is formed on the lower gate electrode material layer 31a, the intermediate gate electrode 41 and the upper gate electrode 50 to fill the gate trench Tg. The lower capping gate electrode material layer 42a may include the same material as the intermediate gate electrode 41.

Referring to fig. 7F, the method may include: the lower capping gate electrode 42 is formed to cover the upper surface of the upper gate electrode 50 by removing an upper portion of the lower capping gate electrode material layer 42a through an etch-back process. The bottom surface and the side surfaces of the upper gate electrode 50 may be surrounded by the middle gate electrode 41, and the upper surface of the upper gate electrode 50 may be covered by the lower cover gate electrode 42. The upper surface of the lower coverage gate electrode 42 may be located at a lower level than the source/drain region 15 or below the source/drain region 15.

Referring to fig. 7G, the method may include forming an upper cover gate electrode material layer 32a on the lower gate electrode material layer 31a and the lower cover gate electrode 42 to fill the gate trench Tg. The upper capping gate electrode material layer 32a may include the same material as the lower gate electrode material layer 31 a. When the lower gate electrode material layer 31a and the upper covering gate electrode material layer 32a include the same material, an interface between the lower gate electrode material layer 31a and the upper covering gate electrode material layer 32a may virtually exist. Thus, the interface between the lower gate electrode material layer 31a and the upper overlying gate electrode material layer 32a is represented by a dashed line in fig. 7G.

Referring to fig. 7H, the method may include: the upper cover gate electrode 32 and the lower gate electrode 31 are formed in the gate trench Tg by removing an upper portion of the upper cover gate electrode material layer 32a and an upper portion of the lower gate electrode material layer 31a, respectively, through an etch-back process. The upper capping gate electrode 32 may cover an upper surface of the lower capping gate electrode 42. The upper surface of the overlying gate electrode 32 may be at a higher level than the bottom surface or lowermost region of the source/drain region 15, or above the bottom surface or lowermost region of the source/drain region 15.

Referring to fig. 7I, the method may include: the gate structure 70 is formed by forming a dielectric gate capping layer 65 to fill the gate trench Tg through a deposition process, and an underlying interlayer dielectric layer 75 is formed to be stacked on the upper surface of the substrate 10. The gate structure 70 may include a gate dielectric layer 20, a cup-shaped lower gate electrode 31, a cup-shaped middle gate electrode 41, an upper gate electrode 50, a lower capping gate electrode 42, an upper capping gate electrode 32, and a gate capping layer 65.

Subsequently, the method may comprise: through a series of processes described above and with reference to fig. 2K-2Q, bit line stack 80 is formed, inter-level dielectric layer 89 is formed, and storage structure 90 is formed. Referring again to fig. 1F, the method may further include forming an upper interlayer dielectric layer 99 on the storage structure 90.

Fig. 8A is a diagram conceptually illustrating a memory module 2100 including a very low temperature semiconductor device, in accordance with various embodiments.

Referring to fig. 8A, a memory module 2100 according to one embodiment may include a module substrate 2110, a plurality of very low temperature semiconductor devices 2120 disposed on the module substrate 2110, and a plurality of terminals 2130 disposed on one side of the module substrate 2110. The module substrate 2110 may include a Printed Circuit Board (PCB). Based on the inventive concept of the present disclosure, the very low temperature semiconductor device 2120 may include at least one of the very low temperature semiconductor devices 100A to 100F according to various embodiments. The plurality of terminals 2130 may comprise a metal such as copper. Each terminal may be electrically coupled to each very low temperature semiconductor device 2120.

Fig. 8B is a block diagram conceptually illustrating an electronic system 2300, according to an embodiment.

Referring to fig. 8B, the electronic system 2300 according to the present embodiment may include a main body 2310, a display unit 2360, and an external device 2370. The main body 2310 may include a microprocessor unit 2320, a power supply unit 2330, a function unit 2340 and/or a display controller unit 2350. The body 2310 may include a motherboard or system board with a PCB, and/or a housing. The microprocessor unit 2320, the power supply unit 2330, the function unit 2340 and the display controller unit 2350 may be mounted or provided on or in the main body 2310. The display unit 2360 may be disposed on an upper surface of the body 2310 or inside or outside the body 2310. The display unit 2360 may display images processed by the display controller unit 2350. For example, the display unit 2360 may include a Liquid Crystal Display (LCD), an Active Matrix Organic Light Emitting Diode (AMOLED), or various display panels. The display unit 2360 may include a touch screen. Accordingly, the display unit 2360 may have an input/output function. The power supply unit 2330 may supply current or voltage to the microprocessor unit 2320, the function unit 2340, the display controller unit 2350, and the like. The power supply unit 2330 may include rechargeable batteries, a receptacle for a battery, or a voltage/current converter. Microprocessor unit 2320 may receive voltage from power supply unit 2330 to control functional unit 2340 and display unit 2360. For example, the microprocessor unit 2320 may include a Central Processing Unit (CPU) or an Application Processor (AP). The functional units 2340 may include touch pads, touch screens, volatile/non-volatile memory, memory card controllers, cameras, lights, audio and video playback processors, wireless transmit/receive antennas, speakers, microphones, Universal Serial Bus (USB) ports, and other units having various functions. The microprocessor unit 2320 or the functional unit 2340 may include at least one of the very low temperature semiconductor devices 100A to 100F according to various embodiments.

Figure 8C is a block diagram conceptually illustrating an electronic system 2400, according to one embodiment.

Referring to fig. 8C, the electronic system 2400 according to the present embodiment may include a microprocessor 2414, a memory system 2412, and a user interface 2418, each of which performs mutual data communication via an internal bus 2420. Microprocessor 2414 may include a CPU or an AP. The electronic system 2400 may also include Random Access Memory (RAM)2416 in direct communication with the microprocessor 2414. Microprocessor 2414 and/or RAM 2416 can be packaged in a single package. The user interface 2418 may be used to input information to the electronic system 2400 or to output information from the electronic system 2400. For example, the user interface 2418 may include a touch pad, touch screen, keyboard, mouse, scanner, voice detector, Cathode Ray Tube (CRT) monitor, LCD, AMOLED, Plasma Display Panel (PDP), printer, lights, or various other input/output devices. The memory system 2412 may store operation codes of the microprocessor 2414, data processed by the microprocessor 2414, or external input data. The storage system 2412 may include a memory controller, hard disk, or Solid State Drive (SSD). Based on the technical concept of the present disclosure, the microprocessor 2414, the RAM 2416, and/or the memory system 2412 may include at least one of the very low temperature semiconductor devices 100A to 100F according to various embodiments.

The extremely low temperature semiconductor device according to the above embodiment includes: a gate electrode having a low work function for lowering a threshold voltage, and an ion implantation region for increasing the threshold voltage. Accordingly, each extremely low temperature semiconductor device can have a threshold voltage appropriately adjusted to have good operation performance in an extremely low temperature region.

The very low temperature semiconductor device according to the above embodiment can operate better in the pseudo very low temperature range. The pseudo-cryogenic temperature range may be defined as about 77K +/-7K. The pseudo-cryogenic range can be implemented or established using liquid nitrogen as a relatively inexpensive refrigerant.

Although the present disclosure has been described with respect to particular embodiments, it should be noted that the embodiments are intended to be illustrative, and not restrictive, of the disclosure. Furthermore, it should be noted that the present disclosure may be implemented in various ways by those skilled in the art through substitution, change and modification without departing from the scope of the present disclosure defined by the appended claims.