阅读说明：本技术 一种用于气体传感器接口电路的新型iic模块 (Novel IIC module for gas sensor interface circuit ) 是由 任明远 刘驰 高天航 于 2019-11-06 设计创作，主要内容包括：本发明公开了一种用于气体传感器接口电路的新型IIC模块,涉及集成电路设计领域。该模块用于气体传感器接口电路,实现数据的双向传输,基本框架如图1所示,它包括传感器模块(1),信号读取模块(2),模数转换模块(3),新型IIC模块(4),主机(5),数模转换模块(6),本发明主要针对传感器接口电路传输延迟长,数据单向传输问题,通过新型IIC模块(4)中的数据缓冲模块(401)、移位寄存器模块(402)、SDA线和SCL线,将数据进行缓冲和转换,并且由SDA和SCL线传输,使数据传输延迟减小,数据进行双向传输。(The invention discloses a novel IIC module for a gas sensor interface circuit, and relates to the field of integrated circuit design. The module is used for a gas sensor interface circuit, bidirectional transmission of data is realized, a basic framework is shown in figure 1 and comprises a sensor module (1), a signal reading module (2), an analog-to-digital conversion module (3), a novel IIC module (4), a host (5) and a digital-to-analog conversion module (6), the module mainly aims at the problems of long transmission delay and unidirectional data transmission of the sensor interface circuit, data are buffered and converted through a data buffer module (401), a shift register module (402), an SDA line and an SCL line in the novel IIC module (4), and the data are transmitted through the SDA line and the SCL line, so that the data transmission delay is reduced, and the data are transmitted in a bidirectional mode.)

1. A novel IIC module for a gas sensor interface circuit, the novel IIC module (4) primary structure comprising a data buffer module (401), a shift register module (402), a merge-in-and-out module (403), a serial-in-and-parallel-out module (404), an SDA line and an SCL line, wherein:

data buffer module (401): the input end is connected with the output end of the analog-to-digital conversion module (3), and the output end is connected with the parallel-in serial-out module (403) in the shift register module (402);

shift register module (402): the input is connected to the data buffer module (401) output and the output is connected to the SDA line and the SCL line.

2. The novel IIC module for a gas sensor interface circuit as claimed in claim 1, wherein said shift register module (402) comprises: a merge-out module (403), a serial-in-parallel-out module (404), wherein:

merging-and-exiting module (403): the input end is connected with the output end of the data buffer module (401), and the output end is connected with the SDA line and the SCL line;

a tandem-in and parallel-out module (404): the input end is connected with the SDA line and the SCL line, and the output end is connected with the digital-to-analog conversion module (6).

3. The IIC module of claim 1, wherein said serial-in parallel-out module (404) of said shift register module (402) comprises PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M8, PMOS transistor M10, PMOS transistor M13, PMOS transistor M14, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, NMOS transistor M9, NMOS transistor M11, NMOS transistor M12, and NMOS transistor M15;

wherein: the grid electrode of a PMOS tube M1 is connected with the grid electrode of an NMOS tube M4 to form a D trigger CK end, the source electrode is connected with a power supply VDD, the drain electrode is connected with the drain electrode of the NMOS tube M4, the grid electrodes of the PMOS tube M2 and the NMOS tube M6 and is connected with a clock signal CLK ', the grid electrode of a PMOS tube M2 is connected with the grid electrode of the NMOS tube M6, the grid electrode of the PMOS tube M1 and the drain electrode of the NMOS tube M4 and is connected with the clock signal CLK', the source electrode is connected with the power supply VDD, the drain electrode is connected with the drain electrode of the NMOS tube M6, the grid electrode of the PMOS tube M3 and the grid electrode of the NMOS tube M7 and is connected with the clock signal CLK, the grid electrode of the PMOS tube M3 is connected with the grid electrode of the NMOS tube M7, the drain electrode of the PMOS tube M2 and the drain electrode of the NMOS tube M6 and is connected with the clock signal CLK, the source electrode VDD, the drain electrode of the NMOS tube M7 and is connected with the clock signal CLK, the drain electrode of the NMOS tube M68656, the NMOS tube M9 and the grid electrode, The drain electrodes of the PMOS tube M8 and the NMOS tube M9 are connected, the source electrode is connected with a power supply VDD, the drain electrode is connected with the drain electrode of the NMOS tube M11, the source electrodes of the PMOS tube M13 and the NMOS tube M12, the grid electrode of the PMOS tube M13 is connected with a clock signal CLK', the source electrode is connected with the source electrode of the NMOS tube M12, the drain electrode of the PMOS tube M10 and the drain electrode of the NMOS tube M11, the drain electrode is connected with the drain electrode of the NMOS tube M12, the grid electrode of the PMOS tube M14 and the grid electrode of the NMOS tube M15, the grid electrode of the PMOS tube M14 is connected with the grid electrode of the NMOS tube M15, the source electrode is connected with the power supply VDD, the drain electrode is connected with the drain electrode of the NMOS tube M15 to form a D end of the trigger Q, the source electrode of the NMOS tube M4 is connected with the drain electrode of the NMOS tube M5, the grid electrode of the NMOS tube M5 to form an f end of the D trigger, the source electrode is connected with the ground.

Technical Field

The invention relates to a novel IIC module for a gas sensor interface circuit, which relates to a sensor module (1), a signal reading module (2), an analog-to-digital conversion module (3), a novel IIC module (4), a host (5) and a digital-to-analog conversion module (6), and belongs to the field of integrated circuit design.

Background

In recent years, sensors have been generally used in various fields such as military science and technology, industry, agriculture, and along with the continuous change of demand, the continuous improvement of integrated circuit field design level, the sensor that has digital output, transmission performance are strong can adapt to the demand in market more, consequently improves through gas sensor interface circuit design, realizes that transmission performance's improvement is very important.

Disclosure of Invention

The invention aims to provide a novel IIC module (4) for a gas sensor interface circuit on the basis of the prior art, which realizes the bidirectional transmission of digital signals and improves the transmission speed and the interface circuit load capacity of a sensor on the basis of ensuring the basic functions of the original gas sensor interface circuit, so that the novel IIC module (4) is added on the basis of the original gas sensor interface circuit, a data buffer with a phase inverter chain is adopted to reduce time delay and increase the load capacity, a shift register is adopted to realize the serial-parallel conversion of data, and serial digital signals can be transmitted from the outside.

The above object of the present invention is achieved mainly by the following means:

a basic framework of a gas sensor interface circuit is shown in fig. 1, and comprises a sensor module (1), a signal reading module (2), an analog-to-digital conversion module (3), a novel IIC module (4), a host (5), and a digital-to-analog conversion module (6), wherein:

sensor module (1): the device is used for converting external gas into a signal to be detected;

signal reading module (2): the device is used for reading a signal to be detected generated by the sensor module (1), converting the signal to be detected into a voltage signal, amplifying the voltage signal and eliminating an interference signal;

analog-to-digital conversion module (3): the voltage signal is converted into a parallel digital signal after being amplified by the signal reading module (2);

IIC module (4): for converting the parallel digital signal into a serial digital signal and transmitting the serial digital signal to a host (5);

host (5): the novel IIC module is used for receiving serial digital signals and transmitting external serial digital signals to the novel IIC module (4);

digital-to-analog conversion module (6): the signal reading module (2) is used for converting the serial digital signals output by the novel IIC module (4) into parallel digital signals and transmitting the parallel digital signals back to the signal reading module.

The above-mentioned novel IIC module (4) comprises: the device comprises a data buffer module (401) and a shift register module (402), wherein the shift register module (402) is composed of a parallel-in serial-out module (403) and a serial-in parallel-out module (404); wherein:

data buffer module (401): the buffer circuit is composed of n +1 inverter chains and is used for buffering parallel digital signals of the analog-digital conversion module (3), reducing time delay and enhancing the load capacity;

shift register module (402): the digital signal processing circuit is used for converting a parallel digital signal in the data buffer module (401) into a serial digital signal, inputting the serial digital signal into an SDA line and an SCL line and transmitting the serial digital signal to a host (5) through the SDA line and the SCL line;

merging-and-exiting module (403): the parallel digital signal is used for receiving the parallel digital signal of the data buffer module (401) and converting the parallel digital signal into a serial digital signal;

a tandem-in and parallel-out module (404): the digital signal transmission device is used for converting serial digital signals transmitted by a host (5) into parallel digital signals through SDA lines and SCL lines.

The specific circuit of the serial-IN parallel-out module (404) mentioned above is shown IN fig. 2, and includes n identical D flip-flops, and outputs n DATA IN parallel, the CK end of the D flip-flop a1 is connected to the clock signal CLK, the D end is connected to the SDA line and the SCL line, the serial digital signal DATA-IN transmitted by the SDA line and the SCL line is input to the D end, the Q end is connected to the D end of the D flip-flop a2, and the n D flip-flops are connected IN this manner IN sequence to form the serial-IN parallel-out module (404).

The structure of the aforementioned D flip-flop of the serial-in parallel-out module (404) is shown in fig. 2, and includes a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M8, a PMOS transistor M10, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, an NMOS transistor M7, an NMOS transistor M9, an NMOS transistor M11, an NMOS transistor M12, and an NMOS transistor M15; wherein: the grid electrode of a PMOS tube M1 is connected with the grid electrode of an NMOS tube M4 to form a D trigger CK end, the source electrode is connected with a power supply VDD, the drain electrode is connected with the drain electrode of the NMOS tube M4, the grid electrodes of the PMOS tube M2 and the NMOS tube M6 and is connected with a clock signal CLK ', the grid electrode of a PMOS tube M2 is connected with the grid electrode of the NMOS tube M6, the grid electrode of the PMOS tube M1 and the drain electrode of the NMOS tube M4 and is connected with the clock signal CLK', the source electrode is connected with the power supply VDD, the drain electrode is connected with the drain electrode of the NMOS tube M6, the grid electrode of the PMOS tube M3 and the grid electrode of the NMOS tube M7 and is connected with the clock signal CLK, the grid electrode of the PMOS tube M3 is connected with the grid electrode of the NMOS tube M7, the drain electrode of the PMOS tube M2 and the drain electrode of the NMOS tube M6 and is connected with the clock signal CLK, the source electrode VDD, the drain electrode of the NMOS tube M7 and is connected with the clock signal CLK, the drain electrode of the NMOS tube M68656, the NMOS tube M9 and the grid electrode, The drain electrodes of the PMOS tube M8 and the NMOS tube M9 are connected, the source electrode is connected with a power supply VDD, the drain electrode is connected with the drain electrode of the NMOS tube M11, the source electrodes of the PMOS tube M13 and the NMOS tube M12, the grid electrode of the PMOS tube M13 is connected with a clock signal CLK', the source electrode is connected with the source electrode of the NMOS tube M12, the drain electrode of the PMOS tube M10 and the drain electrode of the NMOS tube M11, the drain electrode is connected with the drain electrode of the NMOS tube M12, the grid electrode of the PMOS tube M14 and the grid electrode of the NMOS tube M15, the grid electrode of the PMOS tube M14 is connected with the grid electrode of the NMOS tube M15, the source electrode is connected with the power supply VDD, the drain electrode is connected with the drain electrode of the NMOS tube M15 to form a D end of the trigger Q, the source electrode of the NMOS tube M4 is connected with the drain electrode of the NMOS tube M5, the grid electrode of the NMOS tube M5 to form an f end of the D trigger, the source electrode is connected with the ground.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

the invention mainly designs a novel IIC module for a gas sensor interface circuit, and for the problems of long transmission delay and unidirectional data transmission, data is buffered and converted through a data buffer module (401), a shift register module (402), an SDA line and an SCL line in the novel IIC module (4), and is transmitted through the SDA line and the SCL line, so that the data transmission delay is reduced, and the data is transmitted in a bidirectional mode.

Drawings

FIG. 1 is a basic block diagram of an interface circuit for a gas sensor according to the present invention;

figure 2 is a circuit diagram of a series-in parallel-out module (404) of a novel IIC module for a gas sensor interface circuit of the present invention.

Detailed Description

For further explanation of the specific content of the present invention, the structural characteristics of the novel IIC module (4), the specific implementation functions of the novel IIC module (4), and the functions of each circuit structure inside the novel IIC module (4) are described. The invention is described in detail with particular reference to the accompanying drawings.

As shown in FIG. 1, the present invention provides a basic frame diagram for an interface circuit of a gas sensor, which includes a sensor module (1), a signal reading module (2), an analog-to-digital conversion module (3), a novel IIC module (4), a host (5), a digital-to-analog conversion module (6), a data buffer module (401), a shift register module (402), a merging-in and merging-out module (403), a serial-in and parallel-out module (404), an SDA line and an SCL line, wherein the sensor module (1) of the gas sensor converts external gas into a signal to be measured, then the signal to be measured of the sensor module (1) is read by the signal reading module (2), the signal to be measured is converted into a voltage signal, then the voltage signal is amplified and input into the analog-to-digital conversion module (3), the amplified voltage signal is converted into a parallel digital signal by the analog-to-digital conversion module (3), and then the parallel digital signal is input, inputting the buffered parallel digital signal into a parallel-serial module (403) in a shift register module (402), converting the parallel digital signal into a serial signal, inputting the serial signal into an SDA line and an SCL line, and then connecting the SDA line and the SCL line with a host (5) to realize the output of the serial digital signal; similarly, the host (5) transmits serial digital signals to the SDA line and the SCL line, inputs the serial digital signals to the serial-in parallel-out module (404) in the shift register module (402), converts the serial digital signals into parallel digital signals, inputs the parallel digital signals into the digital-to-analog conversion module (6), converts the parallel digital signals into analog signals, transmits the analog signals to the signal reading module (2), and finally transmits the analog signals back to the sensor module (1) as the input of the digital signals, so that bidirectional transmission is realized.

As shown IN fig. 2, the serial-IN parallel-out module (404) is composed of n D flip-flops, wherein the clock signal CLK' is the opposite signal of the clock signal CLK, when the clock signal CLK is inputted to the D flip-flop CK terminal, the serial digital signal DATA-IN is inputted to the D flip-flop D terminal, the output terminal Q DATA is equal to the input terminal D DATA-IN, when the next clock signal CLK is inputted to the D flip-flop CK terminal, the current D flip-flop receives new DATA, the next D flip-flop receives the previous serial digital signal DATA-IN, and then sequentially registers IN this way, and generates serial-IN parallel-out of DATA, wherein the D flip-flop f terminal is connected to the NMOS transistor M5, and connected to the clock signal CLKs, for resetting the flip-flop, when the clock signal CLKs is low level, the NMOS transistor M5 is turned on, so that the D flip-flop is reset, when the clock signal CLKs is high level, the f terminal is not reset, and the D flip-flop is suspended temporarily, so that the performance of the D flip-flop is prevented from being influenced due to the long-time operation of the flip-flop.

In view of the foregoing, it is to be seen that the foregoing is illustrative of the embodiments of the invention and that the principles of the invention are described above. The scope of the invention is not limited thereto. Any simple structural changes made by a designer skilled in the art within the scope of the disclosure of the present invention are within the scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the claims.