阅读说明：本技术 三维半导体器件 (Three-dimensional semiconductor device ) 是由 尹壮根 李载德 于 2019-05-29 设计创作，主要内容包括：提供了一种三维半导体器件,所述三维半导体器件包括：下部结构；位于所述下部结构上的堆叠结构,所述堆叠结构包括：下组,所述下组包括在垂直方向上堆叠并且彼此间隔开的栅电极,以及上组,所述上组包括在所述垂直方向上堆叠并且彼此间隔开的栅电极,所述下组和所述上组在所述垂直方向上堆叠；以及垂直结构,所述垂直结构穿过所述堆叠结构。所述垂直结构可以包括垂直芯图案、位于所述垂直芯图案中的垂直缓冲部分以及垂直半导体层。所述垂直结构可以包括穿过所述下组的下垂直部分和穿过所述上组的上垂直部分,所述下垂直部分的上部区域的宽度大于所述上垂直部分的下部区域的宽度。所述垂直缓冲部分位于所述下垂直部分中并位于所述上垂直部分下方。(There is provided a three-dimensional semiconductor device including: a lower structure; a stack on the lower structure, the stack comprising: a lower group including gate electrodes stacked in a vertical direction and spaced apart from each other, and an upper group including gate electrodes stacked in the vertical direction and spaced apart from each other, the lower group and the upper group being stacked in the vertical direction; and a vertical structure passing through the stacked structure. The vertical structure may include a vertical core pattern, a vertical buffer portion in the vertical core pattern, and a vertical semiconductor layer. The vertical structure may include a lower vertical portion passing through the lower group and an upper vertical portion passing through the upper group, and an upper region of the lower vertical portion has a width greater than a width of a lower region of the upper vertical portion. The vertical buffer portion is located in the lower vertical portion and below the upper vertical portion.)

1. a three-dimensional semiconductor device, the three-dimensional semiconductor device comprising:

A lower structure;

A stack structure on the lower structure, the stack structure comprising:

A lower group including gate electrodes stacked in a vertical direction and spaced apart from each other, the vertical direction being a direction perpendicular to an upper surface of the lower structure,

An upper group including gate electrodes stacked in the vertical direction and spaced apart from each other,

The lower group and the upper group are stacked in the vertical direction; and

A vertical structure passing through the stacked structure, wherein,

The vertical structure includes a vertical core pattern, a vertical buffer portion in the vertical core pattern, and a vertical semiconductor layer surrounding an outer side surface of the vertical core pattern,

The vertical structure includes a lower vertical portion passing through the lower set and an upper vertical portion passing through the upper set,

the upper region of the lower vertical portion has a width greater than that of the lower region of the upper vertical portion, and

The vertical buffer portion is located in the lower vertical portion and below the upper vertical portion.

2. the three-dimensional semiconductor device of claim 1, wherein the vertical core pattern is formed of an insulating material and the vertical buffer portion is a void.

3. The three-dimensional semiconductor device of claim 1, further comprising a horizontal structure on the lower structure, the horizontal structure disposed below the stacked structure and connected to the vertical structure, wherein,

The vertical structure further includes a vertical gate dielectric surrounding an outer surface of the vertical semiconductor layer, and

The horizontal structure includes a horizontal gate dielectric extending from the vertical gate dielectric and disposed below the stacked structure.

4. The three-dimensional semiconductor device of claim 3, wherein the horizontal structure further comprises a horizontal semiconductor layer extending from the vertical semiconductor layer and disposed below the stacked structure.

5. The three-dimensional semiconductor device of claim 3,

the horizontal structure further includes a horizontal core pattern extending from the vertical core pattern and disposed below the stacked structure, and

The vertical core pattern and the horizontal core pattern are formed of an insulating material.

6. The three-dimensional semiconductor device of claim 1, further comprising:

A horizontal structure on the lower structure, the horizontal structure disposed below the stacked structure and connected to the vertical structure; and

A support pattern on the lower structure, the support pattern disposed below the stacked structure and passing through the horizontal structure.

7. the three-dimensional semiconductor device of claim 6,

The vertical structure further includes a vertical gate dielectric surrounding an outer surface of the vertical semiconductor layer,

The horizontal structure includes a horizontal gate dielectric extending from the vertical gate dielectric and disposed below the stack structure,

The horizontal structure further comprises a horizontal buffer portion between the stack structure and the lower structure,

the horizontal gate dielectric extends from the vertical gate dielectric along a lower surface of the stack structure, a side surface of the support pattern, and an upper surface of the lower structure, and

The horizontal buffer portion is between a first portion of the horizontal gate dielectric on a lower surface of the stack structure and a second portion of the horizontal gate dielectric on an upper surface of the lower structure.

8. the three-dimensional semiconductor device according to claim 1,

The stacked structure further includes an intermediate group between the lower group and the upper group,

The vertical structure further comprises an intermediate vertical portion passing through the intermediate set,

The width of the lower region of the middle vertical portion is narrower than the width of the upper region of the lower vertical portion, and

the width of the upper region of the intermediate vertical portion is greater than the width of the lower region of the upper vertical portion.

9. The three-dimensional semiconductor device of claim 8, wherein the vertical core pattern is unitary, extending from an interior of the lower vertical portion through the intermediate vertical portion and continuously to the upper vertical portion.

10. The three-dimensional semiconductor device of claim 1, further comprising a horizontal structure on the lower structure, the horizontal structure disposed below the stacked structure and connected to the vertical structure, wherein,

The horizontal structure includes a horizontal core pattern, and

the horizontal core pattern is in contact with the vertical semiconductor layer and is formed of a semiconductor material or a conductive material.

11. the three-dimensional semiconductor device according to claim 1,

The lower structure includes a semiconductor substrate,

the vertical structure further includes a semiconductor pattern epitaxially grown from the semiconductor substrate, and

The vertical semiconductor layer is on and in contact with the semiconductor pattern.

12. The three-dimensional semiconductor device of claim 1, further comprising a horizontal structure on the lower structure, the horizontal structure disposed below the stacked structure and connected to the vertical structure, wherein,

The horizontal structure includes a lower horizontal pattern and an upper horizontal pattern on the lower horizontal pattern, and

One of the lower and upper horizontal patterns includes a conductive material identical to a material of the gate electrode, and the other horizontal pattern includes a conductive material different from the material of the gate electrode.

13. The three-dimensional semiconductor device according to claim 12, further comprising a contact plug in contact with the lower horizontal pattern, the contact plug passing through the upper horizontal pattern and extending in the vertical direction.

14. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising:

a lower structure;

A stack structure on the lower structure, the stack structure comprising:

a lower group including gate electrodes stacked in a vertical direction and spaced apart from each other, the vertical direction being a direction perpendicular to an upper surface of the lower structure,

an upper group including gate electrodes stacked in the vertical direction and spaced apart from each other,

the lower group and the upper group are stacked in the vertical direction;

a separation structure passing through the stacked structure;

vertical structures located between the separation structures and passing through the stacked structures; and

a horizontal structure located on the lower structure and disposed below the stacked structure, and connected to the vertical structure and the partition structure, wherein,

The vertical structure includes a lower vertical portion passing through the lower set and an upper vertical portion passing through the upper set,

Each of the partition structures includes a lower partition portion passing through the lower group and an upper partition portion passing through the upper group,

The upper region of the lower vertical portion has a width greater than that of the lower region of the upper vertical portion, and

The upper region of the lower partition portion has a width greater than that of the lower region of the upper partition portion.

15. The three-dimensional semiconductor device of claim 14, wherein the vertical structure comprises a vertical core pattern, a vertical semiconductor layer surrounding an outer side surface of the vertical core pattern, and a vertical gate dielectric surrounding an outer side surface of the vertical semiconductor layer.

16. The three-dimensional semiconductor device according to claim 15,

the vertical structure further includes a vertical buffer portion in the vertical core pattern,

The vertical buffer portion is located in the lower vertical portion and disposed below the upper vertical portion, and

The vertical buffer portion is a void.

17. The three-dimensional semiconductor device according to claim 14,

Each of the partition structures includes a partition cushioning portion,

Each of the separation structures has a width greater than that of the vertical structure, and

the partition buffering portion is located in the lower partition portion and disposed below the upper partition portion.

18. A three-dimensional semiconductor device comprising:

a lower structure;

A horizontal structure located on the lower structure;

A stacked structure on the horizontal structure, the stacked structure including a plurality of groups stacked in a vertical direction, each of the plurality of groups including gate electrodes stacked in the vertical direction and spaced apart from each other, the vertical direction being a direction perpendicular to an upper surface of the lower structure;

A partition structure passing through the stacked structure and the horizontal structure; and

a vertical structure located between the separation structures and passing through the stacked structure and the horizontal structure, wherein,

the horizontal structure includes a lower horizontal pattern and an upper horizontal pattern on the lower horizontal pattern, and

One of the lower and upper horizontal patterns includes a conductive material identical to a material of the gate electrode, and the other horizontal pattern includes a conductive material different from the material of the gate electrode.

19. the three-dimensional semiconductor device of claim 18, wherein each of the groups comprises alternately and repeatedly stacked gate electrodes and interlayer insulating layers and capping layers on the alternately and repeatedly stacked gate electrodes and interlayer insulating layers.

20. The three-dimensional semiconductor device according to claim 18,

the vertical structure includes a vertical core pattern, a vertical buffer portion in the vertical core pattern, a vertical semiconductor layer surrounding an outer side surface of the vertical core pattern, and a vertical gate dielectric surrounding an outer side surface of the vertical semiconductor layer, and

The horizontal structure includes a horizontal core pattern connected to the vertical semiconductor layer.

Technical Field

Background

The semiconductor device may include gate electrodes stacked in a direction perpendicular to a surface of the semiconductor substrate.

disclosure of Invention

Drawings

Various features will become apparent to those skilled in the art from the detailed description of example embodiments with reference to the accompanying drawings, in which:

fig. 1 shows a schematic block diagram of a three-dimensional semiconductor device according to an example embodiment;

Fig. 2 shows a schematic circuit diagram of an example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 3 shows a top view of an example of a three-dimensional semiconductor device according to an example embodiment;

FIG. 4 shows a cross-sectional view of the area taken along line I-I' in FIG. 3;

fig. 5A and 5B show enlarged partial views of a portion of fig. 4;

fig. 6A and 6B show partially enlarged views of a modified example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 7 shows a partially enlarged view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 8 shows a partially enlarged view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 9 shows a partially enlarged view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

fig. 10 shows a cross-sectional view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

fig. 11 shows a cross-sectional view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 12A illustrates a cross-sectional view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 12B illustrates a cross-sectional view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 12C illustrates a cross-sectional view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 13 shows a cross-sectional view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

FIG. 14 is an enlarged fragmentary view of a portion of FIG. 13;

fig. 15 shows a partially enlarged view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 16 shows a cross-sectional view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

FIG. 17 shows an enlarged fragmentary view of a portion of FIG. 16;

fig. 18 and 19 each show a partially enlarged view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

fig. 20 shows a cross-sectional view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

FIG. 21 shows an enlarged fragmentary view of a portion of FIG. 20;

Fig. 22 to 24 each show a partially enlarged view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

fig. 25 shows a cross-sectional view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

fig. 26 is an enlarged fragmentary view showing a portion of fig. 25;

fig. 27 and 28 each show a partially enlarged view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

fig. 29 is a sectional view showing a modified example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 30 is an enlarged fragmentary view showing a portion of fig. 29;

fig. 31 shows a cross-sectional view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 32 is an enlarged fragmentary view showing a portion of fig. 31;

Fig. 33 shows a cross-sectional view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 34 shows a partially enlarged view of a portion of fig. 33 in an enlarged manner;

Fig. 35 to 38 each show a partially enlarged view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

fig. 39 and 41 show cross-sectional views of modified examples of a three-dimensional semiconductor device according to example embodiments;

FIG. 40 shows an enlarged fragmentary view of a portion of FIG. 38;

fig. 42 and 43 each show a partially enlarged view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

Fig. 44A and 44C show cross-sectional views of a modified example of a three-dimensional semiconductor device according to an example embodiment;

FIG. 44B shows an enlarged, fragmentary view of a portion of FIG. 44A;

fig. 45 shows a cross-sectional view of a modified example of a three-dimensional semiconductor device according to an example embodiment;

FIG. 46 shows an enlarged fragmentary view of a portion of FIG. 45;

Fig. 47 to 49 illustrate cross-sectional views of examples of methods of forming a three-dimensional semiconductor device according to example embodiments;

Fig. 50 and 51 are sectional views showing modified examples of a method of forming a three-dimensional semiconductor device according to example embodiments; and

Fig. 52 and 53 are sectional views showing modified examples of a method of forming a three-dimensional semiconductor device according to example embodiments.

Embodiments relate to a semiconductor device.