阅读说明：本技术 集成电路装置 (IC apparatus ) 是由 廖忠志 于 2019-01-04 设计创作，主要内容包括：此处提供具有接点栅极结构的集成电路与形成集成电路的方法的例子。在一些例子中,集成电路包括存储器,其包含多个鳍状物,与延伸于鳍状物的第一鳍状物与第二鳍状物上的栅极结构。栅极结构包括物理接触第一鳍状物的栅极,以及位于第二鳍状物与栅极之间的栅极介电层。在这些例子中,第一鳍状物包括源极/漏极区与物理接触栅极的掺杂区。(The example of the method for integrated circuit provided herein with contact gate structure and formation integrated circuit.In some instances, integrated circuit includes memory, and it includes multiple fins, with the gate structure on the first fin and the second fin that extend fin.Gate structure includes the grid that the first fin is physically contacted, and the gate dielectric between the second fin and grid.In these examples, the first fin includes the doped region of source/drain regions and physical contact grid.)

1. a kind of IC apparatus, comprising:

One memory, comprising:

Multiple fins；And

One gate structure extends on one first fin and one second fin of the fin, wherein the gate structure Include:

First fin is physically contacted in one grid；And

One gate dielectric, between the grid and second fin.

Technical field

The present invention is about IC apparatus, particularly about its formed method of contact gate structure.

Background technique

Semiconductor IC industry has undergone Fast Growth.In the evolution of integrated circuit, functional density (such as unit core Intraconnections device number in piece area) usually as geometric dimension (minimum component or route that such as processing procedure can be generated) reduces And increase.The processing procedure of size reduction, which typically favors, to be increased production capacity and reduces relevant cost.However, size reduction also will increase it is whole Close the complexity of the design and manufacture of the device of these integrated circuits.With the progress of manufacturing method, make what complexity improved When design, accuracy and confidence level can be still had both.

For example, the implementable three dimensional design of the progress of manufacturing method such as fin-shaped field-effect transistor.Fin-shaped field-effect transistor It is contemplated that for the general plane device of self-reference substrate outwardly convex to grid.Illustrative fin-shaped field-effect transistor has thin fin-shaped Object or fin structure, self-reference substrate upwardly extend.The channel region of field-effect transistor is formed in this vertical fin, and grid position In on the channel region of fin (as cladding channel region around).Grid around cladding fin can increase channel region and grid it Between contact area, and grid can be via more side control channels.It is more than one kind in the way of above-mentioned apparatus.In some applications In, fin-shaped field-effect transistor can reduce short-channel effect, reduce leakage current and increase electric current.In other words, these devices are than flat Face device faster, it is smaller and more efficiently.

Whether planar transistor, fin-shaped field-effect transistor or other non-planar devices, constitute the transistor of integrated circuit It can be achieved to calculate to a variety of purposes of storage.IC apparatus may include million meters or 1,000,000,000 meter transistor be configured at calculating In core, memory (such as static random access memory), I/O unit and/or other structures.In conclusion storage Minimum space in device between the smallest transistor size and transistor may generate far-reaching shadow to the circuit size of completion It rings.

Summary of the invention

The IC apparatus that one embodiment of the invention provides, comprising: memory, comprising: multiple fins；And grid Structure extends on the first fin and the second fin of fin, and wherein gate structure includes: grid, physical contact the One fin；And gate dielectric, between grid and the second fin.

Detailed description of the invention

Figure 1A and 1B is the flow chart of the production method of the workpiece in various embodiments of the present invention, with contact grid.

Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, with 20A is top view of the workpiece in a variety of stages of production method in various embodiments of the present invention.

Fig. 2 B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, with 20B is in various embodiments of the present invention, and workpiece is in a variety of stages of production method, along the cross-sectional view of gate planar.

Fig. 2 C, 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, 17C, 18C, 19C, with 20C is in various embodiments of the present invention, and workpiece is in a variety of stages of production method, along the section view of the plane of fin length Figure.

Figure 21 is the process of the production method of the workpiece of the contact grid in various embodiments of the present invention, with a variety of compositions Figure.

Figure 22 A, 23A, 24A, 25A, 26A and 27A are in various embodiments of the present invention, and workpiece is in a variety of of production method Top view in stage.

Figure 22 B, 23B, 24B, 25B, 26B and 27B are in various embodiments of the present invention, and workpiece is in a variety of of production method In stage, along the cross-sectional view of gate planar.

Figure 22 C, 23C, 24C, 25C, 26C and 27C are in various embodiments of the present invention, and workpiece is in a variety of of production method In stage, along the cross-sectional view of the plane of fin length.

Figure 28 is the process of the production method of the workpiece of the contact grid in various embodiments of the present invention, with a variety of compositions Figure.

Figure 29 A, 30A, 31A, 32A, 33A and 34A are in various embodiments of the present invention, and workpiece is in a variety of of production method Top view in stage.

Figure 29 B, 30B, 31B, 32B, 33B and 34B are in various embodiments of the present invention, and workpiece is in a variety of of production method In stage, along the cross-sectional view of gate planar.

Figure 29 C, 30C, 31C, 32C, 33C and 34C are in various embodiments of the present invention, and workpiece is in a variety of of production method In stage, along the cross-sectional view of the plane of fin length.

Wherein, the reference numerals are as follows:

100,2100,2800 method

102、104、106、108、110、112、114、116、118、120、122、124、126、128、130、132、134、 136、138、140、142、2102、2104、2106、2108、2110、2112、2114、2802、2804、2806、2808、2810、 2812,2814,2816 step

200,2200,2900 workpiece

202 gate planars

The plane of 204 fin length

206 substrates

207A, 207B, 1402 doped regions

208 fins

210 isolation structures

302 occupy-place grids

304 occupy-place grid materials

306,1202,2404,3004 photoresist layer

402 grid spacers

502,802 recess

602 source/drain structures

702 first interlayer dielectric layers

902,2604 boundary layer

1002 gate dielectrics

1102,2402,3002 hard mask layer

1502,2302 cap rock

1504,2304 work-function layer

1506,2306,2606 electrode filling layer

1508,2308 gate structure

1602 gate caps

1702 source/drain polar contacts

1703 metal silicide layers

1704,2004 adhesion coating

1706,2006 filler

1802 second interlayer dielectric layers

2002 contacts

2008A, 2008B static random access memory

2010A, 2010B pull up transistor

2012A, 2012B pull-down transistor

2014A, 2014B pass gate transistor

2015A, 2015B contact grid

2602 contact areas

Specific embodiment

It is understood that different embodiments or the implementable different structure of the invention of example that following the description provides.It is special The embodiment for determining component and arrangement is to simplify the present invention rather than the limitation present invention.For example, first component is formed in the Narration on two components both includes directly contact, or both between be separated with other additional members and non-direct contact.In addition, this When structure in inventive embodiments connects and/or is coupled to another structure, it may include that structure directly contacts, also may include structure Between be folded with other structures, therefore structure and non-direct contact.

In addition, spatial relative terms such as " lower section ", " under it ", " lower ", " top ", " upper " or similar Term, which can be used for simplifying, illustrates a certain element and the relativeness of another element in the example shown.Spatial relative terms are extensible The element extremely used with other directions, and it is not limited to diagram direction.In addition, label is repeated in a variety of examples of the disclosure, But these repeat only to illustrate to simplified with clear, do not represent the list between different embodiments and/or setting with identical label Corresponding relationship having the same between member.

Illustrative integrated circuit includes multiple circuit devices (such as fin-shaped field-effect transistor, plane field-effect transistor, bipolar Junction transistor, light emitting diode, storage device, other actives and/or passive device, or the like), via intraconnections knot Structure electric property coupling.Internal connection-wire structure may include any number of dielectric layer of vertical stacking, and be laterally extended in nonwoven fabric from filaments Conducting wire.Through-hole can extend vertically, to connect other conducting wires in the conducting wire and adjacent layer in one layer.It is similar Ground, contact can extend vertically between conducting wire and the structure of substrate grade.Route, through-hole, the bogey together with contact Between signal, electric power and ground wire with operation circuit.

It is intended to be electrically coupled to the structure of adjacent second transistor in the structure (such as source/drain structures) of the first transistor In the example of (such as gate structure), docking contact can be used.Docking contact can be plain conductor layer or multiple conductor layers, extend Most bottom dielectric layer across internal connection-wire structure is with physics and electric property coupling transistor arrangement, without the conducting wire of intermediary.So And include the internal connection-wire structure of contact, it typically results in circuit size and is difficult to reduce.Reduced space especially between transistor When, docking contact tendency is shorted to other transistors.

To solve this problem and other problems, other modes can be used and replace docking contact.For example, settable crystal The gate structure of pipe makes conductive electrode directly contact the semiconductor portions of adjacent transistor, brilliant with direct physics and electric property coupling Body pipe.It is compared with contact is docked, contact grid can reduce expected outer short-circuit chance.This control improves can reduction of gate spacing And/or fin spacing, while maintaining acceptable yield.When contact grid for static random access memory area with it is other In compact district, plant bulk and space, and corresponding increase device density can be obviously reduced.

Another advantage of contact grid can release the line areas that docking contact may occupy.For example, due to connecing Point is contact, can extend up through dielectric layer to being enough to couple the height of metallic circuit.When docking contact is intended to couple source Pole/drain electrode structure need to set reserved area in metallic circuit layer to gate structure and when being not coupled to metallic circuit to avoid short circuit. In contrast, the contact grid in a variety of examples may not extend to the height for being enough to be coupled to metallic circuit, therefore metallic circuit Contact grid can be higher than without short circuit.

Even if the resistance of contact grid is greater than the resistance of docking grid, still have the advantage that as follows.It is used in contact grid In an example of sram device, high electrical resistance can slow down static random access memory because charge injects (such as α Particle injection, neutron injection or similar injection), unexpected electric discharge caused by noise conditions or other flexible mistakes.Change speech It, contact grid is compared with contact is docked, and can improve the flexible error rate of device.In these modes and other modes, contact Grid can reduce plant bulk, increases device density and/or improve confidence level.It however unless stated otherwise, must without embodiment Specific advantages need to be provided.

The embodiment of the present invention provides contact grid and to the example for the technology for forming grid.It is brilliant with coupling fin-shaped field-effect The example of the formed method of circuit of the contact grid of body pipe device illustrates collocation Figure 1A to 20C.Figure 1A and 1B is this hair In bright various embodiments, the flow chart with the method 100 of workpiece 200 of contact grid is made.Before method 100, among, With can carry out additional step later, and the method 100 of other embodiments is replaceable or omit some steps.

Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, with 20A is top view of the workpiece 200 in a variety of stages of the method 100 of production in various embodiments of the present invention.Fig. 2 B, 3B, It 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, is a variety of realities of the present invention with 20B It applies in example, workpiece 200 is in a variety of stages of the method 100 of production, along the cross-sectional view of gate planar 202.Fig. 2 C, 3C, 4C, It 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, 17C, 18C, 19C, is a variety of implementations of the present invention with 20C In example, workpiece 200 is in a variety of stages of the method 100 of production, along the cross-sectional view of the plane 204 of fin length.Fig. 2A Simplify to 20C in the hope of clearly illustrating concept of the present invention.It can integrate supernumerary structure in workpiece 200, and the workpiece of other embodiments The 200 replaceable or some following structures of omission.

As shown in the step 102 and Fig. 2A to 2C of Figure 1A, workpiece 200 is received.Workpiece 200 includes substrate 206, and substrate Device will be formed on 206.In a variety of examples, substrate 206 include semiconductor element (single-element) such as crystalline texture silicon or Germanium；Semiconducting compound such as silicon carbide, GaAs, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide；Semiconducting alloy is such as SiGe, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, Gallium indium arsenide, InGaP and/or gallium arsenide phosphide indium；Non-semiconductor material Material such as soda-lime glass, fused silica, vitreous silica and/or calcirm-fluoride；And/or combinations of the above.

Substrate 206 can have it is consistent composition or comprising a variety of nonwoven fabric from filaments, and optionally etch some nonwoven fabric from filaments with Form fin.Nonwoven fabric from filaments can have similar or different composition.In various embodiments, the nonwoven fabric from filaments of some substrates can have Inconsistent composition is strained with inducing device to adjust device efficiency.The example of layered substrate includes the substrate of silicon on insulating layer 206.In these examples, one layer of substrate 206 may include the oxide of insulating layer such as semiconductor, the nitride of semiconductor, half The nitrogen oxides of conductor, the carbide of semiconductor and/or other suitable insulating materials.

Doped region such as wellblock can be formed on substrate 206.The some parts of substrate 206 can doped p type admixture such as boron, difluoro Change boron or indium, and the other parts of substrate 206 can adulterate N-shaped admixture such as phosphorus or arsenic；And/or other comprising combinations of the above Suitable admixture.As shown in Fig. 2A to 2C, first group of doped region is denoted as 207A, and second group of doped region is denoted as 207B. For reference purpose, doped region 207A and 207B are shown in the top view of Fig. 2A, even if substrate 206 is blocked in itself.One In a little examples, doped region 207A is opposite with the doping form of 207B.In this instance, doped region 207A adulterates N-shaped admixture, and adulterates Area 207B doped p type admixture.

In some instances, the device on substrate 206 to be formed in extends substrate 206.For example, fin-shaped field-effect is brilliant Body pipe and/or other non-planar devices can be formed in the fin 208 on substrate 206.The fin 208 of device refers to any Bulge-structure, and include the fin 208 of fin-shaped field-effect transistor device, and other protuberances being used to form on substrate 206 The fin 208 of active and passive device.The forming method of fin 208 can be to deposit a variety of nonwoven fabric from filaments on substrate 206, In The part of etchable substrate 206 and/or other appropriate technologies after etching nonwoven fabric from filaments.For example, the patterning of fin 208 One or more photolithographic processes can be used in method, and it includes double patterning processing procedure or multiple patterning process.In general, double Multigraph patterning process or multiple patterning process combination light lithography and self-aligning process, the pattern spacing generated are less than single straight Connect the resulting pattern spacing of photolithographic processes.For example, an embodiment forms sacrificial layer on substrate, and uses light lithography system Journey sacrificial patterned.Self-aligning process is used to form spacer along the side wall of patterned sacrificial layer.Then it removes sacrificial Domestic animal layer, and can be used for patterning fin after the spacer retained.

Fin 208 can be identical or different with the composition of substrate 206.For example, the substrate 206 of some embodiments is main Comprising silicon, and fin 208 includes the one layer or more for being mainly germanium or silicon germanium semiconductor.In some embodiments, substrate 206 wraps Containing silicon germanium semiconductor, and fin 208 includes the silicon germanium semiconductor of one layer or more difference SiGe ratio.

Fin 208 physics and can electrically be separated with isolation structure 210 such as fleet plough groove isolation structure each other.It is real herein It applies in example, 208 self-reference substrate 206 of fin extends through isolation structure 210 and is higher than isolation structure 210, therefore formed later Gate structure can be around fin 208.In a variety of examples, isolation structure 210 includes the oxygen of dielectric material such as semiconductor Compound, the nitride of semiconductor, semiconductor carbide, adulterate the silicate glass of fluorine, low-k dielectric material, And/or other suitable dielectric materials.

As shown in the step 104 and Fig. 3 A to 3C of Figure 1A, occupy-place grid 302 is formed on the channel region of fin 208.Source Carrier stream (such as fin-shaped field-effect of the electron stream of the fin-shaped field-effect transistor in N-shaped channel and p-type channel between pole/drain electrode structure The hole stream of transistor) channel region is passed through, and gate structure can be applied voltages to control above-mentioned carrier stream.Above-mentioned gate structure With channel region adjacent and about channel region.When the material of gate structure to some processing procedures for example source/drain activation annealing is sensitive when, Processing procedure removes occupy-place grid 302 then to be initially formed occupy-place grid 302 to be replaced into gate structure unit after grid can be used (such as grid, gate dielectric, boundary layer and analog).

In one example, the step of forming occupy-place grid 302 includes deposition occupy-place grid material 304 such as polysilicon, dielectric material Material (such as the oxide of semiconductor, the nitride of semiconductor, the nitrogen oxides of semiconductor, the carbide of semiconductor, semiconductor Carbon nitrogen oxide, or the like) and/or other suitable materials.In various embodiments, occupy-place grid material 304, which can have, appoints Any suitable processing procedure such as chemical vapor deposition, high-density plasma chemical gas phase can be used in what suitable thickness, forming method Deposition, physical vapour deposition (PVD), atomic layer deposition, spin-on deposition and/or other appropriate deposition process.Occupy-place grid material 304 can be deposited as consistent nonwoven fabric from filaments, and occupy-place grid material 304 is patterned in photolithographic processes.

In these examples, photoresist layer 306 is formed on occupy-place grid material 304, and patterns photoresist layer 306 to define Occupy-place grid 302.Illustrative photoresist layer 306 includes light-sensitive material, generates change of properties when exposure.This change of properties can In the patterned processing procedure of lithographic, for selectively removing the exposed portion or unexposed portion of photoresist layer.In one example, light Light in specific pattern of the microlithography system to depend on light shield, exposes photoresist layer 306.It is hit across light shield or from the light that light shield reflects Photoresist layer 306 is hit, photoresist layer 306 is transferred to the pattern that will be formed on light shield.In other examples, the figure of photoresist layer 306 Case method is using direct write or without light shield lithographic techniques, such as laser patterning, e-beam patterning and/or ion beam pattern Change.

Once exposing photoresist layer 306, that is, develop photoresist layer 306 to retain the exposed portion or unexposed portion of photoresist layer. Illustrative patterning process include soft baking photoresist layer 306, aligned mask, exposure, postexposure bake, develop photoresist layer 306, It rinses and dry (such as hard baking).Patterned photoresist layer 306 exposes the part for the occupy-place grid material 304 to be removed.

As shown in the step 104 and Fig. 3 A to 3C of Figure 1A, the exposed portion of occupy-place grid material 304 is etched, with further Define occupy-place grid 302.Etch process may include any suitable etching technique, such as wet etching, dry ecthing, reactive ion Etching, ashing and/or other engraving methods.Any suitable etchant can be used in etch process, and it includes the etchings based on oxygen The etchant based on etchant, chlorine based on agent, fluorine, the etchant based on bromine, the etchant based on iodine, other suitable etchings Agent liquid, gas or plasma and/or combinations of the above.Specifically, etching step and chemical agent are settable with etching Occupy-place grid material 304, and insignificantly etch fin 208 or isolation structure 210.It after the etching, can be from occupy-place grid Material 304 removes any remaining photoresist layer 306.

As shown in the step 106 and Fig. 4 A to 4C of Figure 1A, grid spacer 402 is formed in the side surface of occupy-place grid 302 On.In a variety of examples, grid spacer 402 includes suitable material such as dielectric material (such as the oxygen of semiconductor of one layer or more Compound, the nitride of semiconductor, the nitrogen oxides of semiconductor, the carbide of semiconductor, semiconductor carbon nitrogen oxide or similar Object), spin on glass, tetraethoxy-silicane alkoxide, plasma enhanced oxidation object, high-aspect-ratio processing procedure formed oxidation Object and/or other suitable materials.In one embodiment, grid spacer 402 respectively contains the first layer of silica, silicon nitride The second layer on first layer and the third layer of silica is on the second layer.In embodiment, grid spacer 402 is every A layer thickness is between about 1nm between about 10nm.

Any suitable deposition technique, such as chemical gaseous phase can be used in its forming method of the nonwoven fabric from filaments of grid spacer 402 Deposition, high density plasma CVD, atomic layer deposition, or the like.In one example, grid spacer 402 Nonwoven fabric from filaments be deposited on the method on occupy-place grid 302 and isolation structure 210, using the technology of compliance.Then alternative Ground etches the nonwoven fabric from filaments of grid spacer 402, with from occupy-place grid 302, fin 208, with the horizontal surface of isolation structure 210 The nonwoven fabric from filaments of grid spacer 402 is removed, and retains the nonwoven fabric from filaments of grid spacer 402 in the vertical surface of occupy-place grid 302 On.Above-mentioned steps can define grid spacer 402 along the side wall of occupy-place grid 302.Etch process can be used any suitable Etching method such as wet etching, dry ecthing, reactive ion etching, ashing and/or other etching methods, and can be used any suitable Based etch chemistry.Etching method can change with based etch chemistry with the nonwoven fabric from filaments of the grid spacer 402 of etching, to etch spy Determine material and etch the material except being expected with minimizing.In these embodiments, etch process is arranged to etch anisotropicly Gate spacer nitride layer, to retain the part of grid spacer 402 on the vertical sidewall of occupy-place grid 302.

As Figure 1A step 108 and Fig. 5 A to 5C shown in, on fin 208 carry out etch process to generate recess 502, It can be used to form source/drain structures.Etch process can be used any suitable engraving method, for example, wet etching, dry ecthing, Reactive ion etching and/or other etching methods, and any suitable based etch chemistry such as carbon tetrafluoride, difluoro first can be used Alkane, fluoroform, other suitable etchants and/or combinations of the above.Engraving method and based etch chemistry can be selected to etch fin 208, and insignificantly etch occupy-place grid 302, grid spacer 402 and/or isolation structure 210.

As shown in the step 110 and Fig. 6 A to 6C of Figure 1A, epitaxial manufacture process is carried out, on workpiece 200 with source/drain of growing up Structure 602 is in recess 502.In a variety of examples, epitaxial manufacture process include chemical vapour deposition technique (such as vapour phase epitaxy and/or Ultra-high vacuum CVD), molecular beam epitaxy and/or other suitable processing procedures.Gas phase and/or liquid can be used in epitaxial manufacture process The predecessor of phase is acted on the ingredient (such as silicon or SiGe) of substrate 206 to form source/drain structures 602.Source/drain The semiconductor component of structure 602 can be similar or different from remaining fin 208.For example, siliceous source/drain structures 602 can be formed on the fin 208 containing SiGe, and vice versa.It is had more than when source/drain structures 602 contain with fin 208 When a kind of semiconductor element, the element ratio of the two can be substantially the same or different.In a variety of examples, source/drain structures 602 include SiGe with fin 208, and the germanium ratio of source/drain structures 602 is between about 30% to about 75%, and fin-shaped The germanium ratio of object 208 is between about 10% to about 40%.

Can in-situ doped source pole/drain electrode structure 602, make that it includes p-doping such as boron, boron difluoride or indiums；N-shaped admixture Such as phosphorus or arsenic；And/or other suitable admixtures comprising combinations of the above.In additional or other embodiments, can formed source electrode/ Implant processing procedure (such as junction implant processing procedure) is carried out after drain electrode structure 602, with doped source/drain structure 602.To specific admixture For form, can doped source/drain structure 602 by opposite in the form of remaining fin 208.To N-shaped lane device Speech, the doping N-shaped admixture of fin 208, and 602 doped p type admixture of source/drain structures, and vice versa (to p-type channel dress For setting).Once admixture is imported source/drain structures 602, dopant activation processing procedure such as rapid thermal annealing can be carried out and/or is swashed Photo-annealing processing procedure is to activate admixture.

As shown in the step 112 and Fig. 7 A to 7C of Figure 1A, the first interlayer dielectric layer 702 is formed on workpiece 200.First layer Between dielectric layer 702 be not shown in the top view of Fig. 7 A, to avoid other units for blocking workpiece 200.First interlayer dielectric layer 702 are used as insulating layer, conducting wire sustainable and that electrical multi-layer internal connection line is isolated.Multiple layer inner connection line conversely speaking, Structure can electrically in connection workpiece 200 unit, such as source/drain structures 602 and the gate structure that is formed later.First layer Between dielectric layer 702 may include dielectric material (oxide of such as semiconductor, the nitride of semiconductor, the nitrogen oxides of semiconductor, half The carbide of conductor, or the like), spin on glass, adulterate fluorine silicate glass, phosphosilicate glass, boron phosphorus silicic acid Salt glass, Black(the Applied Materials purchased from California Santa Clara), xerogel, gas glue, Noncrystal carbon fluoride, Parylene, benzocyclobutene,(the Dow Chemical purchased from Michigan Midland), And/or combinations of the above.The forming method of first interlayer dielectric layer 702 can be any suitable processing procedure, comprising chemical vapor deposition, Physical vapour deposition (PVD), spin-on deposition and/or other suitable processing procedures.

The method for forming the first interlayer dielectric layer 702 may include that CMP step is carried out on workpiece 200, with certainly The first interlayer dielectric layer of top removal 702 of occupy-place grid 302.Etch-back processing procedure can be carried out after CMP step, with Any remaining first interlayer dielectric layer 702 is removed from occupy-place grid 302.

As shown in the step 114 and Fig. 8 A to 8C of Figure 1A, a part of grid displacement processing procedure is carried out as removed occupy-place grid 302, to provide recess 802 between grid spacer 402.The method for removing occupy-place grid material 304 may include one or more Etch process (such as wet etching, dry ecthing or reactive ion etching), the based etch chemistry used is optionally etched and is accounted for Position grid material 304, and insignificantly etch adjacent material such as fin 208, source/drain structures 602, grid spacer 402, the first interlayer dielectric layer 702 and analog.

Functional gate structure is subsequently formed in the recess defined in removal occupy-place grid material 304.Such as the step of Figure 1A 116 with shown in Fig. 9 A to 9C, and boundary layer 902 is formed on the upper surface and side surface of fin 208 of channel region.Boundary layer 902 may include the oxide of boundary material such as semiconductor, the nitride of semiconductor, the nitrogen oxides of semiconductor, other semiconductors Dielectric layer, other suitable interface materials and/or combinations of the above.Boundary layer 902 can have any suitable thickness, be formed Any suitable processing procedure, including hot growth, atomic layer deposition, chemical vapor deposition, high-density plasma chemical can be used in method Vapor deposition, physical vapour deposition (PVD), spin-on deposition and/or other suitable deposition manufacture process.In some instances, interface The forming method of layer 902 is thermal oxidation process, and includes thermal oxide (such as siliceous fin of the semiconductor in fin 208 silica, the silicon germanium oxide of the fin containing SiGe, or the like).

As shown in the step 118 and Figure 10 A to 10C of Figure 1A, gate dielectric 1002 is formed on boundary layer 902, can Along the vertical surface of grid spacer 402.Gate dielectric 1002 can include one or more of dielectric material, and feature usually exists Dielectric constant relative to silica.In some embodiments, gate dielectric 1002 includes the dielectric material of high dielectric constant Such as hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, hafnium oxide tantalum, hafnium oxide titanium, hafnium oxide zirconium, zirconium oxide, aluminium oxide, hafnium oxide- Aluminium oxide alloy, the dielectric material of other suitable high dielectric constants and/or combinations of the above.In additional or other embodiments In, gate dielectric 1002 may include the nitrogen oxygen of the oxide of other dielectric layers such as semiconductor, the nitride of semiconductor, semiconductor Compound, the carbide of semiconductor, amorphous carbon, the oxide of tetraethoxysilane, other suitable dielectric materials and/or above-mentioned Combination.Any suitable processing procedure can be used in the forming method of gate dielectric 1002, includes atomic layer deposition, plasma enhancing Atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma CVD, Physical vapour deposition (PVD), spin-on deposition and/or other appropriate deposition process.Gate dielectric 1002 can have any suitable Thickness.In some instances, the thickness of gate dielectric 1002 is between about 0.1nm between about 3nm.

In these regions that final grid is electrically coupled to source/drain structures, boundary layer 902 can be removed and be situated between with grid Electric layer 1002.As shown in the step 120 and Figure 11 A to 11C of Figure 1A, hard mask layer 1102 is formed on workpiece 200, for example formed On gate dielectric 1002 in recess 802.Hard mask layer 1102 may include any suitable material.In a variety of examples, firmly Mask layer 1102 include dielectric material (oxide of such as semiconductor, the nitride of semiconductor, semiconductor nitrogen oxides, partly lead The carbide of body, semiconductor carbon nitrogen oxide, or the like) and/or other suitable materials.The formation side of hard mask layer 1102 Any suitable processing procedure can be used in method, heavy comprising chemical vapor deposition, high density plasma CVD, physical vapor Product, atomic layer deposition, spin-on deposition and/or other suitable deposition manufacture process.

As shown in the step 122 and Figure 12 A to 12C of Figure 1A, hard mask layer 1102 is patterned to expose the grid to be removed The region of dielectric layer 1002 and boundary layer 902 makes the physical gate being subsequently formed and fin 208 in electrical contact.In one example, The photolithographic processes of patterning hard mask layer 1102 include: to form photoresist layer 1202 on hard mask layer 1102, and lithographic exposes light Photoresist layer 1202 after resistance layer 1202, with development exposure is with the part of the exposing hard mask layer 1102 to be removed.Photolithographic processes It substantially can be such as the step 104 of Figure 1A.

After photolithographic processes, the patterning method of step 122 may include etch process to remove hard mask layer 1102 Exposed area.Etch process may include any suitable etching technique, for example, wet etching, dry ecthing, reactive ion etching, Ashing and/or other engraving methods.Any suitable etchant can be used in etch process, and it includes etchant, the fluorine based on oxygen Based on etchant, the etchant based on chlorine, the etchant based on bromine, the etchant based on iodine, other suitable etchant liquid Body, gas or plasma and/or combinations of the above.In one example, etch process includes to wait to etching technique, is used Etchant is arranged to remove the material of hard mask layer 1102, and does not etch between photoresist layer 1202 or adjacent material such as grid substantially Parting 402 and the first interlayer dielectric layer 702.Etching can expose gate dielectric 1002 and the part to be removed of boundary layer 902.

In conclusion removing gate dielectric from fin 208 as shown in the step 124 and Figure 13 A to 13C of Figure 1B 1002 with the exposed portion of boundary layer 902, and removing position is that subsequent gate is coupled at fin 208.This step may include Etch process such as wet etching, dry ecthing, reactive ion etching, ashing and/or other etching methods.Etch process, which can be used, appoints What suitable etchant includes etchant, the etchant based on fluorine, the etchant based on chlorine, the etching based on bromine based on oxygen Etchant, other suitable etchant liquid, gas or plasmas and/or combinations of the above based on agent, iodine.In this example In, etch process includes wet etch techniques, and the material of gate dielectric 1002 with boundary layer 902 can be removed in the etchant used Material, and insignificantly etch fin 208, source/drain structures 602, hard mask layer 1102, grid spacer 402 or other Adjacent material.

As shown in the step 126 and Figure 14 A to 14C of Figure 1B, doping fin 208 will contact the part of grid, to reduce Resistance between contact grid and adjacent source/drain structures 602.The doped region 1402 of fin 208 substantially can be as above It states.In some instances, using ion disposing process doping fin 208 doped region 1402, and its admixture species with it is adjacent Source/drain structures 602 in admixture have same modality (such as N-shaped or p-type), therefore the form of doped region 1402 and remaining Fin 208 form it is opposite.In these examples that source/drain structures 602 include p-doping such as boron, fin 208 Doped region 1402 it is doped with comprising boron (such as boron -11, boron difluoride, or the like), indium or other p-dopings.In source Pole/drain electrode structure 602 includes in N-shaped admixture such as these examples of phosphorus or arsenic, and the doped region 1402 of fin 208 is doped with packet Phosphorous, arsenic and/or other N-shaped admixtures.Doped region 1402 can be doped into any suitable dopant concentration.In a variety of examples, mix The dopant concentration in miscellaneous area 1402 is between about 1 × 10¹⁴Atom/cm²To 5 × 10¹⁵Atom/cm²Between.Hard mask layer 1102 and/or Photoresist layer 1202 can be used as implant mask, to protect remaining fin 208 from being adulterated by admixture species.

As shown in the step 128 and Figure 15 A to 15C of Figure 1B, etching and hard mask layer 1102 removable after implant and photoresist Layer 1202, and retain recess to be used to form remaining gate structure 1508.The removal of hard mask layer 1102 and photoresist layer 1202 Method can be etch process such as wet etching, dry ecthing, reactive ion etching, ashing and/or other engraving methods.In an example In, etch process is arranged to remove the material of hard mask layer 1102 Yu photoresist layer 1202, and does not substantially etch adjacent material such as Grid spacer 402.

As shown in the step 130 and Figure 15 A to 15C of Figure 1B, grid is formed on workpiece 200.Specifically, grid is formed On boundary layer 902 and gate dielectric 1002 in region of the grid as grid, and grid is formed directly into as contact Region in fin 208 on (for example be formed directly on the doped region 1402 of fin 208).

Grid may include multiple and different conductive layers, than three illustrative nonwoven fabric from filaments (cap rocks 1502, work-function layer as shown 1504, with electrode filling layer 1506).About first layer, the step of some examples form grid includes forming cap rock 1502 in work On part 200.Cap rock 1502 is formed directly in grid as on the gate dielectric 1002 in the region of grid, also can direct shape In upper horizontal surface and vertical sidewall at the fin 208 in region of the grid as contact.To reduce resistance, fin 208 can not extend through entire grid along fin length direction.This can provide additional vertical surface in fin end, Grid (such as its cap rock 1502) physics and it is electrically coupled at fin 208.

Cap rock 1502 may include any suitable conductive material such as metal (such as tungsten, aluminium, tantalum, titanium, nickel, copper, cobalt or class Like object), metal nitride and/or metal silicon nitride compound, and its deposition method can for chemical vapor deposition, atomic layer deposition, Plasma enhanced chemical vapor deposition, plasma enhanced atomic layer deposition, physical vapour deposition (PVD) and/or other are suitable heavy Product processing procedure.In various embodiments, cap rock 1502 includes tantalum nitride silicon, tantalum nitride and/or titanium nitride.

In some instances, the method for forming grid includes forming one or more work-function layers 1504 on cap rock 1502. The material of suitable work-function layer 1504 includes the work function material of N-shaped and/or p-type, the end view corresponding dress of gate structure 1508 Depending on setting form.Illustrative p-type workfunction metal includes titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminium, tungsten nitride, zirconium silicide, molybdenum Silicide, tantalum silicide, nickel silicide, other suitable p-type workfunction metals and/or combinations of the above.Illustrative N-shaped Workfunction metal include titanium, silver, tantalum aluminium, tantalum carbide aluminium, TiAlN, tantalum carbide, carbon tantalum nitride, tantalum nitride silicon, manganese, zirconium, its His suitable N-shaped work function material and/or combinations of the above.The deposition method of work-function layer 1504 can be any appropriate technology, Comprising atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, plasma enhanced atomic layer deposition, Physical vapour deposition (PVD) and/or combinations of the above.Since p-type has different work-function layers 1504, some examples from N-shaped device The electricity of p-type device is deposited on using dielectric hard mask in the first deposition manufacture process of the work-function layer 1504 of depositing n-type On extremely, and dielectric hard mask is used to avoid N-shaped dress is deposited in the second deposition manufacture process of the work-function layer of depositing p-type 1504 On the electrode set.

In some instances, the method for forming grid includes to form electrode filling layer 1506 in work-function layer 1504.Electricity Pole filling layer 1506 may include any suitable material such as metal (such as tungsten, aluminium, tantalum, titanium, nickel, copper, cobalt, or the like), gold Belong to oxide, metal nitride and/or combinations of the above.In one example, electrode filling layer includes tungsten.Electrode filling layer 1506 Deposition method can be any appropriate technology, it is heavy comprising atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor Product, plasma enhanced atomic layer deposition, physical vapour deposition (PVD) and/or combinations of the above.

CMP step can be carried out, to remove electrode material (such as cap rock 1502, function except gate structure 1508 Function layer 1504, electrode filling layer 1506, the material with analog).

In some examples as shown in Figure 16 A to 16C, the method for forming gate structure 1508 includes making gate structure 1508 (such as gate dielectric 1002, cap rock 1502, work-function layer 1504, electrode filling layer 1506 and analog) is partly recessed, and Gate cap 1602 is formed on the gate structure 1508 of recess.Gate cap 1602 may include any suitable material such as dielectric material (oxide of such as semiconductor, the nitride of semiconductor, the nitrogen oxides of semiconductor, the carbide of semiconductor, semiconductor carbon nitrogen Oxide, or the like), polysilicon, spin on glass, tetraethoxy-silicane alkoxide, plasma enhanced oxidation object, height The oxide and/or other suitable materials that depth-to-width ratio processing procedure is formed.In some instances, gate cap 1602 includes carbon nitrogen oxidation Silicon.Gate cap 1602 can have any suitable thickness, and forming method uses any suitable deposition technique such as chemical vapor deposition Product, high density plasma CVD, atomic layer deposition or similar deposition method.In some instances, gate cap 1602 thickness is between about 1nm between about 10nm, and its deposition method is chemical vapor deposition and/or atomic layer deposition system Journey.

According to design, can the aperture in the first interlayer dielectric layer 702, be coupled to source/drain structures 602 to be used to form Contact.Although contact gate structure 1508 is that the docking contact for connecting gate structure 1508 to source/drain structures 602 replaces For object, but contact gate structure 1508 is not precluded in the design using docking contact.As shown in the step 132 of Figure 1B, pattern Change the first interlayer dielectric layer 702 to expose the part of source/drain structures 602.The patterning method of step 132 may include one or Multiple tracks step such as applies photoresist, exposure photoresist, development photoresist, the exposed portion with the first interlayer dielectric layer 702 of etching.It is each this A little processing procedures substantially can be as aforementioned.

As shown in the step 134 and Figure 17 A to 17C of Figure 1B, source/drain polar contact 1702 extends through the first interlayer dielectric Recess in layer 702 with physics and is electrically coupled to source/drain structures 602.In the manner, source/drain polar contact 1702 An other source/drain structures 602 are electrically connected to top conductor, source/drain structures 602 can also electrically connected directly with one another It connects.Source/drain polar contact 1702 may include multiple conductive layers.In this embodiment, the method for formation source/drain polar contact includes Formed metal silicide layer 1703 (such as nickel silicide, nisiloy germanide, or the like) in source/drain structures 602.So One, the deposition method of the metal component of metal silicide layer 1703 can be any appropriate technology, (such as comprising physical vapour deposition (PVD) Sputter), chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, plasma enhanced atomic layer it is heavy Long-pending and/or combinations of the above.Then carry out annealing make metal diffuse to source/drain structures 602 semiconductor material (such as silicon, SiGe, or the like) in.

The step of continuing this can form the adhesion coating 1704 of source/drain polar contact 1702 in metal silicide layer 1703 On.Adhesion coating 1704 can promote wettability, increase adherence and/or avoid spreading, to improve the formation of contact.Adhesion coating 1704 may include metal (such as tungsten, aluminium, tantalum, titanium, nickel, copper, cobalt, or the like), metal nitride, metal oxide, other conjunction Suitable conductive material and/or other suitable sticky materials.The forming method of adhesion coating 1704 can be any suitable processing procedure, packet Containing atomic layer deposition, chemical vapor deposition, low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor Deposition and/or other appropriate technologies.In some instances, adhesion coating 1704 includes titanium or titanium nitride, and forming method can be to adopt It is the atomic layer deposition containing titanium precursor with four (dimethylamino) titaniums.Adhesion coating 1704 can have any suitable thickness.Some In example, adhesion coating 1704 has substantial consistent thickness, between aboutTo aboutBetween.

In the above example, the method that source/drain polar contact 1702 is formed in step 134 includes forming filler 1706 In on adhesion coating 1704.Filler 1706 may include metal, metal nitride, metal oxide and/or other suitably lead Electric material.In a variety of examples, filler 1706 includes copper, cobalt, tungsten and/or combinations of the above.The shape of filler 1706 It can be any suitable processing procedure, including chemical vapor deposition, low-pressure chemical vapor deposition, plasma enhanced chemical vapor at method Deposition, physical vapour deposition (PVD), atomic layer deposition and/or other appropriate technologies.In one example, the deposition side of filler 1706 Method is physical vapour deposition (PVD) circulation staggered with chemical vapor deposition.

As depicted at step 134, the method for forming source/drain polar contact 1702 may include carrying out heat on workpiece 200 to flow again Dynamic processing procedure.It may include thermal annealing that heat flows processing procedure again, to eliminate cavity or the lines in source/drain polar contact 1702.Heat flows again Dynamic processing procedure may include heating workpiece 200 to any suitable temperature.In a variety of examples, workpiece 200 can be heated and arrive about 300 DEG C extremely Between about 500 DEG C.Planarization process can be carried out to remove the source/drain on the top for extending the first interlayer dielectric layer 702 The part of contact 1702.

As shown in the step 136 and Figure 18 A to 18C of Figure 1B, the second interlayer dielectric layer 1802 is formed on workpiece 200.The Two interlayer dielectric layers 1802 are not shown in the top view of Figure 18 A, to avoid other units for blocking workpiece 200.Second interlayer Dielectric layer 1802 can be with the composition of the first interlayer dielectric layer 702 substantially like and may include the dielectric material (oxygen of such as semiconductor Compound, the nitride of semiconductor, the nitrogen oxides of semiconductor, semiconductor carbide, or the like), spin on glass, mix Silicate glass, phosphosilicate glass, boron phosphorus silicate glass, the Black of miscellaneous fluorineIt is xerogel, gas glue, non- Brilliant fluorocarbons, Parylene, benzocyclobutene,And/or combinations of the above.Second interlayer dielectric layer 1802 Forming method can be any suitable processing procedure, including chemical vapor deposition, physical vapour deposition (PVD), rotary coating process and/or other Suitable processing procedure.

It, can be in the second interlayer dielectric layer 1802 and aperture in gate cap 1602, to be used to form the source of being coupled to according to design The contact 2002 of pole/drain contact 1702 and gate structure 1508.As shown in the step 138 and Figure 19 A to 19C of Figure 1B, pattern Change part and gate structure 1508 that the second interlayer dielectric layer 1802 exposes source/drain polar contact 1702 with gate cap 1602 Part.The patterning method of step 138 can include one or more of that steps are as follows: apply photoresist, exposure photoresist, development photoresist, with Etch the exposed portion of the second interlayer dielectric layer 1802 and gate cap 1602.Each processing procedure substantially can be as above-mentioned.

As shown in the step 140 and Figure 20 A to 20C of Figure 1B, contact 2002 is formed with physics and is electrically coupled to source/drain Polar contact 1702 and gate structure 1508.Contact 2002 is not shown in the top view of Figure 20 A, to avoid workpiece 200 is blocked Other units.The method for forming contact 2002 substantially can be such as step 134.In this instance, the method for formation contact 2002 includes Form adhesion coating 2004, and form filler 2006 on adhesion coating 2004, and these nonwoven fabric from filaments substantially can respectively freely before It states.

As shown in the step 142 of Figure 1B, workpiece 200 is provided for subsequent production.In a variety of examples, subsequent production packet Include the rest part to form connection of electric internal connection line structure, cutting, encapsulation and other production processing procedures.

It should be understood that above-mentioned contact gate structure can be used for entire integrated circuit, it includes logic areas, memory block, defeated Enter/output area, with similar area.For example, the illustrative integrated circuit of Fig. 2A to 20C is static random access memory knot Structure, details is as shown in FIG. 20 A, and includes two static random access memories 2008A and 2008B.Above-mentioned memory is respectively Include six transistors: two pull up transistor 2010A and 2010B, two pull-down transistor 2012A and 2012B and two Pass gate transistor 2014A and 2014B.In illustrative example, contact grid 2015A couples the 2010A (N-shaped that pulls up transistor P-type metal oxide semiconductor on well such as doped region 207A pulls up transistor 2010A) source/drain structures to lower crystal pulling Body pipe 2012B (the n-type metal oxide semiconductor pull-down transistor 2012B on p-type well such as doped region 207B) and upper crystal pulling The grid of pipe 2010B (p-type metal oxide semiconductor on N-shaped well such as doped region 207A pull up transistor 2010B), and contact Grid 2015B coupling pull up transistor 2010B source/drain structures to pull-down transistor 2012A (p-type well such as doped region Pull-down transistor 2012A on 207B) with the grid of 2010A of pulling up transistor.It should be noted, however, that contact gate structure is simultaneously It is not limited to storage circuit.

In the above example, the grid part as device grid can include many phases with the grid part as contact Same material.In another example, the electrode of the method for providing integrated circuit and forming integrated circuit, gate structure has first group At first part using the second part as device grid, and with different compositions using as contact.Figure 21 is the present invention In various embodiments, the flow chart with the method 2100 of the workpiece 2200 of contact grid of a variety of compositions is made.In method Before 2100, among, with can carry out additional step later, and the method 2100 of other embodiments is replaceable or omit some steps Suddenly.

Figure 22 A, 23A, 24A, 25A, 26A and 27A are in various embodiments of the present invention, and workpiece 2200 is in the method for production Top view in 2100 a variety of stages.Figure 22 B, 23B, 24B, 25B, 26B and 27B are workpiece in various embodiments of the present invention 2200 in a variety of stages of the method 2100 of production, along the cross-sectional view of gate planar 202.Figure 22 C, 23C, 24C, 25C, 26C and 27C is in various embodiments of the present invention, and workpiece 2200 is in a variety of stages of the method 2100 of production, along fin The cross-sectional view of the plane 204 of length.Figure 22 A to 27C has simplified clearly to illustrate concept of the present invention.It can be integrated in workpiece 2200 Supernumerary structure, and the workpiece 2200 of other embodiments is replaceable or omits some following structures.

As shown in the step 2102 and Figure 22 A to 22C of Figure 21, the workpiece 2200 containing substrate 206, and substrate 206 are received With fin 208, isolation structure 210, grid spacer 402, source/drain structures 602, the first interlayer dielectric layer 702, with Recess 802 is on substrate 206, and boundary layer 902 and gate dielectric 1002 are located in each recess 802.These units essence On can as above-mentioned, and its forming method can be any appropriate technology, the above-mentioned processing procedure of the step 102 comprising Figure 1A to 118.

As shown in the step 2104 and Figure 23 A to 23C of Figure 21, grid is formed on workpiece 2200.This step substantially may be used Such as the step 130 of Figure 1B.However the grid in step 2104 is formed in region (i.e. region of the grid as grid of two kinds of forms With region of the grid as contact) in boundary layer 902 and gate dielectric 1002 on.

Grid may include multiple and different conductive layers.In some instances, the method for forming grid includes forming cap rock 2302 In on workpiece 2200.Cap rock 2302 is formed directly on gate dielectric 1002.

Cap rock 2302 can be with the composition of cap rock 1502 substantially like and may include any suitable conductive material such as metal (such as tungsten, aluminium, tantalum, titanium, nickel, copper, cobalt, or the like), metal nitride and/or metal silicon nitride, and its deposition method can For chemical vapor deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, plasma enhanced atomic layer deposition, object Physical vapor deposition and/or other suitable deposition manufacture process.In various embodiments, cap rock 2302 includes tantalum nitride silicon, nitridation Tantalum and/or titanium nitride.

In some instances, the method for forming grid includes forming one or more work-function layers 2304 on cap rock 2302. Work-function layer 2304 can be with the composition of work-function layer 1504 substantially like and the material of suitable work-function layer 2304 includes n The work function material of type and/or p-type is held depending on the corresponding device form of gate structure 2308.Illustrative p-type work function gold Belong to comprising titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminium, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, other Suitable p-type work function material and/or combinations of the above.Illustrative N-shaped workfunction metal includes titanium, silver, tantalum aluminium, carbonization Tantalum aluminium, TiAlN, tantalum carbide, carbon tantalum nitride, tantalum nitride silicon, manganese, zirconium, other suitable N-shaped work function materials and/or on The combination stated.The deposition method of work-function layer 2304 can for any appropriate technology for example atomic layer deposition, chemical vapor deposition, etc. from Daughter enhances chemical vapor deposition, plasma enhanced atomic layer deposition, physical vapour deposition (PVD) and/or combinations of the above.One In a little examples, since p-type can have different work-function layers 2304 from N-shaped device, the of the work-function layer 2304 of depositing n-type It can avoid being deposited on the electrode of p-type device using dielectric hard mask when one deposition manufacture process, and in the work-function layer of depositing p-type It can avoid being deposited on the electrode of N-shaped device using dielectric hard mask when 2304 the second deposition manufacture process.

In some instances, the method for forming grid includes forming electrode filling layer 2306 in work-function layer 2304.Electricity Pole filling layer 2306 can with electrode filling layer 1506 substantially like, and may include any suitable material such as metal (such as tungsten, Aluminium, tantalum, titanium, nickel, copper, cobalt, or the like), metal oxide, metal nitride and/or combinations of the above.In one example, electric Pole filling layer includes tungsten.The deposition method of electrode filling layer 2306 can be any appropriate technology, include atomic layer deposition, chemical gas Mutually deposition, plasma enhanced chemical vapor deposition, plasma enhanced atomic layer deposition, physical vapour deposition (PVD) and/or above-mentioned Combination.

CMP step can be carried out to remove electrode material (such as cap rock 2302, function except gate structure 2308 Function layer 2304, electrode filling layer 2306, the material with analog).

As shown in the step 2106 and Figure 24 A to 24C of Figure 21, patterned hard mask layer 2402 is formed in workpiece 2200 On, forming method may include forming patterned photoresist layer 2404 on hard mask layer 2402.Hard mask layer 2402 may include Any suitable material.In a variety of examples, hard mask layer 2402 may include dielectric material (oxide, the semiconductor of such as semiconductor Nitride, the nitrogen oxides of semiconductor, the carbide of semiconductor, semiconductor nitrogen oxycarbide, shield analog) and/or its His suitable material.Any suitable processing procedure can be used in the forming method of hard mask layer 2402, includes chemical vapor deposition, high density etc. Ion body chemical vapor phase growing, physical vapour deposition (PVD), atomic layer deposition, spin-on deposition and/or other suitable deposition systems Journey.

Patterning hard mask layer 2402 is to expose gate structure 2308 (such as electrode filling layer 2306, work-function layer 2304, lid Layer 2302, gate dielectric 1002 and/or boundary layer 902) region to be removed, keep the conductive material being subsequently formed electrical Contact fin 208.In one example, the photolithographic processes for patterning hard mask layer 2402 include: forming photoresist layer 2404 in hard Photoresist layer 2404 on mask layer 2402, after lithographic exposure photoresist layer 2404 and development exposure is to expose the hard screening to be removed The part of cap layer 2402.Photolithographic processes substantially can be such as the step 104 of Figure 1A.

After photolithographic processes, the patterning method of step 2106 may include etch process to remove hard mask layer 2402 Exposed portion.Etch process may include any suitable etching technique, for example, wet etching, dry ecthing, reactive ion etching, Ashing and/or other etching methods.Any suitable etchant can be used in etch process, and it includes etchant, the fluorine based on oxygen to be Etchant based on main etchant, chlorine, the etchant based on bromine, the etchant based on iodine, other suitable etchant liquid, Gas or plasma and/or combinations of the above.In one example, etch process includes the erosion for waiting and using to etching technique It carves agent to be set as removing the material of hard mask layer 2402, and does not etch photoresist layer 2404 or adjacent material such as gate spacer substantially Object 402, the first interlayer dielectric layer 702 and gate structure 2308.Etching can expose the part for the gate structure 2308 to be removed.

As Figure 21 step 2108 and Figure 25 A to 25C shown in, from fin 208 remove grid, gate dielectric 1002, With the exposed portion of boundary layer 902, and remove position be after formed conductive material to couple at fin 208.The method can Comprising being etched processing procedure such as wet etching, dry ecthing, reactive ion etching, ashing and/or other etching methods.Etch process Any suitable etchant can be used, it includes the etchant based on oxygen, the etchant based on fluorine, the etchants based on chlorine, bromine Based on etchant, the etchant based on iodine, other suitable etchant liquid, gas or plasmas and/or above-mentioned Combination.In this instance, etch process includes multiple etching step, and the etchant that each step uses is arranged with technology to remove Grid (such as cap rock 2302, work-function layer 2304, electrode filling layer 2306 and analog), gate dielectric 1002 and boundary layer 902 certain material, and insignificantly etch fin 208, source/drain structures 602, hard mask layer 2402, gate spacer Object 402 or other adjacent materials.

As shown in the step 2110 and Figure 25 A to 25C of Figure 21, doping fin 208 will contact the part of grid, to reduce Resistance between contact grid and adjacent source/drain structures 602.The doped region 1402 of fin 208 substantially can be as above It states.In some instances, using ion disposing process doping fin 208 doped region 1402, and its admixture species with it is adjacent Source/drain structures 602 in admixture have same modality (such as N-shaped or p-type), therefore the form of doped region 1402 and remaining Fin 208 form it is opposite.In these examples that source/drain structures 602 include p-doping such as boron, fin 208 Doped region 1402 it is doped with comprising boron (such as boron -11, boron difluoride, or the like), indium or other p-dopings.In source Pole/drain electrode structure 602 includes in N-shaped admixture such as these examples of phosphorus or arsenic, and the doped region 1402 of fin 208 is doped with packet Phosphorous, arsenic and/or other N-shaped admixtures.Doped region 1402 can be doped into any suitable dopant concentration.In a variety of examples, mix The dopant concentration in miscellaneous area 1402 is between about 1 × 10¹⁴Atom/cm²To 5 × 10¹⁵Atom/cm²Between.Hard mask layer 2402 and/or Photoresist layer 2404 can be used as implant mask, make remaining fin 208 from being adulterated by admixture species.

As shown in the step 2112 and Figure 26 A to 26C of Figure 21, the contact areas 2602 of grid is formed on workpiece 2200.Such as Shown in name, contact areas 2602 is formed in grid as in the region of contact.Contact areas 2602 and the other parts of grid can have Different compositions and/or material.

Contact areas 2602 may include multiple and different conductive layers.In some instances, the method for formation contact areas 2602 includes Boundary layer 2604 is formed on workpiece 2200.Boundary layer 2604 is formed directly in grid as the fin in the region of contact In 208 upper horizontal surface and vertical sidewall surface.To reduce resistance, fin 208 will not be along the length direction of fin Extend through entire grid.This can provide additional vertical surface in fin end, i.e. (such as its interface of contact areas 2602 Layer) it physics and can be electrically coupled at fin 208.

Boundary layer 2604 may include any suitable conductive material such as metal (such as tungsten, aluminium, tantalum, titanium, nickel, copper, cobalt or Analog), metal nitride and/or metal silicon nitride compound, and its deposition method can be chemical vapor deposition, atomic layer deposition Product, plasma enhanced chemical vapor deposition, plasma enhanced atomic layer deposition, physical vapour deposition (PVD) and/or other are suitable Deposition manufacture process.In a variety of examples, boundary layer 2604 includes titanium, cobalt or nickel, be can be used for and the semiconductor of fin 208 Interface forms silicide, to reduce interface resistance.In these examples, annealing system is carried out after deposited interfacial layer 2604 Journey, to form silication interface.

Other conductive layers can be formed on boundary layer 2604.For example, electrode filling layer 2606 can be formed in boundary layer On 2604.Electrode filling layer 2606 may include any suitable material such as metal (such as tungsten, aluminium, tantalum, titanium, nickel, copper, cobalt or similar Object), metal oxide, metal nitride and/or combinations of the above.In one example, electrode filling layer includes tungsten.Electrode filling The deposition method of layer 2606 can be any appropriate technology, include atomic layer deposition, chemical vapor deposition, plasma enhanced chemical Vapor deposition, plasma enhanced atomic layer deposition, physical vapour deposition (PVD) and/or combinations of the above.

CMP step can be carried out, to remove gate structure 2308 along hard mask layer 2402 and photoresist layer 2404 Outer excess stock (such as material of boundary layer 2604 and/or electrode filling layer 2606).

In some instances, processing procedure includes to make gate structure 2308 (such as gate dielectric 1002, lid containing contact areas 2602 Layer 2302, work-function layer 2304, electrode filling layer 2306, boundary layer 2604, electrode filling layer 2606 and analog) recess, and Gate cap 1602 is formed on the gate structure 2308 of recess.Gate cap 1602 can be with preceding substantially like and may include Any suitable material such as dielectric material (oxide of such as semiconductor, the nitride of semiconductor, semiconductor nitrogen oxides, partly lead The carbide of body, semiconductor carbon nitrogen oxide, or the like), polysilicon, spin on glass, tetraethoxy-silicane alkoxide The oxide and/or other suitable materials that object, plasma enhanced oxidation object, high-aspect-ratio processing procedure are formed.In some examples In, gate cap 1602 includes carbon silicon oxynitride.Gate cap 1602 can have any suitable thickness, and forming method can be used any Suitable deposition techniques such as chemical vapor deposition, high density plasma CVD, atomic layer deposition or similar deposition side Method.In some embodiments, the thickness of gate cap 1602 is between about 1nm between about 10nm, and its deposition method is chemical gas Mutually deposition and/or atomic layer deposition processing procedure.Gate cap 1602 is not shown in the top view of Figure 26 A, to avoid workpiece is blocked 2200 other units.

As shown in the step 2114 of Figure 21, the processing procedure of the step 132 to 142 of Figure 1B can be carried out on workpiece 2200.To scheme For 26A to 26C, the first interlayer dielectric layer 702 is patterned to expose the part of source/drain structures 602, and formed and extended through The source/drain polar contact 1702 of the first interlayer dielectric layer 702 is crossed, with physics and is electrically coupled to source/drain structures 602.Such as Shown in Figure 27 A to 27C, form the second interlayer dielectric layer 1802 on workpiece 2200, the second interlayer dielectric layer of patterning 1802 with Gate cap 1602 forms contact 2002 to expose the part and the part of gate structure 2308 of source/drain polar contact 1702 with object Source/drain polar contact 1702 and gate structure 2308 are managed and be electrically coupled to, and provides workpiece 2200 for follow-up process.This A little processing procedures and Individual cells substantially can be as above-mentioned.

In the above example, it is formed after the grid part as device grid, just forms the grid part as contact. In another example, before forming grid part, it is initially formed the contact portions of grid.

Figure 28 is to make the method with the workpiece 2900 of contact grid of a variety of compositions in various embodiments of the present invention 2800 flow chart.Before method 2800, among, with can carry out additional step, and the method 2800 of other embodiments later The replaceable or some steps of omission.

Figure 29 A, 30A, 31A, 32A, 33A and 34A are in various embodiments of the present invention, and workpiece 2900 is in the method for production Top view in 2800 a variety of stages.Figure 29 B, 30B, 31B, 32B, 33B and 34B are workpiece in various embodiments of the present invention 2900 in a variety of stages of the method 2800 of production, along the cross-sectional view of gate planar 202.Figure 29 C, 30C, 31C, 32C, 33C and 34C is in various embodiments of the present invention, and workpiece 2900 is in a variety of stages of the method 2800 of production, along fin The cross-sectional view of the plane 204 of length.Figure 29 A to 34C has simplified clearly to illustrate concept of the present invention.It can be integrated in workpiece 2900 Supernumerary structure, and the workpiece 2900 of other embodiments is replaceable or omits some following structures.

As shown in the step 2802 and Figure 29 A to 29C of Figure 28, the workpiece 2900 containing substrate 206, and substrate 206 are received With fin 208, isolation structure 210, occupy-place grid 302, grid spacer 402, source/drain structures 602 and first layer Between dielectric layer 702 on substrate 206.These units substantially can be as above-mentioned, and its forming method can be any appropriate technology, packet The above-mentioned processing procedure of step 102 containing Figure 1A to 112.

As shown in the step 2804 and Figure 30 A to 30C of Figure 28, patterned hard mask layer 3002 is formed in workpiece 2900 On, and the above method may include forming patterned photoresist layer 3004 on hard mask layer 3002.Hard mask layer 3002 may include Any suitable material.In a variety of examples, hard mask layer 3002 includes dielectric material (such as the oxide of semiconductor, semiconductor Nitride, the nitrogen oxides of semiconductor, the carbide of semiconductor, semiconductor carbon nitrogen oxide, or the like) and/or other Suitable material.Any suitable processing procedure can be used in the forming method of hard mask layer 3002, comprising chemical vapor deposition, high density etc. from Daughter chemical vapor deposition, physical vapour deposition (PVD), atomic layer deposition, spin-on deposition and/or other what suitable deposition systems Journey.

Hard mask layer 3002 is patterned to expose the region to be removed of occupy-place grid 302, the conductive material formed after being allowed to It can fin 208 in electrical contact.It in one example, include: to form photoresist layer in the photolithographic processes of patterning hard mask layer 3002 3004 on hard mask layer 3002, and lithographic exposes photoresist layer 3004, and the photoresist layer 3004 of development exposure is intended to remove to expose Hard mask layer 3002 part.Photolithographic processes substantially can be such as the step 104 of Figure 1A.

After photolithographic processes, the patterning method of step 2804 may include etch process, to remove hard mask layer 3002 exposed portion.Etch process may include any suitable etching technique, such as wet etching, dry ecthing, reactive ion Etching, ashing and/or other engraving methods.Any suitable etchant can be used in etch process, and it includes the etchings based on oxygen The etchant based on etchant, chlorine based on agent, fluorine, the etchant based on bromine, the etchant based on iodine, other suitable etchings Agent liquid, gas or plasma and/or combinations of the above.In one example, etch process includes to wait to etching technique, is adopted Etchant is set as removing the material of hard mask layer 3002, and does not substantially etch photoresist layer 3004 or adjacent material such as accounts for Position grid 302, grid spacer 402 and the first interlayer dielectric layer 702.Etching can expose the occupy-place grid material 304 to be removed Part.

As shown in the step 2806 and Figure 31 A to 31C of Figure 28, the exposing of occupy-place grid material 304 is removed from fin 208 Part, and remove the conductive material formed after position is and be coupled at fin 208.The method includes to be etched processing procedure such as Wet etching, dry ecthing, reactive ion etching, ashing and/or other engraving methods.Etch process can be used any suitable Etchant, it includes the etchant based on oxygen, the etchant based on fluorine, the etchant based on chlorine, the etchant based on bromine, iodine to be Main etchant, other suitable etchant liquid, gas or plasmas and/or combinations of the above.In this instance, it etches Etchant that processing procedure uses and technology are arranged to remove occupy-place grid material 304, and insignificantly remove fin 208, source electrode/ Drain electrode structure 602, hard mask layer 3002, grid spacer 402 or other adjacent materials.

As shown in the step 2808 and Figure 31 A to 31C of step 28, doping fin 208 will contact the part of grid, with drop Resistance between low contact grid and adjacent source/drain structures 602.The doped region 1402 of fin 208 substantially can be such as It is above-mentioned.In some instances, the doped region 1402 of fin 208, and its admixture species and phase are adulterated using ion disposing process Admixture in adjacent source/drain structures 602 has same modality (such as N-shaped or p-type), thus the form of doped region 1402 and its The form of remaining fin 208 is opposite.In these examples that source/drain structures 602 include p-doping such as boron, fin 208 doped region 1402 it is doped with comprising boron (such as boron -11, boron difluoride, or the like), indium or other p-dopings.In Source/drain structures 602 include in these examples of N-shaped admixture such as phosphorus or arsenic, the doped region 1402 of fin 208 it is doped with Include phosphorus, arsenic and/or other N-shaped admixtures.Doped region 1402 can be doped into any suitable dopant concentration.In a variety of examples, The dopant concentration of doped region 1402 is between about 1 × 10¹⁴Atom/cm²To 5 × 10¹⁵Atom/cm²Between.Hard mask layer 3002 and/ Or photoresist layer 3004 can be used as implant mask, protect the rest part of fin 208 from admixture object species complexity.

As shown in the step 2810 and Figure 32 A to 32C of Figure 28, the contact areas 2602 of grid is formed on workpiece 2900.It connects The region that point area 2602 is formed is grid as junction, can with foregoing teachings substantially like.

Contact areas 2602 may include multiple and different conductive layers.In some instances, the method for formation contact areas 2602 includes Boundary layer 2604 is formed on workpiece 2900.Boundary layer 2604 is formed directly in grid as the fin in the region of contact In 208 upper horizontal surface and vertical sidewall surface.To reduce resistance, fin 208 will not be along the length direction of fin Extend through entire grid.This can provide additional vertical surface in fin end, i.e. (such as its interface of contact areas 2602 Layer) it physics and can be electrically coupled at fin 208.

Boundary layer 2604 may include any suitable conductive material such as metal (example without tungsten, aluminium, tantalum, titanium, nickel, copper, cobalt or Analog), metal nitride and/or metal silicon nitride compound, and its deposition method can be chemical vapor deposition, atomic layer deposition Product, plasma enhanced chemical vapor deposition, plasma enhanced atomic layer deposition, physical vapour deposition (PVD) and/or other are suitable Deposition manufacture process.In a variety of examples, boundary layer 2604 includes titanium, cobalt or nickel, can (such as fin 208 is partly led with semiconductor Body) silicide is formed in interface, to reduce interface resistance.In this instance, annealing system is carried out after deposited interfacial layer 2604 Journey, to form silicide interface.

Other conductive layers can be formed on boundary layer 2604.For example, electrode filling layer 2606 can be formed in boundary layer On 2604.Electrode filling layer 2606 may include any suitable material such as metal (such as tungsten, aluminium, tantalum, titanium, nickel, copper, cobalt or similar Object), metal oxide, metal nitride and/or combinations of the above.In one example, electrode filling layer includes tungsten.Electrode filling The deposition method of layer 2606 can be any appropriate technology, include atomic layer deposition, chemical vapor deposition, plasma enhanced chemical Vapor deposition, plasma enhanced atomic layer deposition, physical vapour deposition (PVD) and/or combinations of the above.

Chemical mechanical grinding can be carried out, to remove the outer of gate structure 2308 along hard mask layer 3002 and photoresist layer 3004 Excess stock (such as boundary layer 2604 and/or electrode filling layer 2606).

As shown in the step 2812 and Figure 33 A to 33C of Figure 28, the rest part of occupy-place grid 302 is removed.This step essence On can be such as the step 114 of Figure 1A.The step of removing occupy-place grid material 304 may include one or more etch process (such as wet etching, Dry ecthing or reactive ion etching), the etchant that uses is arranged to be etched selectively to occupy-place grid material 304, without Significantly etch adjacent material such as fin 208, source/drain structures 602, grid spacer 402, the first interlayer dielectric layer 702, the contact areas 2602 of grid, and the like.

As shown in the step 2814 and Figure 33 A to 33C of Figure 28, the rest part of grid is formed on workpiece 2900.It is above-mentioned Step substantially can be such as the step 130 of Figure 1B and/or the step 2104 of Figure 21.

Grid may include multiple and different conductive layer.In some instances, the method for forming grid includes forming cap rock 2302 on workpiece 2900.Cap rock 2302 is formed directly on gate dielectric 1002.

Cap rock 2302 can be with the composition of cap rock 1502 substantially like and may include suitable conductive material such as metal (example As tungsten, aluminium, tantalum, titanium, nickel, copper, cobalt, or the like), metal nitride and/or metal silicon nitride compound, and its deposition method Can for chemical vapor deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, plasma enhanced atomic layer deposition, Physical vapour deposition (PVD) and/or other suitable deposition manufacture process.In various embodiments, cap rock 2302 includes tantalum nitride silicon, nitridation Tantalum and/or titanium nitride.

In some instances, the method for forming grid includes forming one or more work-function layers 2304 on cap rock 2302. Work-function layer 2304 can be with the composition of work-function layer 1504 substantially like and the material of suitable work-function layer 2304 includes n The work function material of type and/or p-type is held depending on the corresponding device type of gate structure 2308.Illustrative p-type work function gold Belong to comprising titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminium, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, other Suitable p-type work function material and/or combinations of the above.Illustrative N-shaped workfunction metal includes titanium, silver, tantalum aluminium, carbonization Tantalum aluminium, TiAlN, tantalum carbide, carbon tantalum nitride, tantalum nitride silicon, manganese, zirconium, other suitable N-shaped work function materials and/or on The combination stated.The deposition method of work-function layer 2304 can for any appropriate technology for example atomic layer deposition, chemical vapor deposition, etc. from Daughter enhances chemical vapor deposition, plasma enhanced atomic layer deposition, physical vapour deposition (PVD) and/or combinations of the above.One In a little examples, since p-type can have different work-function layers 2304 from N-shaped device, the of the work-function layer 2304 of depositing n-type It can avoid being deposited on the electrode of p-type device using dielectric hard mask when one deposition manufacture process, and in the work-function layer of depositing p-type It can avoid being deposited on the electrode of N-shaped device using dielectric hard mask when 2304 the second deposition manufacture process.

In some instances, the method for forming grid includes forming electrode filling layer 2306 in work-function layer 2304.Electricity Pole filling layer 2306 can with electrode filling layer 1506 substantially like, and may include any suitable material such as metal (such as tungsten, Aluminium, tantalum titanium, nickel, copper, cobalt, or the like), metal oxide, metal nitride and/or combinations of the above.In one example, electric Pole filling layer includes tungsten.The deposition method of electrode filling layer 2306 can be any appropriate technology such as atomic layer deposition, chemical gaseous phase Deposition, plasma enhanced chemical vapor deposition, plasma enhanced atomic layer deposition, physical vapour deposition (PVD) and/or above-mentioned Combination.

Chemical mechanical grinding can be carried out to remove electrode material (such as cap rock 2302, work function except gate structure 2308 Layer 2304, electrode filling layer 2306 and analog).

In some instances, processing procedure includes to make gate structure 2308 (such as gate dielectric 1002, cap rock containing contact areas 2302, work-function layer 2304, electrode filling layer 2306, boundary layer 2604, electrode filling layer 2606 and analog) material it is recessed It falls into, and forms gate cap 1602 on the gate structure 2308 of recess.Gate cap 1602 can be with preceding substantially like and can Comprising any suitable material such as dielectric material (oxide of such as semiconductor, the nitride of semiconductor, semiconductor nitrogen oxides, The carbide of semiconductor, semiconductor carbon nitrogen oxide, or the like), polysilicon, spin on glass, tetraethoxysilane The oxide and/or other suitable materials that oxide, plasma enhanced oxidation object, high-aspect-ratio processing procedure are formed.In some examples In son, gate cap 1602 includes carbon silicon oxynitride.Gate cap 1602 can have any suitable thickness, and forming method, which can be used, appoints What suitable deposition technique such as chemical vapor deposition, high density plasma CVD, atomic layer deposition or similar heavy Product.In some instances, the thickness of gate cap 1602 is between about 1nm between about 10nm, and its deposition method can be chemical gas Mutually deposition and/or atomic layer deposition processing procedure.Gate cap 1602 is not shown in Figure 33 A, to avoid other for blocking workpiece 2900 Unit.

As shown in the step 2816 of Figure 28, the step 132 of Figure 1B can be carried out on workpiece 2900 to 142.Extremely with Figure 33 A For 33C, the first interlayer dielectric layer 702 is patterned to expose the part of source/drain structures 602, and form source/drain and connect Point 1702 extends through the first interlayer dielectric layer 702, with physics and is electrically coupled to source/drain structures 602.Extremely such as Figure 34 A Shown in 34C, the second interlayer dielectric layer 1802 is formed on workpiece 2900, patterns the second interlayer dielectric layer 1802 and gate cap 1602 to expose the part and the part of gate structure 2308 of source/drain polar contact 1702, and formed contact 2002 with physics with It is electrically coupled to source/drain polar contact 1702 and gate structure 2308, and provides workpiece 2900 to be used for follow-up process.These systems Journey and Individual cells can be substantially such as above contents.

Therefore the present invention provides the integrated circuit with contact gate structure and forms the example of the method for integrated circuit.In In some examples, IC apparatus includes: memory comprising multiple fins；And gate structure, extend fin The first fin and the second fin on.Gate structure includes grid, and the first fin is physically contacted；And gate dielectric Layer, between grid and the second fin.In some instances, the first fin includes source/drain regions and physical contact The doped region of grid；Source/drain regions include the first admixture of the first form；And doped region includes the second of the first form mixing Matter.In some instances, third admixture of remaining first fin comprising the second form, and the second form and the first form phase Instead.In some instances, physical gate contacts upper surface and the both side surface of the first fin.In some instances, grid prolongs It stretches beyond the first fin in fin-shaped length direction, the end surface of the first fin is further physically contacted.In this example In, memory includes the first drawing upwardly device, the second drawing upwardly device, the first pull device, the second pull device, the first pass gate dress It sets, be formed on fin with the second pass gate device.Grid extends on the first pull device and the first drawing upwardly device, and physics The first fin is contacted to be coupled to the source/drain structures of the second drawing upwardly device.In this instance, gate structure is first grid Structure and grid are first grid.In this instance, IC apparatus further includes second grid structure, it includes second grid It extends on the second pull device and the second drawing upwardly device, and the second fin is physically contacted to be coupled to the first drawing upwardly device Source/drain structures.In some instances, interface of the silicide between grid and the first fin.In these examples, The first part of the grid of the first fin is physically contacted, has not with the second part for extending the grid on the second fin With composition.

In other examples, device includes the first transistor, is located on the first fin；And second transistor, it is located at On second fin.The first part of grid is located on the first fin, is located on the second fin with the second part of gate pole, Wherein second transistor includes that gate dielectric is located between the second part and the second fin of grid；And the first of grid Part physical contacts the first fin, to couple the first transistor to second transistor.In some instances, grid electric property coupling The source/drain structures of the first transistor on to the first fin.In these examples, grid is mixed via the first fin Miscellaneous area is electrically coupled to the source/drain structures of the first transistor.In these examples, doped region includes mixing for the first form Matter, and source/drain structures include the admixture of the first form.In these examples, remaining first fin includes the second shape The admixture of state, and the second form is opposite with the first form.In these examples, physical gate contacts and surrounds the first fin Fin end surface.In these examples, the first transistor is the first p-type metal oxygen of static random access memory memory Compound semiconductor drawing upwardly device, and be located on N-shaped well.In these examples, second transistor is deposited for static random access memory Second p-type metal oxide semiconductor drawing upwardly device of reservoir, and be located on N-shaped well.

In other examples, method includes receiving workpiece comprising multiple fins of substrate and self-reference substrate extension.It is formed Gate dielectric is on the channel region of fin；Gate dielectric is removed from the region of the first fin of fin, without certainly Second fin of fin removes gate dielectric；And grid is formed to be physically contacted the first fin, and grid and the Two fins are separated with gate dielectric.It include: to be formed from the step of the first fin removal gate dielectric in these examples Hard mask is on gate dielectric；Hard mask is patterned to expose a part of the gate dielectric on the first fin；And It using hard mask and is etched, to remove the exposed portion of gate dielectric from the first fin.In these examples, also wrap Include a part using hard mask and the first fin of implant.

The feature of above-described embodiment is conducive to technician in the art and understands the disclosure.Technology in the art Personnel should be understood that the disclosure, which can be used, makees basis, designs and change other processing procedures and complete with structure the identical mesh of above-described embodiment And/or same advantage.Technician in the art it should also be understood that these equivalent replacements without departing from disclosure spirit with Range, and can be changed, replace or change under the premise of without departing from the spirit and scope of the disclosure.