阅读说明：本技术 电平转换电路 (Level shifting circuit ) 是由 浦珺慧 于 2019-09-30 设计创作，主要内容包括：本发明公开了一种电平转换电路,包括：第一NMOS源极接地,漏极接第三NMOS源极,栅极作为第一低压输入端；第二NMOS源极接地,漏极接第四NMOS源极,栅极作为第二低压输入端；第三NMOS漏极接第二PMOS栅极、第三PMOS漏极和第一迟滞反馈电路输入端并作为第一高压输出端,栅极接中等电压偏置电位；第四NMOS漏极接第一PMOS栅极、第四PMOS漏极和第二迟滞反馈电路输入端并作为第二高压输出端,栅极接中等电压偏置电位；第一PMOS源极接高压电源,漏极接第三PMOS源极；第二PMOS源极接高压电源,漏极接第四PMOS源极；第三PMOS栅极接第一迟滞反馈电路输出端；第四PMOS栅极接第二迟滞反馈电路输出端；第一～第四NMOS体区接地,第一～第四PMOS接高压电源。本发明能在接近器件阈值电压情况下正常工作。(The invention discloses a kind of level shifting circuits, comprising: the first NMOS source ground connection, drain electrode connect third NMOS source, and grid is as the first low pressure, input end；Second NMOS source ground connection, drain electrode connect the 4th NMOS source, and grid is as the second low pressure, input end；3rd NMOS drain electrode connects the 2nd PMOS grid, the 3rd PMOS drain electrode and the first lagging feedback circuit input end and as the first high-voltage output end, and grid connects medium voltate bias potential；4th NMOS drain electrode connects the first PMOS grid, the 4th PMOS drain electrode and the second lagging feedback circuit input end and as the second high-voltage output end, and grid connects medium voltate bias potential；First pmos source connects high voltage power supply, and drain electrode connects third pmos source；Second pmos source connects high voltage power supply, and drain electrode connects the 4th pmos source；3rd PMOS grid connects the first lagging feedback circuit output end；4th PMOS grid connects the second lagging feedback circuit output end；First~the 4th NMOS body area ground connection, the first~the 4th PMOS connect high voltage power supply.The present invention can work normally close to device threshold voltage.)

1. a kind of level shifting circuit characterized by comprising

First NMOS transistor (MN1), source electrode are grounded (VSS), drain electrode connection third NMOS transistor (MN3) source electrode, Grid connects third NMOS transistor (MN3) grid as the first low pressure, input end (I)；

Second NMOS transistor (MN2), source electrode are grounded (VSS), drain electrode the 4th NMOS transistor (MN4) source electrode of connection, Grid connects the 4th NMOS transistor (MN4) grid as the second low pressure, input end (IN)；

Third NMOS transistor (MN3), drain electrode connection the second PMOS transistor (MP2) grid, third PMOS transistor (MP3) Drain electrode is with the first lagging feedback circuit (A) input terminal and as the first high-voltage output end (Z)；

4th NMOS transistor (MN4), drain electrode connection the first PMOS transistor (MP1) grid, the 4th PMOS transistor (MP4) Drain electrode is with the second lagging feedback circuit (B) input terminal and as the second high-voltage output end (ZN)；

First PMOS transistor (MP1), source electrode connect high voltage power supply (VCCH), drain electrode connection third PMOS transistor (MP3) source electrode；

Second PMOS transistor (MP2), source electrode connect high voltage power supply (VCCH), drain electrode the 4th PMOS transistor of connection (MP4) source electrode；

Third PMOS transistor (MP3), grid connect first lagging feedback circuit (A) output end (FBZ)；

4th PMOS transistor (MP4), grid connect second lagging feedback circuit (B) output end (FBZN)；

First~the 4th NMOS transistor (MN1~MN4) body area is grounded (VSS), the first~the 4th PMOS transistor (MP1~ MP4 high voltage power supply (VCCH)) is met.

2. level shifting circuit as described in claim 1, it is characterised in that:

First NMOS transistor (MN1) and the second NMOS transistor (MN2) are low voltage nmos transistors；

Third NMOS transistor (MN3) and the 4th NMOS transistor (MN4) are zero threshold NMOS transistors of high pressure；

First~the 4th PMOS transistor (MP1~MP4) is high voltage PMOS transistor.

3. level shifting circuit as described in claim 1, it is characterised in that:

First NMOS transistor (NM1) and third NMOS transistor (NM3), which are realized, realizes level drop-down to the first high-voltage output end；

Second NMOS transistor (NM2) and the 4th NMOS transistor (NM4), which are realized, realizes level drop-down to the second high-voltage output end；

First PMOS transistor (MP1) and third PMOS transistor (MP3), which are realized, realizes level pull-up to the first high-voltage output end；

Second PMOS transistor (MP2) and the 4th PMOS transistor (MP4), which are realized, realizes level pull-up to the second high-voltage output end.

4. level shifting circuit as described in claim 1, it is characterised in that:

First NMOS transistor (MN1), grid is as the first low pressure, input end (I)；

Second NMOS transistor (MN2), grid as the second low pressure, input end (IN),

Third NMOS transistor (MN3), grid connect medium voltate bias potential (VBN)；

4th NMOS transistor (MN4), grid connect medium voltate bias potential (VBN).

5. level shifting circuit as claimed in claim 4, it is characterised in that:

First NMOS transistor (MN1) and the second NMOS transistor (MN2) are low voltage nmos transistors；

Third NMOS transistor (MN3) and the 4th NMOS transistor (MN4) are High voltage NMOS transistors；

First~the 4th PMOS transistor (MP1~MP4) is high voltage PMOS transistor.

6. level shifting circuit as described in claim 1, it is characterised in that: the first lagging feedback circuit (A) includes that first is anti- Phase device (IN1), first input end connect first high-voltage output end of level shifting circuit (Z), and the connection of the second input terminal is high Voltage source (VCCH), third input end grounding (VSS), output end connect the second phase inverter (IN2) first input end；

Second phase inverter (IN2), the second input terminal connect high voltage power supply (VCCH), and third input end grounding (VSS) is defeated Outlet connects the 5th NMOS transistor (NM5) source electrode；

5th NMOS transistor (NM5), grid connect high voltage power supply (VCCH), and drain electrode is used as the first lagging feedback circuit (A) output end (FBZ).

7. level shifting circuit as described in claim 1, it is characterised in that: the second lagging feedback circuit (B) includes that third is anti- Phase device (IN3), first input end connect the second high-voltage output end of level shifting circuit (ZN), and the second input terminal connects high pressure Power supply (VCCH), third input end grounding (VSS), output end connect the 4th phase inverter (IN4) first input end；

4th phase inverter (IN4), the second input terminal connect high voltage power supply (VCCH), and third input end grounding (VSS) is defeated Outlet connects the 6th NMOS transistor (NM6) source electrode；

6th NMOS transistor (NM6), grid connect high voltage power supply (VCCH), and drain electrode is used as the second lagging feedback circuit (B) output end (FBZN).

Technical field

The present invention relates to integrated circuit fields, more particularly to a kind of level shifting circuit.

Background technique

Level shifting circuit includes high voltage level conversion circuit and low voltage level conversion circuit, and wherein high voltage level conversion is electric Low-voltage control signal is converted to high voltage control signal by road, realizes control of the low voltage logic to high-voltage power output stage.In general, root According to the output polar difference of high voltage control signal, level shifting circuit can be divided into negative pressure level shifting circuit and positive pressure level conversion Circuit.Traditional level shifting circuit is made of four high voltage transistors.Two high voltage PMOS pipes are for pulling up, two high pressures NMOS tube is for pulling down.Two input terminals of the grid of two high pressure NMOSs as level shifting circuit, input terminal voltage are low Voltage potential.Two output ends of the drain electrode of two high voltage PMOS pipes as level shifting circuit, output end voltage is high voltage Current potential.Since two high pressure NMOS pipes work in low voltage situations, causes the pull-down capability of two high pressure NMOS pipes very weak, work as low pressure When value is as low as a certain degree, level shifting circuit can not work, namely cannot achieve the function of level conversion.

Summary of the invention

The technical problem to be solved in the present invention is to provide it is a kind of can under the low voltage situations close to device threshold voltage it is normal The level shifting circuit of work.

In order to solve the above technical problems, level shifting circuit provided by the invention, comprising:

First NMOS transistor MN1, source electrode are grounded VSS, drain electrode connection third NMOS transistor MN3 source electrode, grid Pole connects third NMOS transistor MN3 grid as the first low pressure, input end I；

Second NMOS transistor MN2, source electrode are grounded VSS, drain electrode the 4th NMOS transistor MN4 source electrode of connection, grid Pole connects the 4th NMOS transistor MN4 grid as the second low pressure, input end IN, and logical value is opposite with the end I；

Third NMOS transistor MN3, the second PMOS transistor MP2 grid of drain electrode connection, third PMOS transistor MP3 leakage Pole and the first lagging feedback circuit A input terminal and as the first high-voltage output end Z, logical output values are identical as the end I；

4th NMOS transistor MN4, the first PMOS transistor MP1 grid of drain electrode connection, the 4th PMOS transistor MP4 leakage Pole and the second lagging feedback circuit B input terminal and as the second high-voltage output end ZN, logical output values are opposite with Z；

First PMOS transistor MP1, source electrode connect high voltage power supply VCCH, drain electrode connection third PMOS transistor MP3 Source electrode；

Second PMOS transistor MP2, source electrode connect high voltage power supply VCCH, the 4th PMOS transistor MP4 of drain electrode connection Source electrode；

Third PMOS transistor MP3, grid connect the first lagging feedback circuit A output end FBZ；

4th PMOS transistor MP4, grid connect the second lagging feedback circuit B output end FBZN；

First~the 4th NMOS transistor MN1~MN4 body area is grounded VSS, the first~the 4th PMOS transistor MP1~MP4 Meet high voltage power supply VCCH.

Wherein, the first NMOS transistor MN1 and the second NMOS transistor MN2 is low voltage nmos transistor；

Third NMOS transistor MN3 and the 4th NMOS transistor MN4 is zero threshold NMOS transistor of high pressure；

First~the 4th PMOS transistor MP1~MP4 is high voltage PMOS transistor.

Wherein, the first NMOS transistor MN1 and third NMOS transistor MN3, which is realized, realizes level to the first high-voltage output end Drop-down；

Second NMOS transistor MN2 and the 4th NMOS transistor MN4, which is realized, realizes level drop-down to the second high-voltage output end；

First PMOS transistor MP1 and third PMOS transistor MP3, which is realized, realizes level pull-up to the first high-voltage output end；

Second PMOS transistor MP2 and the 4th PMOS transistor MP4, which is realized, realizes level pull-up to the second high-voltage output end.

The present invention provides another level shifting circuit, comprising:

First NMOS transistor MN1, source electrode are grounded VSS, drain electrode connection third NMOS transistor MN3 source electrode, grid Pole is as the first low pressure, input end I；

Second NMOS transistor MN2, source electrode are grounded VSS, drain electrode the 4th NMOS transistor MN4 source electrode of connection, grid Pole is as the second low pressure, input end IN；

Third NMOS transistor MN3, the second PMOS transistor MP2 grid of drain electrode connection, third PMOS transistor MP3 leakage Pole and the first lagging feedback circuit A input terminal and as the first high-voltage output end Z, grid connects medium voltate bias potential VBN；

4th NMOS transistor MN4, the first PMOS transistor MP1 grid of drain electrode connection, the 4th PMOS transistor MP4 leakage Pole and the second lagging feedback circuit B input terminal and as the second high-voltage output end ZN, grid connects medium voltate bias potential VBN；

First PMOS transistor MP1, source electrode connect high voltage power supply VCCH, drain electrode connection third PMOS transistor MP3 Source electrode；

Second PMOS transistor MP2, source electrode connect high voltage power supply VCCH, the 4th PMOS transistor MP4 of drain electrode connection Source electrode；

Third PMOS transistor MP3, grid connect the first lagging feedback circuit A output end FBZ；

4th PMOS transistor MP4, grid connect the second lagging feedback circuit B output end FBZN；

First~the 4th NMOS transistor MN1~MN4 body area is grounded VSS, the first~the 4th PMOS transistor MP1~MP4 Meet high voltage power supply VCCH.

Wherein, the first NMOS transistor MN1 and the second NMOS transistor MN2 is low voltage nmos transistor；

Third NMOS transistor MN3 and the 4th NMOS transistor MN4 is High voltage NMOS transistor；

First~the 4th PMOS transistor MP1~MP4 is high voltage PMOS transistor.

Wherein, the first NMOS transistor MN1 and third NMOS transistor MN3, which is realized, realizes level to the first high-voltage output end Drop-down；

Second NMOS transistor MN2 and the 4th NMOS transistor MN4, which is realized, realizes level drop-down to the second high-voltage output end；

First PMOS transistor MP1 and third PMOS transistor MP3, which is realized, realizes level pull-up to the first high-voltage output end；

Second PMOS transistor MP2 and the 4th PMOS transistor MP4, which is realized, realizes level pull-up to the second high-voltage output end.

The present invention provides one kind the first lagging feedback circuit A, including

First phase inverter IN1, for first input end as the level shifting circuit the first high-voltage output end Z, second is defeated Enter end connection high voltage power supply VCCH, third input end grounding VSS, output end connects the second phase inverter IN2 first input end；

Second phase inverter IN2, the second input terminal connect high voltage power supply VCCH, third input end grounding VSS, output The 5th NMOS transistor NM5 source electrode of end connection；

5th NMOS transistor NM5, grid connect high voltage power supply VCCH, and drain electrode is used as the first lagging feedback circuit A output end FBZ.

The present invention provides one kind the second lagging feedback circuit B, including

Third phase inverter IN3, for first input end as the level shifting circuit the second high-voltage output end ZN, second is defeated Enter end connection high voltage power supply VCCH, third input end grounding VSS, output end connects the 4th phase inverter IN4 first input end；

4th phase inverter IN4, the second input terminal connect high voltage power supply VCCH, third input end grounding VSS, output The 6th NMOS transistor NM6 source electrode of end connection；

6th NMOS transistor NM6, grid connect high voltage power supply VCCH, and drain electrode is used as the second lagging feedback circuit B output end FBZN.

The first design (with reference to shown in Fig. 2) of the present invention, utilizes the first NMOS transistor (low pressure NMOS) and the 3rd NMOS Transistor (zero threshold value of high pressure

NMOS it) realizes and level drop-down is realized to the first high-voltage output end；Second NMOS transistor (low pressure NMOS) and the 4th NMOS transistor (zero threshold value NMOS of high pressure), which is realized, realizes level drop-down to the second high-voltage output end；First PMOS transistor is (high Press PMOS) and third PMOS transistor (high voltage PMOS) realize to the first high-voltage output end realize level pull up；2nd PMOS is brilliant Body pipe (high voltage PMOS) and the 4th PMOS transistor (high voltage PMOS), which are realized, realizes level pull-up to the second high-voltage output end.First The input of the grid of NMOS transistor (low pressure NMOS) and the second NMOS transistor (low pressure NMOS) is low-voltage；3rd NMOS crystal The grid input for managing (zero threshold value NMOS of high pressure) and the 4th NMOS transistor (zero threshold value NMOS of high pressure) is medium bias voltage；The The grid of three PMOS transistors (high voltage PMOS) and four PMOS transistors (high voltage PMOS) connects lagging feedback circuit.The present invention can have Effect improves level conversion ability, so that level shifting circuit is worked under the low voltage situations close to device threshold voltage, helps In the low power dissipation design for realizing integrated circuit.

Second of design of the present invention (with reference to shown in Fig. 3), utilizes the first NMOS transistor (low pressure NMOS) and the 3rd NMOS Transistor (high pressure NMOS), which is realized, realizes level drop-down to the first high-voltage output end；Second NMOS transistor (low pressure NMOS) and Four NMOS transistors (high pressure NMOS), which are realized, realizes level drop-down to the second high-voltage output end；First PMOS transistor (high pressure PMOS it) realizes and level pull-up is realized to the first high-voltage output end with third PMOS transistor (high voltage PMOS)；2nd PMOS crystal It manages (high voltage PMOS) and the 4th PMOS transistor (high voltage PMOS) is realized and realizes level pull-up to the second high-voltage output end.First The input of the grid of NMOS transistor (low pressure NMOS) and the second NMOS transistor (low pressure NMOS) is low-voltage；3rd NMOS crystal The grid input for managing (high pressure NMOS) and the second NMOS transistor (high pressure NMOS) is medium bias voltage, makes the first NMOS crystal (low pressure NMOS) and the work of the second NMOS transistor (low pressure NMOS) are managed under medium bias voltage, guarantees device reliability；The The grid of three PMOS transistors (high voltage PMOS) and four PMOS transistors (high voltage PMOS) connects lagging feedback circuit, can overcome high pressure NMOS tube works in low voltage situations, and the pull-down capability of two high pressure NMOS pipes is very weak, the defect that level shifting circuit can not work. The present invention is effectively improved level conversion ability, allows level shifting circuit work under the low voltage situations close to device threshold voltage Make, helps to realize the low power dissipation design of integrated circuit.

Detailed description of the invention

Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

Fig. 1 is a kind of structural schematic diagram of existing level shifting circuit.

Fig. 2 is the structural schematic diagram of first embodiment of the invention.

Fig. 3 is the structural schematic diagram of second embodiment of the invention.

Fig. 4 is the structural schematic diagram of the first lagging feedback circuit of the invention.

Fig. 5 is the structural schematic diagram of the second lagging feedback circuit of the invention.

Description of symbols

NM1~NM6 is the first~the 6th NMOS

MP1~MP4 is the first~the 4th PMOS

Z is first high-voltage output end of level shifting circuit

ZN is second high-voltage output end of level shifting circuit

FBZ is the first lagging feedback circuit output end

FBZN is the second lagging feedback circuit output end

A is the first lagging feedback circuit

B is the second lagging feedback circuit

VBN is medium voltate bias potential

VCCH is high voltage power supply

First phase inverter~the 4th phase inverter IN1~IN4.

Specific embodiment

Illustrate embodiments of the present invention below by way of particular specific embodiment, those skilled in the art can be by this explanation Book disclosure of that is fully understood from other advantages and technical effect of the invention.The present invention can also be by different specific Embodiment is embodied or practiced, and the various details in this specification can also be applied based on different viewpoints, is not having Various modifications or alterations are carried out under total mentality of designing away from inventing.It should be noted that in the absence of conflict, implementing below Feature in example and embodiment can be combined with each other.The application classifies by general knowledge known in this field, and low voltage mos transistor refers to 1V-40V, high-voltage MOS transistor refer to 400V-1000V.

As shown in Fig. 2, level shifting circuit first embodiment provided by the invention, comprising:

First NMOS transistor MN1, source electrode are grounded VSS, drain electrode connection third NMOS transistor MN3 source electrode, grid Pole connects third NMOS transistor MN3 grid as the first low pressure, input end I；

Second NMOS transistor MN2, source electrode are grounded VSS, drain electrode the 4th NMOS transistor MN4 source electrode of connection, grid Pole connects the 4th NMOS transistor MN4 grid as the second low pressure, input end IN,

Third NMOS transistor MN3, the second PMOS transistor MP2 grid of drain electrode connection, third PMOS transistor MP3 leakage Pole and the first lagging feedback circuit A input terminal and as the first high-voltage output end Z；

4th NMOS transistor MN4, the first PMOS transistor MP1 grid of drain electrode connection, the 4th PMOS transistor MP4 leakage Pole and the second lagging feedback circuit B input terminal and as the second high-voltage output end ZN；

First PMOS transistor MP1, source electrode connect high voltage power supply VCCH, drain electrode connection third PMOS transistor MP3 Source electrode；

Second PMOS transistor MP2, source electrode connect high voltage power supply VCCH, the 4th PMOS transistor MP4 of drain electrode connection Source electrode；

Third PMOS transistor MP3, grid connect the first lagging feedback circuit A output end FBZ；

4th PMOS transistor MP4, grid connect the second lagging feedback circuit B output end FBZN；

First~the 4th NMOS transistor MN1~MN4 body area is grounded VSS, the first~the 4th PMOS transistor MP1~MP4 Meet high voltage power supply VCCH.

Wherein, the first NMOS transistor MN1 and the second NMOS transistor MN2 is low voltage nmos transistor；

Third NMOS transistor MN3 and the 4th NMOS transistor MN4 is zero threshold NMOS transistor of high pressure；

The first~the 4th PMOS transistor MP1~MP4 of 4th NMOS transistor MN4 is high voltage PMOS transistor.

First NMOS transistor MN1 and third NMOS transistor MN3, which is realized, realizes level drop-down to the first high-voltage output end；

Second NMOS transistor MN2 and the 4th NMOS transistor MN4, which is realized, realizes level drop-down to the second high-voltage output end；

First PMOS transistor MP1 and third PMOS transistor MP3, which is realized, realizes level pull-up to the first high-voltage output end；

Second PMOS transistor MP2 and the 4th PMOS transistor MP4, which is realized, realizes level pull-up to the second high-voltage output end.

As shown in figure 3, the present invention provides level shifting circuit second embodiment, comprising:

First NMOS transistor MN1, source electrode are grounded VSS, drain electrode connection third NMOS transistor MN3 source electrode, grid Pole is as the first low pressure, input end I；

Second NMOS transistor MN2, source electrode are grounded VSS, drain electrode the 4th NMOS transistor MN4 source electrode of connection, grid Pole is as the second low pressure, input end IN；

Third NMOS transistor MN3, the second PMOS transistor MP2 grid of drain electrode connection, third PMOS transistor MP3 leakage Pole and the first lagging feedback circuit A input terminal and as the first high-voltage output end Z, grid connects medium voltate bias potential VBN；

4th NMOS transistor MN4, the first PMOS transistor MP1 grid of drain electrode connection, the 4th PMOS transistor MP4 leakage Pole and the second lagging feedback circuit B input terminal and as the second high-voltage output end ZN, grid connects medium voltate bias potential VBN；

First PMOS transistor MP1, source electrode connect high voltage power supply VCCH, drain electrode connection third PMOS transistor MP3 Source electrode；

Second PMOS transistor MP2, source electrode connect high voltage power supply VCCH, the 4th PMOS transistor MP4 of drain electrode connection Source electrode；

Third PMOS transistor MP3, grid connect the first lagging feedback circuit A output end FBZ；

4th PMOS transistor MP4, grid connect the second lagging feedback circuit B output end FBZN；

First~the 4th NMOS transistor MN1~MN4 body area is grounded VSS, the first~the 4th PMOS transistor MP1~MP4 Meet high voltage power supply VCCH.

Wherein, the first NMOS transistor MN1 and the second NMOS transistor MN2 is low voltage nmos transistor；

Third NMOS transistor MN3 and the 4th NMOS transistor MN4 is High voltage NMOS transistor；

First~the 4th PMOS transistor MP1~MP4 is high voltage PMOS transistor.

First NMOS transistor MN1 and third NMOS transistor MN3, which is realized, realizes level drop-down to the first high-voltage output end；

Second NMOS transistor MN2 and the 4th NMOS transistor MN4, which is realized, realizes level drop-down to the second high-voltage output end；

First PMOS transistor MP1 and third PMOS transistor MP3, which is realized, realizes level pull-up to the first high-voltage output end；

Second PMOS transistor MP2 and the 4th PMOS transistor MP4, which is realized, realizes level pull-up to the second high-voltage output end.

As shown in figure 4, the present invention provides one kind mono- embodiment of the first lagging feedback circuit A, including

First phase inverter IN1, for first input end as the level shifting circuit the first high-voltage output end Z, second is defeated Enter end connection high voltage power supply VCCH, third input end grounding VSS, output end connects the second phase inverter IN2 first input end；

Second phase inverter IN2, the second input terminal connect high voltage power supply VCCH, third input end grounding VSS, output The 5th NMOS transistor NM5 source electrode of end connection；

5th NMOS transistor NM5, grid connect high voltage power supply VCCH, and drain electrode is used as the first lagging feedback circuit A output end FBZ.

As shown in figure 5, the present invention provides mono- embodiment of the second lagging feedback circuit B, including

Third phase inverter IN3, for first input end as the level shifting circuit the second high-voltage output end ZN, second is defeated Enter end connection high voltage power supply VCCH, third input end grounding VSS, output end connects the 4th phase inverter IN4 first input end；

4th phase inverter IN4, the second input terminal connect high voltage power supply VCCH, third input end grounding VSS, output The 6th NMOS transistor NM6 source electrode of end connection；

6th NMOS transistor NM6, grid connect high voltage power supply VCCH, and drain electrode is used as the second lagging feedback circuit B output end FBZN.

Above by specific embodiment and embodiment, invention is explained in detail, but these are not composition pair Limitation of the invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change Into these also should be regarded as protection scope of the present invention.