阅读说明：本技术 存储装置 (Storage device ) 是由 伊东干彦 小柳胜 中谷真史 奥野晋也 长坂繁辉 吉原正浩 梅泽明 筑山慧至 河崎一茂 于 2017-03-23 设计创作，主要内容包括：实施方式的存储装置包含：第1存储芯片,包含第1电路、第1及第2端子；第2存储芯片,包含第2电路及第3端子；及接口芯片,包含第1及第2电压产生电路。所述第2存储芯片设置在所述第1存储芯片上方,所述接口芯片设置在所述第1存储芯片下方。所述第1端子的第1端部连接到所述第1电路,所述第1端子的第2端部连接到所述第1电压产生电路。所述第2端子的第3端部连接到所述第3端子,所述第2端子的第4端部连接到所述第2电压产生电路。所述第3端子的第5端部连接到所述第2电路,所述第3端子的第6端部经由所述第2端子连接到所述第2电压产生电路。在相对于所述第1存储芯片的表面垂直的方向上,所述第3端部不与所述第4端部重叠,所述第3端部与所述第6端部重叠。(The storage device of embodiment includes: the 1st storage chip, includes the terminal of the 1st circuit, the 1st and the 2nd；2nd storage chip includes the 2nd circuit and the 3rd terminal；And interface chip, it include the 1st and the 2nd voltage generation circuit.2nd storage chip is arranged above the 1st storage chip, and the interface chip is arranged below the 1st storage chip.1st end of the 1st terminal is connected to the 1st circuit, and the 2nd end of the 1st terminal is connected to the 1st voltage generation circuit.3rd end of the 2nd terminal is connected to the 3rd terminal, and the 4th end of the 2nd terminal is connected to the 2nd voltage generation circuit.5th end of the 3rd terminal is connected to the 2nd circuit, and the 6th end of the 3rd terminal is connected to the 2nd voltage generation circuit via the 2nd terminal.On the vertical direction in the surface relative to the 1st storage chip, the 3rd end is not Chong Die with the 4th end, and the 3rd end is Chong Die with the 6th end.)

1. a kind of storage device, has:

1st storage chip includes the 1st circuit, the 1st terminal and the 2nd terminal；

2nd storage chip includes the 2nd circuit and the 3rd terminal；And

Interface chip includes the 1st voltage generation circuit and the 2nd voltage generation circuit；

The top of the 1st storage chip is arranged in 2nd storage chip,

The lower section of the 1st storage chip is arranged in the interface chip,

1st end of the 1st terminal is electrically connected to the 1st circuit, and the 2nd end of the 1st terminal is electrically connected to described 1st voltage generation circuit,

3rd end of the 2nd terminal is electrically connected to the 3rd terminal, and the 4th end of the 2nd terminal is electrically connected to described 2nd voltage generation circuit,

5th end of the 3rd terminal is electrically connected to the 2nd circuit, and the 6th end of the 3rd terminal is via the 2nd end Son is electrically connected to the 2nd voltage generation circuit,

On the vertical direction in the surface relative to the 1st storage chip, the 3rd end is not Chong Die with the 4th end, And the 3rd end is Chong Die with the 6th end.

2. storage device according to claim 1, wherein

The interface chip further includes the imput output circuit of data,

The imput output circuit is arranged in the 1st region of the interface chip,

1st and the 2nd voltage generation circuit is arranged in the 2nd region of the interface chip,

The 3rd region is set between the 1st region and the 2nd region,

3rd region is electrically separated by the 1st region and the 2nd region.

3. storage device according to claim 2, wherein

The imput output circuit is electrically connected to the 1st power supply via the 1st wiring,

1st and the 2nd voltage generation circuit is electrically connected to the 2nd power supply via the 2nd wiring,

1st wiring and the 2nd wiring are electrically separated.

4. storage device according to claim 1, wherein

2nd storage chip further includes the 4th terminal,

1st terminal is adjacent with the 1st circuit,

2nd terminal and the 1st terminal are electrically separated,

3rd terminal is adjacent with the 2nd circuit,

4th terminal and the 3rd terminal are electrically separated,

The structure of 2nd storage chip is identical as the structure of the 1st storage chip.

5. storage device according to claim 1, more standby:

The 3rd storage chip above 2nd storage chip is set,

1st storage chip further includes 5th terminal electrically separated with the 1st and the 2nd terminal,

2nd storage chip further includes 6th terminal electrically separated with the 3rd terminal,

The interface chip further includes the 3rd voltage generation circuit,

3rd storage chip includes the 3rd circuit and is electrically connected to the 7th terminal of the 3rd circuit,

7th terminal is electrically connected to the 3rd voltage generation circuit via the described 5th and the 6th terminal.

6. a kind of storage device, has:

M (natural number that M is 2 or more) storage core circuits；

Voltage is supplied to the M storage core circuit by 1 or more voltage generation circuit；And

Control circuit controls the operation of the voltage generation circuit；

The M storage core circuit respectively can be by the 1st signal corresponding with the voltage supply from the voltage generation circuit It is output to the control circuit,

From described M store core circuit in it is N number of (N be less than M and be 1 or more natural number) storage core circuit it is each In the case that the 1st signal among is output to the control circuit, the control circuit is so as to store described M The mode of the voltage supply delay of remaining storage core circuit in core circuit, controls the movement of the voltage generation circuit.

7. storage device according to claim 6, wherein

It is described in the case where stopping the 1st storage core circuit output 1 signal in the M storage core circuit Control circuit is in a manner of starting to supply the voltage to the 2nd storage core circuit in remaining described storage core circuit, control Make the voltage generation circuit.

8. storage device according to claim 7, wherein

The 2nd storage core circuit exports the 1st signal after being supplied to the voltage.

9. storage device according to claim 6, wherein

The M storage core circuit respectively contains depositing with the one end for being connected to the grid of wordline and being connected to source electrode line Storage unit,

1st signal is at least one generated with the electric current in the voltage application to the wordline and the source electrode line Kind situation accordingly exports.

10. a kind of storage device, has:

Core circuit is stored, comprising the 1st driving circuit for sending the 1st data and exports expression the 1st driving circuit 1st circuit of the 1st signal of state；And

Interface circuit receives circuit comprising the 1st for receiving the 1st data；And output indicates that the described 1st receives circuit 2nd circuit of the 2nd signal of state；

In the case where sending the interface circuit from the storage core circuit for the 1st data,

The storage core circuit in order to indicate the 1st driving circuit be initiate mode, and by the signal of the 1st signal electricity It is flat to be set as the 1st level,

1st signal of the interface circuit based on the 1st level, receiving circuit configuration for the described 1st is initiate mode.

11. storage device according to claim 10, wherein

In order to indicate that the described 1st receives circuit as initiate mode, the signal level of the 2nd signal is set as the 1st electricity It is flat.

12. storage device according to claim 10, wherein

The interface circuit further includes the 2nd driving circuit for sending the 2nd data to the storage core circuit, and described the The state of 2 driving circuits indicates by the 2nd signal,

Before the 1st signal is set as the 1st level,

In order to indicate that the 2nd driving circuit is non-enabled state, the interface circuit sets the signal level of the 2nd signal It is set to 2nd level different from the 1st level,

Storage 2nd signal of the core circuit based on the 2nd level, the 1st driving circuit is set as enabling State.

13. storage device according to claim 12, wherein

In the case where sending the storage core circuit from the interface circuit for the 2nd data,

2nd driving circuit is set as opening by the interface circuit based on the 1st signal for being set as the 2nd level With state,

The interface circuit in order to indicate the 2nd driving circuit be initiate mode and the signal level of the 2nd signal is set It is set to the 1st level.

14. storage device according to claim 13, wherein

The storage core circuit is after the 1st driving circuit is set to non-enabled state, by the signal of the 1st signal Level is set as the 2nd level.

15. storage device according to claim 10, wherein

1st driving circuit is controlled based on the 1st control signal from the 1st circuit,

The 1st reception circuit is controlled based on the 2nd control signal from the 2nd circuit,

2nd signal of 1st circuit based on 2nd level different from the 1st level, by the 1st control signal Signal level be set as the 1st level,

1st driving circuit is set to initiate mode based on the 1st control signal of the 1st level,

The signal level of the 2nd control signal is set as by 1st signal of the 2nd circuit based on the 1st level 1st level,

The 1st reception circuit is set to the initiate mode based on the 2nd control signal of the 1st level.

16. a kind of storage device, has: interface chip；

1st storage chip is arranged above the interface chip, comprising the 1st circuit, is electrically connected to the 1st logical of the 1st circuit Road and 2nd channel non-electric-connecting with the 1st channel；And

2nd storage chip, setting connect above the 1st storage chip described, comprising the 2nd circuit and are electrically connected to the 2nd circuit The 3rd channel；

The interface chip includes:

Control circuit controls write-in, deletion and the reading to the 1st and the 2nd storage chip according to input signal；

1st voltage generation circuit, comprising be electrically connected to via the 1st channel the 1st circuit the 1st voltage booster, And the 2nd voltage booster of the 2nd circuit is electrically connected to via the 2nd channel and the 3rd channel；And

1st convex block is electrically connected the 1st voltage generation circuit and the 1st power supply；And

2nd convex block, it is non-electric-connecting with the 1st convex block, and it is electrically connected the control circuit and the 2nd power supply.

17. storage device according to claim 16, wherein

1st to the 3rd channel is silicon perforation.

18. storage device according to claim 16, wherein

The interface chip further includes the 2nd voltage generation circuit for being electrically connected to the 2nd convex block,

1st storage chip further includes the 4th channel for being electrically connected the 1st circuit and the 2nd voltage generation circuit,

2nd storage chip, which is further included, is electrically connected the 2nd circuit and the 2nd voltage generation electricity via the 4th channel 5th channel on road.

19. storage device according to claim 18, wherein

4th and the 5th channel is silicon perforation.

20. storage device according to claim 18, wherein

The 1st region of the interface chip is arranged in the control circuit and the 2nd voltage generation circuit,

The 2nd region of the interface chip is arranged in 1st voltage generation circuit,

The 3rd region is set between the 1st region and the 2nd region,

3rd region is electrically separated by the 1st region and the 2nd region.

21. storage device according to claim 20, wherein

3rd region from the 1st end setting made of the surface and the 1st side as the interface chip to by the surface and 2nd end made of the 2nd side with the 1st side opposite direction.

22. storage device according to claim 16, wherein

1st end in the 1st channel is electrically connected to the 1st circuit, and the 2nd end in the 1st channel is electrically connected to described 1st voltage booster,

3rd end in the 2nd channel is electrically connected to the 3rd channel, and the 4th end in the 2nd channel is electrically connected to described 2nd voltage booster,

5th end in the 3rd channel is electrically connected to the 2nd circuit, and the 6th end in the 3rd channel is logical via the described 2nd Road is electrically connected to the 2nd voltage booster,

On the vertical direction in the surface relative to the 1st storage chip, the 3rd end is not Chong Die with the 4th end, 3rd end is Chong Die with the 6th end.

23. storage device according to claim 20, wherein

1st storage chip further includes the 3rd voltage generation circuit for being electrically connected to the 1st voltage generation circuit,

2nd storage chip further includes the 4th voltage generation circuit for being electrically connected to the 1st voltage generation circuit,

The interface chip further includes the 1st clock production for sending clock signals to the voltage generation circuit of the described 1st, the 3rd and the 4th Raw circuit,

1st clock generation circuit is arranged in the 1st region.

24. storage device according to claim 23, wherein

1st storage chip further includes the 2nd clock generation circuit for being connected to the 3rd voltage generation circuit,

2nd storage chip further includes the 3rd clock generation circuit for being connected to the 4th voltage generation circuit.

25. a kind of storage device, has:

Interface chip has the 1st interarea, comprising the 1st voltage generation circuit and is arranged in the 1st interarea and is electrically connected to institute State the 1st terminal of the 1st voltage generation circuit；

The top of the interface chip is arranged in 1st storage chip, has 2nd interarea and institute opposite with the 1st interarea The 3rd interarea of the 2nd interarea opposite side is stated, and includes setting in the 2nd interarea and via the 1st convex block and the 1st terminal electricity 2nd terminal of connection and the 3rd terminal that the 3rd interarea is set；

The top of the 1st storage chip is arranged in 2nd storage chip, has 4th interarea opposite with the 3rd interarea, and Include the 4th terminal that the 4th interarea is set and is electrically connected via the 2nd convex block with the 3rd terminal；

1st sealing material is arranged in a manner of connecting with the 2nd region in the 1st region of the 1st interarea and the 2nd interarea Between the interface chip and the 1st storage chip, and filler is not included；And

2nd sealing material does not include the 3rd region of the 1st interarea in the 1st region and not comprising the described 2nd comprising filling The 4th of 2nd interarea in region is interregional, and fills the filler between the 3rd interarea and the 4th interarea.

26. storage device according to claim 25, wherein

The pyroconductivity of 1st sealing material is lower than the 2nd sealing material.

27. storage device according to claim 25, wherein

The 1st interarea of the interface chip includes: inside the 1st voltage generation circuit setting to the interface chip The 5th region and not set 1st voltage generation circuit the 6th region,

5th region includes the 1st region, and the 6th region does not include the 1st region.

28. storage device according to claim 27, wherein

1st storage device includes the 2nd voltage generation circuit,

The 2nd interarea of 1st storage chip includes: by the 2nd voltage generation circuit setting to the 1st storage core 8th region in the 7th region and not set 2nd voltage generation circuit inside piece,

7th region does not include the 2nd region, and the 8th region includes the 2nd region.

Technical field

Embodiments of the present invention are related to a kind of storage device.

Background technique

Flash memory is used for various electronic devices.

[background technology document]

[patent document]

[patent document 1] Japanese Patent Laid-Open 2009-3991 bulletin

No. 4791924 specifications of [patent document 2] Japanese Patent No.

No. 5814859 specifications of [patent document 3] Japanese Patent No.

Summary of the invention

[problem to be solved by the invention]

Reduce the manufacturing cost of storage device.

[technical means to solve problem]

Detailed description of the invention

Fig. 1 is the schematic diagram of the storage system comprising storage device.

Fig. 2 is the block diagram for indicating the Inner Constitution of storage device.

Fig. 3 is the cross-sectional view for indicating the structural example of storage device.

Fig. 4 is the cross-sectional view for indicating the structural example of storage device of the 1st embodiment.

Fig. 5 is the schematic diagram for indicating the structural example of storage device of the 1st embodiment.

Fig. 6 is the top view for indicating the structural example of storage device of the 1st embodiment.

Fig. 7 is the schematic diagram for indicating the structural example of storage device of the 2nd embodiment.

Fig. 8 is the top view for indicating the structural example of storage device of the 2nd embodiment.

Fig. 9 is the schematic diagram for illustrating the storage device of the 3rd embodiment.

Figure 10 is the timing diagram for indicating the action example of storage device of the 3rd embodiment.

Figure 11 is the schematic diagram for illustrating the storage device of the 3rd embodiment.

Figure 12 is the schematic diagram for illustrating the storage device of the 4th embodiment.

Figure 13 is the equivalent circuit diagram for indicating the configuration example of storage device of the 4th embodiment.

Figure 14 is the timing diagram for indicating the action example of storage device of the 4th embodiment.

Figure 15 is the schematic diagram for the action example for illustrating the storage device of the 4th embodiment.

Figure 16 is the schematic diagram for the action example for illustrating the storage device of the 4th embodiment.

Figure 17 is the schematic diagram for the action example for illustrating the storage device of the 4th embodiment.

Figure 18 is the schematic diagram for the action example for illustrating the storage device of the 4th embodiment.

Figure 19 is the schematic diagram for the action example for illustrating the storage device of the 4th embodiment.

Figure 20 is the equivalent circuit diagram for indicating the configuration example of storage device of the 5th embodiment.

Figure 21 is the equivalent circuit diagram for indicating the configuration example of storage device of the 5th embodiment.

Figure 22 is the top view for indicating the interface chip of the configuration example of storage device of the 6th embodiment.

Figure 23 is the top view for indicating the storage core chips of the configuration example of storage device of the 6th embodiment.

Figure 24 is the schematic diagram for illustrating the storage device of the 6th embodiment.

Figure 25 is the cross-sectional view for indicating the configuration example of storage device of the 7th embodiment.

Figure 26 is the top view for indicating the interface chip of the configuration example of storage device of the 7th embodiment.

Figure 27 is the cross-sectional view for indicating the configuration example of storage device of the 8th embodiment.

Figure 28 is the top view for indicating the interface chip of the configuration example of storage device of the 8th embodiment.

The storage device of embodiment includes: the 1st storage chip, includes the 1st circuit, the 1st terminal and the 2nd terminal；2nd deposits Chip is stored up, includes the 2nd circuit and the 3rd terminal；And interface chip, electricity is generated comprising the 1st voltage generation circuit and the 2nd voltage Road.The top of the 1st storage chip is arranged in 2nd storage chip, and the interface chip setting is in the 1st storage core The lower section of piece.1st end of the 1st terminal is electrically connected to the 1st circuit, and the 2nd end of the 1st terminal is electrically connected to 1st voltage generation circuit.3rd end of the 2nd terminal is electrically connected to the 3rd terminal, and the 4th of the 2nd terminal the End is electrically connected to the 2nd voltage generation circuit.5th end of the 3rd terminal is electrically connected to the 2nd circuit, described 6th end of the 3rd terminal is electrically connected to the 2nd voltage generation circuit via the 2nd terminal.It is deposited relative to the described 1st It stores up on the vertical direction in surface of chip, the 3rd end is not Chong Die with the 4th end, and the 3rd end and described the The overlapping of 6 ends.