阅读说明：本技术 具有带单元的半导体器件 (Semiconductor devices with tape cell ) 是由 罗国鸿 张峰铭 郭盈秀 王屏薇 于 2019-05-24 设计创作，主要内容包括：提供了具有带单元的半导体器件,半导体器件包括第一阱,具有第一导电类型并且沿着第一方向延伸；第二阱和第三阱,具有第二导电类型并且在第二方向上设置在第一阱的相对侧上；位单元的第一阵列和位单元的第二阵列,设置在第一阱至第三阱上方；带单元,设置在第一阱至第三阱上并且设置在第一阵列和第二阵列之间,包括第一阱拾取区域和第二阱拾取区域,具有第一带电类型,设置在第一阱上,在第一方向上彼此分隔开,以及第三阱拾取区域和第四阱拾取区域,具有第二导电类型并且分别设置在第二阱和第三阱上；第一导电图案和第二导电图案,分别电连接至第一阱拾取区域和第二阱拾取区域；以及第三导电图案,电连接至第三阱拾取区域和第四阱拾取区域。(The semiconductor devices with tape cell is provided, semiconductor devices includes the first trap, has the first conduction type and extends along a first direction；Second trap and third trap have the second conduction type and are arranged on the opposite side of the first trap in a second direction；First array of bit location and the second array of bit location are arranged above the first trap to third trap；Tape cell, it is arranged on the first trap to third trap and is arranged between the first array and second array, including the first trap picking region and the second trap picking region, with the first electrification type, it is arranged on the first trap, separated from one another in a first direction and third trap picking region and the 4th trap picking region have the second conduction type and are separately positioned on the second trap and third trap；First conductive pattern and the second conductive pattern are respectively electrically connected to the first trap picking region and the second trap picking region；And third conductive pattern, it is electrically connected to third trap picking region and the 4th trap picking region.)

1. a kind of semiconductor devices, comprising:

First trap has the first conduction type and extends along a first direction；

The opposite side of first trap is arranged in the second conduction type and in a second direction in second trap and third trap On；

First array of bit location and the second array of bit location are arranged above first trap to the third trap；

Tape cell is arranged above first trap to the third trap and is arranged in first array and second gust described Between column, the tape cell includes:

First trap picking region and the second trap picking region have first conduction type and are arranged on first trap Side and separated from one another in said first direction, the doping of first trap picking region and second trap picking region Concentration is greater than the doping concentration of first trap；And

Third trap picking region and the 4th trap picking region have second conductive-type different from first conduction type Type, and be separately positioned on above second trap and the third trap, and separated from one another in this second direction, institute The doping concentration for stating third trap picking region and the 4th trap picking region is greater than mixing for second trap and the third trap Miscellaneous concentration；

First conductive pattern and the second conductive pattern, are respectively electrically connected to first trap picking region and second trap picks up Region and extend above first trap picking region and second trap picking region；And

Third conductive pattern is electrically connected to third trap picking region and the 4th trap picking region and in the third Extend above trap picking region and the 4th trap picking region.

2. semiconductor devices according to claim 1, wherein third trap picking region and the 4th trap pick-up area The width of each of domain in said first direction is greater than in first trap picking region and second trap picking region Each of width in said first direction.

3. semiconductor devices according to claim 1, further comprises:

First power supply pattern extends along a first direction above first array, the tape cell and the second array, And it is electrically connected to first conductive pattern and second conductive pattern；And

Second source pattern and third power supply pattern, above first array, the tape cell and the second array Extend along a first direction, and is electrically connected to the third conductive pattern.

4. semiconductor devices according to claim 3, wherein

First power supply pattern is arranged between the second source pattern and the third power supply pattern and is electrically connected to described The source region of the first transistor and second transistor of first array and the bit location of the second array, wherein described The source region of one transistor and the second transistor has second conduction type；

Second source pattern is electrically connected to the source electrode of the third transistor of the bit location of first array and the second array Region, wherein the source region of the third transistor has first conduction type；And

Third power supply pattern is electrically connected to the source electrode of the 4th transistor of the bit location of first array and the second array Region, wherein the source region of the 4th transistor has first conduction type.

5. semiconductor devices according to claim 4, further comprises:

First bit line extends above first array, the tape cell and the second array along the first direction, And it is electrically connected to the source region of the 5th transistor of the bit location of first array and the second array, wherein institute The source region for stating the 5th transistor has second conduction type；And

Second bit line extends above first array, the tape cell and the second array along the first direction, And it is electrically connected to the source region of the 6th transistor of the bit location of first array and the second array, wherein institute The source region for stating the 6th transistor has second conduction type.

6. semiconductor devices according to claim 1, further comprises:

Gate electrode layer extends in first array and the second array along the second direction；And

Pseudo- gate electrode layer extends in the tape cell along the second direction,

Wherein, the gate electrode layer and the pseudo- gate electrode layer are arranged in same level and are manufactured from the same material.

7. semiconductor devices according to claim 6, wherein the puppet gate electrode layer further comprises:

Multiple first pseudo- gate electrode layers, extend above first trap picking region；

Multiple second pseudo- gate electrode layers, extend above second trap picking region；And

Multiple third puppet gate electrode layers extend above third trap picking region and the 4th trap picking region, and

Each of the multiple third puppet gate electrode layer, setting is in the described first pseudo- gate electrode layer and the second pseudo- gate electrode Between layer.

8. semiconductor devices according to claim 6, wherein it is described puppet gate electrode layer include:

First pseudo- gate electrode layer, extends above first trap picking region；

Second pseudo- gate electrode layer, extends above second trap picking region；And

Third puppet gate electrode layer extends above third trap picking region and the 4th trap picking region, and

4th pseudo- gate electrode layer, setting are picked up in first trap picking region and third trap picking region and the 4th trap It takes between region；And

5th pseudo- gate electrode layer, setting are picked up in second trap picking region and third trap picking region and the 4th trap It takes between region.

9. a kind of semiconductor devices, comprising:

First trap and the second trap have the first conduction type and separated from one another in a first direction；

Third trap has the second conduction type different from first conduction type, and including being arranged in first trap With on the side of second trap first part, be arranged on the other side of first trap and second trap second Point and the first part and the second part are connected to each other and be arranged in first trap and second trap it Between Part III；

First array of bit location is arranged in above first part and the second part of first trap and the third trap；

The second array of bit location is arranged in above first part and the second part of second trap and the third trap；

Tape cell, be arranged above first trap, second trap and the third trap and be arranged in first array and Between the second array, the tape cell includes:

First trap picking region and the second trap picking region have first conduction type, are separately positioned on first trap Above second trap, and separated from one another in said first direction, first trap picking region and described second The doping concentration of trap picking region is greater than the doping concentration of first trap and second trap；And

Third trap picking region has second conduction type, is arranged above the third trap and is arranged described the Between one trap picking region and second trap picking region, the doping concentration of third trap picking region is greater than the third The doping concentration of trap；

First conductive pattern and the second conductive pattern are electrically connected to first trap picking region and second trap pick-up area Domain, and extend above first trap picking region and second trap picking region respectively；And

Third conductive pattern is electrically connected to third trap picking region, and extends above third trap picking region.

10. a kind of semiconductor devices, comprising:

First trap and the second trap have the first conduction type, and separated from one another in a first direction；

Third trap has the second conduction type different from first conduction type, and including being arranged in first trap With on the side of second trap first part, be arranged on the other side of first trap and second trap second Divide and the first part and the second part are connected to each other and are separated from each other first trap and second trap Part III；

Bit location is arranged in above first part and the second part of first trap and the third trap；

Tape cell is arranged above first trap, second trap and the third trap, and the tape cell includes:

First trap picking region and the second trap picking region have first conduction type, are separately positioned on first trap Above second trap, and separated from one another in said first direction, first trap picking region and described second The doping concentration of trap picking region is greater than the doping concentration of first trap and second trap；And

Third trap picking region has second conduction type, is arranged above the third trap and is arranged described the Between one trap picking region and second trap picking region, the doping concentration of third trap picking region is greater than the third The doping concentration of trap；

First conductive pattern and the second conductive pattern are connected to first trap picking region and second trap picking region, And extend above first trap picking region and second trap picking region respectively；And

Third conductive pattern is electrically connected to third trap picking region, and extends above third trap picking region,

Wherein, institute's bitcell is provided only on the side of the tape cell.

Technical field

The embodiment of the present invention is generally related to technical field of semiconductors, more particularly, to partly leading with tape cell Body device.

Background technique

In the semiconductor devices of such as static random access memory (SRAM), multiple bit locations or multiple bit locations Array extends in a column direction, and tape cell is arranged between the array of multiple bit locations or multiple bit locations and including being formed in Trap picking region in trap.Tape cell is for voltage pick-up and provides trap bias, to prevent the voltage drop along column direction It falls.

Summary of the invention

According to an aspect of the present invention, a kind of semiconductor devices is provided, comprising: the first trap has the first conduction type And extend along a first direction；Second trap and third trap have the second conduction type and institute are arranged in a second direction On the opposite side for stating the first trap；First array of bit location and the second array of bit location, setting is in first trap to described Above third trap；Tape cell is arranged above first trap to the third trap and is arranged in first array and institute It states between second array, the tape cell includes: the first trap picking region and the second trap picking region, has first conduction Type and above first trap and separated from one another in said first direction, first trap picking region of setting It is greater than the doping concentration of first trap with the doping concentration of second trap picking region；And third trap picking region and Four trap picking regions have second conduction type different from first conduction type, and are separately positioned on described Above second trap and the third trap, and separated from one another in this second direction, third trap picking region and institute The doping concentration for stating the 4th trap picking region is greater than the doping concentration of second trap and the third trap；First conductive pattern and Second conductive pattern is respectively electrically connected to first trap picking region and second trap picking region and described first Extend above trap picking region and second trap picking region；And third conductive pattern, it is electrically connected to the third trap and picks up It takes region and the 4th trap picking region and prolongs above third trap picking region and the 4th trap picking region It stretches.

According to another aspect of the present invention, a kind of semiconductor devices is provided, comprising: the first trap and the second trap have the One conduction type and separated from one another in a first direction；Third trap has second different from first conduction type Conduction type, and first part on the side including first trap and second trap is arranged in, setting are described the Second part on the other side of one trap and second trap and the first part and the second part are connected to each other And the Part III between first trap and second trap is set；First array of bit location, setting is described the Above the first part and second part of one trap and the third trap；The second array of bit location, setting in second trap and Above the first part of the third trap and second part；Tape cell, setting is in first trap, second trap and described Above third trap and it is arranged between first array and the second array, the tape cell includes: the first trap pick-up area Domain and the second trap picking region have first conduction type, are separately positioned on above first trap and second trap, And separated from one another in said first direction, the doping of first trap picking region and second trap picking region is dense Degree is greater than the doping concentration of first trap and second trap；And third trap picking region, there is second conductive-type Type is arranged above the third trap and is arranged between first trap picking region and second trap picking region, The doping concentration of third trap picking region is greater than the doping concentration of the third trap；First conductive pattern and the second conductive pattern Case is electrically connected to first trap picking region and second trap picking region, and respectively in first trap pick-up area Extend above domain and second trap picking region；And third conductive pattern, it is electrically connected to third trap picking region, and And extend above third trap picking region.

According to another aspect of the invention, providing a kind of semiconductor devices includes: the first trap and the second trap, has first Conduction type, and it is separated from one another in a first direction；Third trap has and leads different from the second of first conduction type Electric type, and first part on the side including first trap and second trap is arranged in, be arranged described first Second part on the other side of trap and second trap and the first part and the second part are connected to each other and The Part III that first trap and second trap are separated from each other；Bit location, setting is in first trap and described the Above the first part of three traps and second part；Tape cell is arranged on first trap, second trap and the third trap Side, the tape cell include: the first trap picking region and the second trap picking region, have first conduction type, set respectively It sets above first trap and second trap, and separated from one another in said first direction, first trap picks up The doping concentration of region and second trap picking region is greater than the doping concentration of first trap and second trap；And the Three trap picking regions have second conduction type, are arranged above the third trap and are arranged and pick up in first trap It takes between region and second trap picking region, the doping concentration of third trap picking region is greater than mixing for the third trap Miscellaneous concentration；First conductive pattern and the second conductive pattern are connected to first trap picking region and second trap pick-up area Domain, and extend above first trap picking region and second trap picking region respectively；And third conductive pattern, It is electrically connected to third trap picking region, and is extended above third trap picking region, wherein institute's bitcell is only It is arranged on the side of the tape cell.

Detailed description of the invention

When reading in conjunction with the accompanying drawings, various aspects of the invention are best understood from described in detail below.It should Note that according to the standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, various parts Size can be arbitrarily increased or decreased.

Fig. 1 shows the schematic layout of the semiconductor devices of embodiment according to the present invention.

Fig. 2 shows the enlarged drawings of the region R1 of Fig. 1 of embodiment according to the present invention.

Fig. 3 shows the enlarged drawing of the region R2 of Fig. 1 of embodiment according to the present invention.

Fig. 4 A shows the static random access memory (SRAM) for being embodied as bit location of embodiment according to the present invention The circuit diagram of unit.

Fig. 4 B shows the layout of the bit location for the circuit diagram of embodiment according to the present invention shown in Figure 4 A.

Fig. 4 C shows the simplified topology of bit location shown in Fig. 4 B of embodiment according to the present invention.

Fig. 4 D shows the diagram of bit location and tape cell.

Fig. 5 A and Fig. 5 B show the layout of the tape cell in Fig. 3 of embodiment according to the present invention.

Fig. 5 C shows the region of the tape cell of embodiment according to the present invention.

Fig. 5 D shows cutting along the substrate including trap and trap picking region intercepted of the line V-V ' in Fig. 5 B and 5C Face figure.

Fig. 5 E shows the region of the tape cell of embodiment according to the present invention.

Fig. 6 A and Fig. 6 B show another layout of the tape cell in Fig. 3 of embodiment according to the present invention.

Fig. 6 C shows the region of the tape cell of embodiment according to the present invention.

Fig. 6 D is shown along the substrate including trap and trap picking region intercepted of the line VI-VI ' in Fig. 6 B and 6C Sectional view.

Fig. 6 E shows the region of the tape cell of embodiment according to the present invention.

Fig. 7 shows another enlarged drawing of the region R1 of Fig. 1 of embodiment according to the present invention.

Fig. 8 shows another enlarged drawing of the region R2 of Fig. 1 of embodiment according to the present invention.

Fig. 9 A and Fig. 9 B show the layout of the tape cell in Fig. 8 of embodiment according to the present invention.

Fig. 9 C shows the region of the tape cell of embodiment according to the present invention.

Fig. 9 D is shown along the substrate including trap and trap picking region intercepted of the line IX-IX ' in Fig. 9 B and 9C Sectional view.

Fig. 9 E shows the region of the tape cell of embodiment according to the present invention.

Figure 10 A and Figure 10 B show the circuit for implementing bit location in the semiconductor device of embodiment according to the present invention Figure.

Specific embodiment

Following disclosure provides the different embodiments or example of many different characteristics for realizing provided theme. The particular instance of component and arrangement is described below to simplify the present invention.Certainly, these are only example, are not intended to limit this Invention.For example, in the following description, above second component or the upper formation first component may include the first component and second The embodiment that component is formed in a manner of directly contacting, and also may include can be with shape between the first component and second component At additional component, so that the embodiment that the first component and second component can be not directly contacted with.In addition, the present invention can be Repeat reference numerals and/or character in each example.The repetition is that for purposes of simplicity and clarity, and itself is not indicated The relationship between each embodiment and/or configuration discussed.

Although for ease of explanation, it is described with specific, continuous sequence in disclosed methods, devices and systems Some operations, it should be appreciated that, unless particular statement presented below needs particular order, otherwise this mode is retouched It states including rearranging.Such as, in some cases it may rearrange or be performed simultaneously the operation described in order.

In some embodiments of the invention, for example, semiconductor fin is used for fin formula field effect transistor (FinFET).Partly lead Body fin can be prominent from semiconductor substrate and be used to form various semiconductor devices, including but not limited to fin field effect crystal It manages (FinFET).Fin can be patterned by any suitable method.For example, fin can be used one or more photoetching processes into Row patterning, including double patterning process or more Patternized techniques.In general, double patterning process or more Patternized technique combination light It carves and self-registered technology, between allowing pattern to be made with than otherwise using obtained by the direct photoetching process of single Away from smaller spacing.For example, in one embodiment, sacrificial layer forms on substrate and carries out pattern using photoetching process Change.Spacer is formed on the side of patterned sacrificial layer using self-registered technology.Then sacrificial layer and remaining are removed Spacing body can be used for patterning fin.

Fig. 1 shows the schematic layout of the semiconductor devices 100 of embodiment according to the present invention.In some embodiments In, semiconductor devices 100 is static random access memory (SRAM).

With reference to Fig. 1, the semiconductor devices 100 of embodiment according to the present invention includes region 110；Bit location region 120, Each bit location region is included in column direction (that is, Y-direction) and extends and by the multiple positions separated from one another of region 110 Unit or multiple bit cell arrays；And peripheral circuit, including the first Y- multiplexer and sensing amplifier 161, second Y- multiplexer and sensing amplifier 162 and word line driver/selector 163.

The first Y- multiplexer is arranged in bit location region 120 and region 110 in an alternating fashion in a column direction Between sensing amplifier 161 and the 2nd Y- multiplexer and sensing amplifier 162.

Bit line BL and paratope line BLB extends along column direction and multiplexes with bit location and the first Y- is electrically connected to Device and sensing amplifier 161 and/or the 2nd Y- multiplexer and sensing amplifier 162, wherein paratope line BLB transmission Signal is complementary with the signal that bit line BL is transmitted.

Wordline WL is along multiple bit locations in the line direction (that is, X-direction) vertical with column direction unit area 120 in place Top extends, and is electrically connected to multiple bit locations and word line driver/selector 163.Although a word is shown in FIG. 1 Line drive/selector 163, but semiconductor devices 100 may include that unit area 120 and region 110 in place is arranged Another word line driver/the selector opposite with word line driver/selector 163 on the other side.

First Y- multiplexer and sensing amplifier 161, the 2nd Y- multiplexer and sensing amplifier 162 and wordline Driver/selector 163 operationally selects bit location, allows to through the first Y- multiplexer and sensing amplifier 161 and/or the 2nd Y- multiplexer and sensing amplifier 162 are read and output is stored in bit location data and will be new Bit location is written in data.

In some embodiments, power supply pattern Vdd and Vss1/Vss2 extend along column direction, and connect in a column direction To the source region of the respective transistor of multiple bit locations, wherein power supply pattern Vdd and Vss1/Vss2 is by such as the first metal One layer of conductive pattern of layer is made.When for example, by holding voltage to be applied respectively to power supply pattern Vdd and Vss1/ provided by power supply When Vss2, the multiple bit locations for being connected to power supply pattern Vdd and Vss1/Vss2 are powered (energized) to allow multiple position Cell operation, so that passing through the first Y- multiplexer and sensing amplifier 161, the 2nd Y- multiplexer and sensing amplifier 162 and word line driver/selector 163 operation from multiple bit locations read its store data or can be by new data It is written in multiple bit locations.

Region 110 including tape cell provides the trap in active area inside the trap for including N-type trap and p-type trap and picks up It takes.Tape cell is used for voltage pick-up to provide trap bias, so as to prevent or inhibit along bit line BL's and paratope line BLB The voltage landing of extending direction (that is, column direction).Tape cell in region 110 not storing data, and it is to provide N-type trap and P Connection and end voltage between type trap.

In some embodiments, diagram shown in Fig. 1, semiconductor devices 100 includes being located at topmost and most lower Topmost and lowest part region 110 above and below site units region 120.It is distributed in multiple bit location regions 120 To allow pairs of bit line BL and paratope line BLB to be propagated through greater number of position in a column direction longerly single for region 110 Member or bit cell array, without leading to bit line BL between multiple bit locations in a column direction and BLB pairs of paratope line Difference is greater than predetermined tolerance limit.

However, if tape cell does not provide or provides insufficient density in a column direction, between nearest tape cell Different performances can be presented in the bit location for separating different distance.For example, it may be possible to which latch occurs, and then lead to semiconductor devices Failure or performance deterioration.

Referring still to Fig. 1, semiconductor devices 100 further comprises prolonging above each region 110 along line direction The N trap band pattern NL1/NL2 and p-well band pattern P L stretched.N trap band pattern NL1/NL2 and p-well band pattern P L are by such as the second metal One layer of conductive pattern of layer is made, and is respectively connected to end voltage.In some embodiments, the first metal layer and second metal layer It is arranged in different levels and its pattern is by penetrating the insulating layer being arranged between the first metal layer and second metal layer Through-hole is connected to each other.In some embodiments, pass through the vertical connecting structure in region 120, such as through-hole and contact, N Trap band pattern NL1/NL2 is electrically connected to power supply pattern Vdd and p-well band pattern P L is electrically connected to power supply pattern Vss1/Vss2.Slightly After these components will be described referring to Fig. 3 and Fig. 5 A to 9D.

In some embodiments, wordline WL with pattern NL1/NL2 and p-well with for manufacturing N trap with the identical of pattern P L by leading Electric layer is made, and but the invention is not restricted to this.

In some embodiments, semiconductor devices 100 further includes the top edge cellular zone of formed therein which edge dummy unit Domain 131 and lower edge unit area 132.In some embodiments, diagram shown in Fig. 1, top edge unit area 131 is being arranged Side is set up between the first Y- multiplexer and sensing amplifier 161 and topmost region 110, and in Fig. 1 institute In the diagram shown, 162 He of the 2nd Y- multiplexer and sensing amplifier is arranged in lower edge unit area 132 in a column direction Between lowest part region 110.

In other embodiments, it is convenient to omit topmost region 110 and lowest part region 110 shown in Fig. 1.In In this case, top edge unit area 131 be set up directly on topmost bit location region 120 and the first Y- multiplexer and Between sensing amplifier 161, and lower edge unit area 132 is set up directly on lowest part bit location region 120 and the 2nd Y- Between multiplexer and sensing amplifier 162.

Optionally or optionally, semiconductor devices 100 further comprises additional edge cells region (not shown), In, it is pseudo- single that additional edge is formed in the left and right side of combination zone for including region 110 and bit location region 120 Member.In this way, edge cells region 131 and 132 and additional edge cells region are entirely around all bit location regions.In In this case, the variation of the bit location in different location caused by the technique change by different location can be inhibited.

Fig. 2 shows the enlarged drawings of the region R1 of Fig. 1.For ease of description, Fig. 2 shows the selection layer of region R1, But the semiconductor devices 100 of embodiment according to the present invention includes extra play.

Referring to Fig. 1 and Fig. 2, top edge unit area 131 includes p-type trap Pwell.Tape cell region 110 and bit location area Domain 120 includes the p-type trap Pwell and N-type trap Nwell being alternately arranged along line direction.Lower edge unit area 132 includes P Type trap Pwell.P-type trap Pwell and top edge unit area 131 in tape cell region 110 and bit location region 120 and following P-type trap Pwell in edge unit area 132 forms the continuous overall region (integral of as shown in Figure 2 one Region), wherein the side of being expert at is arranged in the N-type trap Nwell with banded structure in tape cell region 110 and bit location region 120 Upwards.

Although being not shown, according to other embodiments, top edge unit area 131 includes N-type trap, tape cell region 110 and bit location region 120 include the p-type trap being alternately arranged along line direction and N-type trap, and lower edge unit area 132 include N-type trap.Tape cell region 110 and N-type trap and top edge unit area 131 and lower edge in bit location region 120 N-type trap in unit area 132 forms a continuous overall region, wherein tape cell region 110 and bit location region 120 With banded structure p-type trap setting in the row direction.

Fig. 3 shows the enlarged drawing of the region R2 of Fig. 1.For ease of description, the selection in the R2 of region is shown in Fig. 3 Layer, but the semiconductor devices 100 of embodiment according to the present invention is included in unshowned extra play in Fig. 3.

With reference to Fig. 3, in a column, the two bit location regions separated by region 110 are arranged in tape cell R21 Between two bit location R22 in 120.Tape cell refers to the region with bit location in the row direction with same widths It a unit cell in 110 and is aligned in a column direction with bit location.

Each bit location R22 is included in the one or more wordline WL extended above bit location R22 along line direction X. The wordline WL that bit location R22 is extended through in mutually colleague is electrically connected to the respective transistor of the bit location in mutually colleague.Although It is not shown in Fig. 3, but wordline WL is electrically connected to the peripheral circuit of such as word line driver/selector 163.

Each bit location R22 include the bit line BL made of identical conduction layer, paratope line BLB, power supply pattern Vdd and Vss1/Vss2, for example, the first metal wire.In Fig. 3, power supply pattern Vss1, bit line BL, power supply pattern Vdd, paratope line BLB It is arranged with power supply pattern Vss2 along line direction X with this sequence.However, power supply pattern Vss1, bit line BL, power supply pattern The sequence of Vdd, paratope line BLB and power supply pattern Vss2 are not limited to sequence shown in Fig. 3, and can be according to design details It modifies.

Power supply pattern Vss1, bit line BL, power supply pattern Vdd, paratope line BLB and power supply pattern Vss2 in same column Each of extend continuously through region 110 and bit location region 120.In this way, power supply pattern Vss1 in same column, Each of bit line BL, power supply pattern Vdd, paratope line BLB and power supply pattern Vss2 are electrically connected to each position in same column The respective transistor of unit.Although being not shown in Fig. 3, power supply pattern Vss1, bit line BL, power supply pattern Vdd, paratope Line BLB and power supply pattern Vss2 is electrically connected to peripheral circuit, such as the first Y- multiplexer and sensing amplifier 161 and/or The power supply of 2nd Y- multiplexer and sensing amplifier 162 and offer end voltage.

In some embodiments, tape cell R21 includes the first N trap band made of the identical conduction layer of such as second metal layer Pattern NL1 and the 2nd N trap band pattern NL2 and p-well band pattern P L, wherein the conductive layer is different from being used to form power supply pattern The conductive layer of Vss1, bit line BL, power supply pattern Vdd, paratope line BLB and power supply pattern Vss2.In some embodiments, it is used for It manufactures the first N trap and can be also used for wordline with the conductive layer of pattern P L with pattern NL2 and p-well with pattern NL1 and the 2nd N trap WL。

With reference to Fig. 3, p-well band pattern P L is arranged between the first N trap band pattern NL1 and the 2nd N trap band pattern NL2 and edge Line direction extend.In some embodiments, wordline WL, the first N trap band pattern NL1 and the 2nd N trap band pattern NL2 and p-well Band pattern P L has identical spacing in a column direction, and but the invention is not restricted to this.

In some embodiments, the first N trap band pattern NL1, p-well band pattern P L and the 2nd N trap band pattern NL2 are in column direction On be arranged by this sequence, and be arranged in region 110 two bit location R22 on opposite sides wordline WL it Between.

Referring still to Fig. 3, the first N trap band pattern NL1 and the 2nd N trap band pattern NL2 pass through through-hole V1 and V2 respectively and are electrically connected It is connected to power supply pattern Vdd, and p-well band pattern P L passes through through-hole V3 and V4 respectively and is electrically connected to power supply pattern Vss1 and Vss2. Although being not shown, the first N trap band pattern NL1 and the 2nd N trap band pattern NL2 and p-well band pattern P L are electrically connected to periphery Circuit such as provides such as power supply of end voltage.

Hereinafter, bit location R22 will be more fully described referring to Fig. 4 B and Fig. 4 D, and later with reference to Fig. 5 A to Fig. 6 B Tape cell R21 is more fully described.

Fig. 4 A shows the static random access memory (SRAM) that embodiment according to the present invention is embodied as bit location R22 The circuit diagram of unit.Fig. 4 B shows the layout of bit location R22, wherein shows the bit cell circuit figure in Figure 4 A.Fig. 4 C Show the simplified topology of bit location R22 shown in Fig. 4 B, wherein for ease of description, some of which layer is omitted.Figure 4D shows the diagram of bit location R22 and tape cell R21.

With reference to attached drawing, bit location R22 is 6 transistors (6T) sram cell, and including cross-linked first phase inverter With the second phase inverter and the first transmission gate transistor PG1 and the second transmission gate transistor PG2, wherein the first phase inverter includes First pull up transistor PU1 and the first pull-down transistor PD1 and the second phase inverter includes second pulling up transistor PU2 and second Pull-down transistor PD2.

The source electrode of transmission gate transistor PG1 and PG2 are coupled respectively to bit line BL and paratope line BLB；Transmission gate crystal The gate electrode of pipe PG1 and PG2 are coupled to wordline WL.First pull up transistor PU1, the first transmission gate transistor PG1, first drop-down The drain electrode of transistor PD1 is electrically connected to each other.Second pulls up transistor the lower crystal pulling of PU2, the second transmission gate transistor PG2 and second The drain electrode of body pipe PD2 is electrically connected to each other.The source electrode of first pull-down transistor PD1 and the second pull-down transistor PD2 connect respectively It is connected to power supply Vss1 and Vss2.First source electrode that PU1 and second pulls up transistor PU2 that pulls up transistor is connected to power supply Vdd.

As shown in figs. 4 b and 4 c, bit location R22 is formed in the region as defined by boundary B and including three trap, Wherein, which is N-type trap Nwell at its center and positioned at the first p-type trap of the opposite side N-type trap Nwell and the 2nd P Type trap Pwell.In figure 4 c, the boundary of N-type trap Nwell is only marked.It should be appreciated by those skilled in the art that the first p-type trap Pwell and the second p-type trap Pwell occupies the remaining area of bit location R22A.

Referring to Fig. 4 B and Fig. 4 C, bit location includes the semiconductor fin F extended each along column direction.Semiconductor fin F includes logical Cross the active area that the insulating layer of such as shallow trench isolation part (STI) (not shown) is separated from each other, wherein formed in the active area There is the transistor of bit location R22/R22A.

Source region, the drain region of the first transmission gate transistor PG1 and the first pull-down transistor PD1 of bit location R22 It is made with channel region of the semiconductor fin F in the first p-type trap Pwell.The lower crystal pulling of second transmission gate transistor PG2 and second Source electrode, drain electrode and the channel region of pipe PD2 is made of the semiconductor fin F in the second p-type trap Pwell.First pulls up transistor PU1 Source electrode, drain electrode and channel region and second pull up transistor PU2 source electrode, drain electrode and channel region by N-type trap Nwell Semiconductor fin F is made.

As shown in figs. 4 b and 4 c, bit location R22 includes first gate electrode layer P1, which includes being located at the First part and second above the channel region of one transmission gate transistor PG1 pull up transistor PU2 and the second pull-down transistor PD2 Channel region above second part.In addition, bit location R22 further comprises gate electrode layer P2, the second gate electrode layer P2 packet It includes the Part III above the channel region positioned at the second transmission gate transistor PG2 and pulls up transistor PU1 and first positioned at first Part IV above the channel region of pull-down transistor PD1.First gate electrode layer P1 and the second gate electrode layer P2 are in a column direction Spacing PP include one width and first gate electrode layer P1 and in first gate electrode layer P1 and the second gate electrode layer P2 The distance of two gate electrode layer P2 in a column direction.Other bit locations although being not shown, in identical bit location region 120 Gate electrode layer in a column direction repeatedly be arranged and have spacing PP.The material of gate electrode layer P1 and P2 can be polysilicon, Polysilicon and silicide, Al, Cu, W, Ti, Ta, TiN, TaN, TiW, WN, TiAl, TiAlN, TaC, TaCN and TiSiN, or Any other suitable conductive material.

As shown in Figure 4 D, one in two bit location R22 on the shared column boundary in same column is based on two position lists Boundary between first R22 is overturn about another one unit R 22, and two position lists on the shared column boundary in mutually colleague One in first R22 is overturn based on the boundary between two bit location R22 about another one unit R 22.It is fixed with difference To letter " F " indicate bit location R22 about mutual relative orientation.Although two bit location R22 are arranged in a column direction On every side of the opposite side of each tape cell R21, but the bit location R22 being arranged on the same side of each tape cell R21 Quantity be not limited to two and for example can be with more than two, for example, 4,16,32,128,256 or more It is a.

Fig. 5 A shows the specific layout of the tape cell R21 in Fig. 3.For ease of description, it is used to form in addition to being omitted The layer of power supply pattern Vss1, bit line BL, power supply pattern Vdd, paratope line BLB and power supply pattern Vss2；It is used to form the first N trap With pattern NL1 and the 2nd N with the through-hole V1-V4 between the layer of trap pattern NL2 and p-well with pattern P L and this two layers except, Fig. 5 B shows the essentially identical layout with layout shown in Fig. 5 A.Fig. 5 C shows the region of tape cell R21.Fig. 5 D is shown Along line V-V ' in Fig. 5 B and Fig. 5 C intercepted include trap and trap picking region substrate sectional view.Fig. 5 E is shown The region of tape cell R21.

In tape cell R21, corresponding semiconductor fin F is aligned with each other in a column direction and also (is scheming with bit location R22 Shown in 4B and Fig. 4 C) in corresponding semiconductor fin F alignment.Although by with for the semiconductor fin F's in bit location R22 The different legend of legend indicates the semiconductor fin F in tape cell R21, but all in tape cell R21 and bit location R22 Semiconductor fin F is formed in identical level by same process using identical material.

Semiconductor fin F in tape cell R21 cannot be used for forming transistor.However, even if based on half in tape cell R21 Conductor fin F forms transistor, but different from transistor in bit location R22, this transistor is not used in storing data.For side Just, the semiconductor fin F in tape cell R21 will be described as pseudo- semiconductor fin.Puppet in some embodiments, tape cell R21 is partly led Body fin is aligned with the semiconductor fin F in the bit location R22 of same column in a column direction.However, the semiconductor fin in tape cell R21 The length of F can be identical or different with the length of the semiconductor fin in bit location R22.

In tape cell R21, gate electrode layer PO is set as first gate electrode layer P1 and the second gate electrode with bit location R22 P2 is parallel (shown in Fig. 4 B and Fig. 4 C), and extends along line direction.Although by with for first in bit location R22 The different legend of the legend of gate electrode layer P1 and the second gate electrode layer P2 carrys out the gate electrode layer PO in the tape cell R21 of surface, still All gate electrode layer PO in tape cell R21 and all gate electrode layer P1 and P2 in bit location R22 are utilized by same process Identical material is formed in same level.Although each gate electrode layer PO in tape cell R21 is single pantostrat, this hair It is bright without being limited thereto.In other embodiments, each of one or more gate electrode layer PO include aligned with each other but are expert at The two or more parts separated on direction.Due to the gate electrode layer in bit location R22 differently, in tape cell R21 Gate electrode layer PO is not used in form the transistor for wanting storing data, so the gate electrode layer PO in tape cell R21 is in column direction The upper pseudo- gate electrode layer being repeatedly arranged by spacing PP, allows to inhibit each bit location due to semiconductor devices 100 Technique change in region 120 and the effect generated.

Although being not shown in the accompanying drawings, in a column direction, two positions on opposite sides of tape cell R21 are set The gate electrode layer P1 and P2 of unit R 22 and the pseudo- gate electrode layer PO in tape cell R21 are repeatedly arranged as having identical spacing PP。

In the present invention, the multiple patterns repeatedly arranged in one direction indicate that multiple patterns are based in one direction On preset space length periodically positioned, but the length of each pattern on the other direction vertical with a direction Degree/width can be the same or different from each other.

Although a spacing PP between two adjacent pseudo- gate electrode layers is only marked in figure 5B, in some implementations , the spacing between any other two adjacent gate electrode layers is identical as spacing PP.In addition, although being not shown, The gate electrode P1 or P2 of the bit location R22 and pseudo- gate electrode PO adjacent with the gate electrode P1 or P2 of bit location R22 also have with The identical spacing of spacing PP.

Referring now to Fig. 5 B to Fig. 5 D, tape cell R21 is divided into region 501 to region 508, region 511,512 and of region Region 520.In some embodiments, region 504, region 502, region 520, region 501 and region 503 are in a column direction with this Sequence is arranged, and indicates the N-type trap Nwell in tape cell R21.Region 504 and a position adjacent to tape cell R21 N-type trap Nwell (Fig. 3, Fig. 4 B and Fig. 4 C shown in) in unit R 22 is directly contacted and is aligned；And region 503 with adjacent to N-type trap Nwell (Fig. 3, Fig. 4 B and Fig. 4 C shown in) in the another one unit R 22 of tape cell R21 is directly contacted and is aligned.In In this case, the N-type trap Nwell of the N-type trap Nwell and bit location R22 of the tape cell R21 in same column form one completely N-type trap.Although being not shown in the accompanying drawings, remaining region 505 to region 508, region 511 and 512 indicate p-type Trap.P-type trap in tape cell R21 in a column direction with the p-type trap Pwell of adjacent bit positions R22 (in Fig. 4 B and Fig. 4 C institute Show) it connects and is aligned.

In some embodiments, the region 501 and 502 in N-type trap Nwell is the N trap pick-up area for being heavily doped with N-type impurity Domain, and the region 511 and 512 in p-type trap is the p-type picking region for being heavily doped with p type impurity.

In some embodiments, N trap picking region 501 and 502 and p-well picking region 511 and 512 surround tape cell The central area of R21.

In some embodiments, 501 He of N trap picking region is arranged in the region 520 in N-type trap Nwell in a column direction It is additionally arranged between p-well picking region 511 and 512 between 502 and in the row direction, when region 511, region 512 and region 520 when being heavily doped with p type impurity as a whole, the region 520 be heavily doped with during forming p-well picking region 511 and 512 with The opposite impurity of p type impurity.Because of the phase contra-doping in region 520, compared with other non-return doping, trap contact resistance And/or trap electrical sheet resistance is relatively large in region 520.In some embodiments, the p-type doping in opposite doped region 520 The doping concentration of agent is greater than the doping concentration of the N type dopant in N-type trap Nwell.For example, the p-type in opposite doped region 520 The doping concentration of dopant is the single order or higher order doping concentration of the N type dopant in N-type trap Nwell.

In the present invention, the region (such as N trap picking region/p-well picking region) of heavy doping refers at the top of trap Region, the doping concentration which has is before heavy doping (or bottom for not reaching heavy doping of well area) At least single order or higher order of doping concentration in well area.

Trap picking region 501 and 502 is electrically connected to power supply pattern Vdd by therebetween contact and p-well is picked up Region 511 and 512 is respectively electrically connected to power supply pattern Vss1 and Vss2 by therebetween contact (not shown).With reference to Fig. 5 A, power supply pattern Vdd are respectively electrically connected to the first N-type trap band pattern NL1 and the by therebetween through-hole V1 and V2 Two N-type traps band pattern NL2, and power supply Vss1 and Vss2 is electrically connected to p-type trap separately by therebetween through-hole V3 and V4 Band pattern P L.In this way, the first N-type trap band pattern NL1 and the second N-type trap band pattern NL2 and power supply Vdd are picked up at least through N trap Region 501 and 502 is taken to be electrically connected to N-type trap, and p-type trap band pattern P L and power supply pattern Vss1 and Vss2 at least through-hole P Trap picking region 511 and 512 is electrically connected to p-type trap.

With reference to Fig. 5 B, the width of tape cell R21 is that gate electrode layer P1, P2 (are shown in Fig. 4 B and Fig. 4 C in a column direction P1 and P2) and PO spacing PP N times (N is integer), but the invention is not restricted to this.

In some embodiments, puppet semiconductor fin F in each of N-type trap picking region 501 and 502 is in a column direction Length is 2 times of spacing 2PP and the width of each of N-type trap picking region 501 and 502 in a column direction is greater than 2 times of spacing 2PP and less than 4 times spacing 4PP.In some embodiments, each of N-type trap picking region 501 and 502 is included in it Two or more pseudo- gate electrode layer PO of upper extension.

Referring still to Fig. 5 B, in some embodiments, the pseudo- semiconductor fin F in p-type trap picking region 511 and 512 is being arranged Length on direction is 3 times of spacing 3PP, and the width of p-type trap picking region 511 and 512 in a column direction is greater than 3 times of spacing 3PP and less than 5 times spacing 5PP.In some embodiments, p-type trap picking region 511 and 512 includes 4 times extended on it Or more pseudo- gate electrode layer PO.

In some embodiments, the width of p-type trap picking region 511 and 512 in a column direction is greater than N-type trap picking region Each of 501 and 502 width in a column direction.Because of the width phase of p-type trap picking region 511 and 512 in a column direction For N-type trap picking region 501 and 502 or relative to the comparison with the relatively small width for p-type trap picking region Example and increase, so reducing the trap contact resistance and/or trap electrical sheet resistance of p-well picking region.In addition, two N-type traps are picked up It takes region 501 and 502 to be arranged on the opposite side of p-type trap picking region 511 and 512, and N-type trap picking region is used only Comparative example compares, and increases the gross area of N-type trap picking region.It therefore reduces the trap contact resistance of N trap picking region And/or trap electrical sheet resistance.According to some embodiments, compared with comparative example, N-type trap picking region 501 and 502 and p-type Trap picking region 511 and 512 has reduced trap contact resistance and/or reduced trap electrical sheet resistance, can inhibit or prevent all As the failure or performance of the latch of semiconductor devices 100 deteriorate.

First N trap is not limited to institute in Fig. 5 A with the layout of pattern P L with pattern NL2 and p-well with pattern NL1 and the 2nd N trap The layout shown.For example, the first N trap band pattern NL1, p-well band pattern P L and the 2nd N trap band pattern NL2 with same widths exist It is evenly distributed in the whole region of tape cell R21 along column direction.According to some embodiments, the wordline WL (figure of bit location R22 Shown in 3 and Fig. 4 B), the first N trap band pattern NL1, p-well band pattern P L with same widths and the 2nd N trap band pattern NL2 exist It is evenly distributed in the combination zone of bit location R22 and tape cell R21 along column direction.

Since the width of tape cell R21 in a column direction is greater than the width of 3 times of bit location R22 in a column direction, so The available width being routed with pattern P L and the 2nd N trap with pattern NL2 with pattern NL1, p-well on column direction to the first N trap is big In the wordline width of 3 times of each bit location R22.Therefore, in some embodiments, the wordline WL of bit location R22 is in a column direction Width less than the first N trap with pattern NL1, p-well with pattern P L and the 2nd N trap with each of pattern NL2 in a column direction Width.

Referring still to Fig. 5 B, in some embodiments, the pseudo- semiconductor fin F in edge region 503 and 504 is in column direction On length between 2 times of 2PP to 2.5 times of 2.5PP.Fringe region 503 and 504 includes 3 or more extended on it Pseudo- gate electrode layer PO.

In some embodiments, the width of tape cell R21 in a column direction is 16 times of spacing 16PP, but the present invention is unlimited In this.

The structure description of pseudo- semiconductor fin F and pseudo- gate electrode layer PO in the remaining P type trap zone domain of tape cell R21 can be joined The description of the structure of the pseudo- semiconductor fin F and pseudo- gate electrode layer PO in N-type trap region adjacent thereto in the row direction is examined, therefore The descriptions thereof are omitted to avoid redundancy.

Although Fig. 5 B and Fig. 5 C show N trap picking region 501 and 502 relative to p-type trap picking region 511 and 512 pairs It is configured with claiming or relative to the combination zone for including p-type trap picking region 511 and 512 and opposite doped region 520 It is symmetrically configured, but the invention is not restricted to this.

In some embodiments, by formation p-type trap picking region 511 and 512 caused by fabrication error and Translation, distortion or the expansion of opposite doped region 520 and the injection window of the p type impurity of heavy doping, 501 He of N trap picking region 502 are asymmetricly arranged relative to p-type trap picking region 511 and 512, or relative to including 511 He of p-type trap picking region 512 and the combination zone of opposite doped region 520 be asymmetricly arranged.For example, as shown in fig. 5e, towards N trap picking region 501 translation p-type trap picking regions 511 and 512 and opposite doped region 520, have logical so as to cause N trap picking region 502 Cross region 502 and opposite doped portion represented by the overlapping region of opposite doped region 520.However, due to N-type trap pick-up area Domain 502 is unaffected, so while the variation of the effective coverage of entire N-type trap picking region caused by phase contra-doping is relatively It is small.Therefore, according to some embodiments, tape cell R21 still can be effectively prevented or inhibit the voltage landing along column direction.

On the other hand, if one in N trap picking region be omitted and formed p-type trap picking region 511 and 512 with And translation, distortion or the expansion of opposite doped region 520 and the injection window of the p type impurity of heavy doping reduce one N of residue The effective area of trap picking region, then due to the increasing of trap contact resistance and/or trap electrical sheet resistance in remaining N trap picking region Greatly, such tape cell cannot be effectively prevented or inhibit the voltage landing along column direction.

Since the tape cell in the present invention includes being respectively connected to the first N trap band pattern NL1 and the 2nd N trap band pattern NL2 Two N-type trap picking regions 501 and 502, so even if forming the N-type impurity of N trap picking region 501 and 502 and heavy doping Injection window or formed p-type trap picking region 511 and 512 and the p type impurity of heavy doping injection window is translated, distortion Or expand, with cause one of N-type trap picking region 501 and 502 with including p-type trap picking region 511 and 512 and opposite The combination zone of doped region 520 is partially or even wholly overlapped, another and p-type in N-type trap picking region 501 and 502 Trap picking region 511 and 512 and opposite doped region 520 are not also overlapped.Therefore, power supply pattern Vdd and the first N trap band pattern NL1 and the 2nd N trap are electrically connected to N trap pick-up area still through therebetween through-hole or contact with one in pattern NL2 One of domain 501 and 502.

As described above, if only one N trap picking region is supplied to tape cell, and if forming N trap picking region The injection window of the N-type impurity of heavy doping forms p-type trap picking region and the injection window of the p type impurity of heavy doping is put down It moves, distortion or expand, to cause unique N trap picking region to partly overlap with combination zone or completely overlapped, wherein combine Region includes the region of p-type trap picking region and the phase contra-doping between p-type trap picking region, then unique N trap picks up Region has the resistance increased due to phase contra-doping, to reduce the effect for preventing or inhibiting the voltage landing along column direction Rate.In this case, relatively high number of tape cell is used for the bit location of same column, leads to the semiconductor for manufacturing bit location The lower service efficiency of the area of device.

However, according to the present invention, because each tape cell can be phase when reducing trap contact resistance and trap electrical sheet resistance More multi-bit cell in same column provides trap and picks up, so while additional area is for implementing two N trap picking regions and real The tape cell quantity applying relatively wide p-well picking region, but being the reduction of in same column.Therefore, reduce whole for manufacturing The gross area of tape cell in a column.For example, in one embodiment, a tape cell R21 can be from for 64 bit locations It increases to for 128 bit locations, wherein a tape cell is used in the comparative example for only including a N trap picking region 64 bit locations.Therefore, more many areas can be used for manufacturing bit location, to increase the memory capacity of semiconductor devices.

In embodiment described above, the wordline WL of bit location R22, the first N trap band pattern NL1 and the 2nd N trap band figure Case NL2 and p-well band pattern P L are made of identical conduction layer, such as second metal layer.However, the invention is not limited thereto.At it In his embodiment, the wordline WL of bit location R22 by with for manufacture the first N trap band pattern NL1 and the 2nd N trap band pattern NL2 with And the different conductive layer of conductive layer of the p-well with pattern P L is formed.For example, the wordline WL of bit location R22 by second metal layer on Third metal layer be made, and the first N trap band pattern NL1 and the 2nd N trap band pattern NL2 and p-well band pattern P L are by second Metal layer is made, and vice versa.

Fig. 6 A shows another layout of the tape cell R21 in Fig. 3.For ease of description, it is used to form in addition to being omitted The layer of power supply pattern Vss1, bit line BL, power supply pattern Vdd, paratope line BLB and power supply pattern Vss2 are used to form the first N Layer of the trap with pattern NL1 and the 2nd N trap with pattern NL2 and p-well with pattern P L, and the through-hole V1- between this two layers Except V4, Fig. 6 B shows and is laid out essentially identical layout shown in Fig. 6 A.Fig. 6 C shows the region of tape cell R21. Fig. 6 D is shown along the substrate including multiple traps and multiple trap picking regions intercepted of the line VI-VI ' in Fig. 6 B and Fig. 6 C Sectional view.Fig. 6 E shows the region of tape cell R21.

With reference to Fig. 6 A to Fig. 6 C, the layout of tape cell R21 additionally includes pseudo- gate electrode layer PO61, the puppet gate electrode layer PO61 be inserted into N trap picking region 501 with include p-well picking region 511,512 and opposite doped region 520 combination zone it Between.In addition, puppet gate electrode layer PO62 is inserted into N trap picking region 502 and includes p-well picking region 511,512 and phase contra-doping Between the combination zone in region 520.N trap picking region 501 is spaced apart by region 509 with opposite doped region 520, wherein The region 509 is a part of the N-type trap Nwell of tape cell R21；N trap picking region 502 passes through region 510 and phase contra-doping Region 520 is spaced apart, wherein the region 510 is a part of the N-type trap Nwell of tape cell R21.

In some embodiments, the width of tape cell R21 in a column direction is 18 times of spacing 18PP, but the present invention is unlimited In this.In other embodiments, two or more gate electrode layers can be inserted N trap picking region 501 and include p-well pick-up area Between the combination zone of domain 511 and 512 and opposite doped region 520, and it is inserted into N trap picking region 502 and includes p-well Between the combination zone of picking region 511 and 512 and opposite doped region 520.

Although Fig. 6 B and Fig. 6 C show N trap picking region 501 and 502 relative to p-type trap picking region 511 and 512 pairs Claim ground setting, but the invention is not restricted to this.In other embodiments, N trap picking region is formed as caused by fabrication error 501 and 502 and the injection window of the N-type impurity of heavy doping or to be formed include p-well picking region 511 and 512 and opposite Translation, distortion or the expansion of the combination zone of doped region 520 and the injection window of the p type impurity of heavy doping, so N trap Picking region 501 and 502 is asymmetricly arranged relative to p-type trap picking region 511 and 512 or relative to including that p-well is picked up It takes the combination zone in region 511 and 512 and opposite doped region 520 rather than is symmetrically arranged.For example, because additional areas 509 and 510, so even if as illustrated in fig. 6e, forming p-well picking region 511 and 512 towards the translation of N trap picking region 502 and weighing The injection window of the p type impurity of doping, opposite doped region 520 is also Chong Die with additional areas 510, but can not pick up with N trap Region 502 is taken to be overlapped.Therefore, by or be not injected into the position change of window, N trap picking region 501 and 502 is not by shadow It rings.

Other descriptions of Fig. 6 A to Fig. 6 E are referred to the description of Fig. 5 A to Fig. 5 E, therefore by the descriptions thereof are omitted to avoid superfluous It is remaining.

Fig. 7 shows another amplification diagram of the region R1 in Fig. 1.For ease of description, region R1 is shown in FIG. 7 In selection layer, but the semiconductor devices 100 of embodiment according to the present invention include extra play.

With reference to Fig. 1 and Fig. 7, top edge unit area 131 includes p-type trap Pwell, tape cell region 110 and bit location area Domain 120 includes the p-type trap Pwell and N-type trap Nwell alternately configured along line direction, and lower edge unit area 132 is wrapped Include p-type trap Pwell.131 and of p-type trap Pwell and top edge unit area in tape cell region 110 and bit location region 120 P-type trap Pwell in lower edge unit area 132 forms continuous global shape, wherein tape cell region 110 and bit location The N-type trap Nwell with banded structure in region 120 is separated from one another in the row direction.In some embodiments, in same column N-type trap Nwell to pass through the part of p-type trap Pwell being arranged in region 110 separated from one another.In this case, In In each column, semiconductor devices 100 includes multiple N-type traps, rather than the N-type trap of an entirety in example as shown in Figure 2 Nwell。

Although being not shown, according to other embodiments, top edge unit area 131 includes N-type trap, tape cell region 110 and bit location region 120 include the p-type trap alternately configured along line direction and N-type trap, and lower edge unit area 132 include N-type trap.Tape cell region 110 and N-type trap and top edge unit area 131 in bit location region 120 and following N-type trap in edge unit area 132 forms a continuous global shape, wherein tape cell region 110 and bit location region The 120 p-type trap with banded structure is separated from one another in the row direction.In some embodiments, the p-type trap in same column is logical The part for crossing the N-type trap being arranged in region 110 is separated from one another.In this case, in each column, semiconductor devices 100 include multiple p-type trap Pwell.

Fig. 8 shows another enlarged drawing of the region R2 in Fig. 1.For ease of description, it is shown in FIG. 8 in the R2 of region Selection layer, but the semiconductor devices 100 of embodiment according to the present invention includes unshowned extra play in fig. 8.

In addition to the central area in tape cell R21 ' is that (p-type trap Pwell is in a column direction by multiple N by p-type trap Pwell Type trap Nwell is separated from each other and multiple p-type trap Pwell is connected to each other in the row direction) except, area as shown in fig. 8 Domain R2 is substantially identical as region shown in Fig. 3.Other descriptions in Fig. 8 can refer to the description of Fig. 3, therefore omit it and retouch It states to avoid redundancy.

Fig. 9 A shows the detailed placement of the tape cell R21 ' in Fig. 8.For ease of description, electricity is used to form in addition to omitting The layer of source pattern Vss1, bit line BL, power supply pattern Vdd, paratope line BLB and power supply pattern Vss2；It is used to form the first N trap band Except pattern NL1 and the 2nd N trap are with the through-hole V1-V4 between the layer of pattern NL2 and p-well with pattern P L and this two layers, Fig. 9 B Show the layout substantially the same with Fig. 9 A.Fig. 9 C shows the region of tape cell R21 '.Fig. 9 D is shown along Fig. 9 B With the line IX-IX ' of 9C intercepted include multiple traps or multiple trap picking regions substrate sectional view.Fig. 9 E shows band The region of unit R 21 '.

In tape cell R21 ', the p-type trap picking region 511 ' based on P type trap zone domain is fully by N-type trap picking region 501 and 502 are separated from each other, and continuously extend between the edge of tape cell R21 ' in the row direction.In this case, Tape cell R21 ' includes a complete p-well picking region, which is formed in and p-well picking region 511 In 512 and the opposite corresponding region of doped region 520.Due to the edge of the tape cell R21 ' of p-type trap in the row direction Between continuously extend, so there is no the opposite doped regions in example shown in Fig. 5 A to Fig. 5 C in tape cell R21 ' 520。

With reference to Fig. 9 B, in some embodiments, pseudo- semiconductor fin F in p-type trap picking region 511 ' is in a column direction Length is 3 times of spacing 3PP, and the width of p-type trap picking region 511 ' in a column direction is greater than 5 times of spacing 5PP and less than 7 times Spacing 7PP, for example, 6 times of spacing 6PP.In some embodiments, p-type trap picking region 511 ' include 6 extended on it or More pseudo- gate electrode layer PO.

Similarly with the example in Fig. 9 A to Fig. 9 C, tape cell R21 ' additionally includes pseudo- gate electrode layer PO61, is inserted in N Between the pseudo- gate electrode layer PO that trap picking region 501 and 511 ' top of p-well picking region extend.In addition, pseudo- gate electrode layer PO62 It is inserted between the pseudo- gate electrode layer PO that N trap picking region 502 and 511 ' top of p-well picking region extend.N trap picking region 501 are separated by region 509 with p-well picking region 511 ', and N trap picking region 502 is picked up by region 510 and p-well Region 511 ' separates, wherein the part and region 510 for the N-type trap Nwell that region 509 is tape cell R21 ' are tape cell The part of the N-type trap Nwell of R21 '.

Although being not shown in Fig. 9 A to Fig. 9 C, it can be omitted and be inserted in N trap picking region 501 and p-well pick-up area The top of domain 511 ' extends the pseudo- gate electrode layer PO61 between pseudo- gate electrode layer PO and it is inserted in N trap picking region 502 and p-well is picked up The pseudo- gate electrode layer PO62 between pseudo- gate electrode layer PO for taking 511 ' top of region to extend, so that tape cell R21 ' is in a column direction Width reduce.

In some embodiments, the width of p-well picking region 511 ' in a column direction is greater than N trap picking region 501 and 502 Each of width in a column direction.Because the width of p-well picking region 511 ' in a column direction is relative to N trap picking region 501 and 502 or relative to the relatively small width for p-type trap picking region comparative example and increase, so reducing P The trap contact resistance and/or trap electrical sheet resistance of type trap picking region.In addition, two N trap picking regions 501 and 502 are arranged in p-well On the opposite side of picking region 511 ', compared with the comparative example that a N-type trap picking region is used only, increases N trap and pick up Take the gross area in region 511 '.It therefore reduces the trap contact resistance and/or trap electrical sheet resistance of N trap picking region.According to some Embodiment, compared with comparative example, there is reduced trap to contact for N trap picking region 501 and 502 and p-well picking region 511 ' Resistance and/or reduced trap electrical sheet resistance, can inhibit or prevent the failure or performance of such as latch of semiconductor devices 100 Deterioration.

In some embodiments, the width of tape cell R21 ' in a column direction is 20 times of spacing 20PP, but the present invention is not It is limited to this.

Although Fig. 9 B and Fig. 9 C show N trap picking region 501 and 502 and symmetrically set relative to p-well picking region 511 ' It sets, but the invention is not restricted to this.In other embodiments, passing through formation N trap picking region caused by fabrication error 501 and 502 and carry out heavily doped N-type impurity injection window or formed p-well picking region 511 ' and carry out heavily doped P-type impurity Injection window translation, distortion or amplification, N trap picking region 501 and 502 relative to p-well picking region 511 ' asymmetricly Setting.For example, it is miscellaneous to carry out heavily doped P-type even if forming p-type trap picking region 511 ' because of additional areas 509 and 510 The injection window of matter is translated towards N trap picking region 502 shown in Fig. 9 D, and opposite doped region is Chong Die with additional areas 510, but Being impossible Chong Die with N trap picking region 502.Therefore, by or be not injected into the change in location of window, N trap picking region 501 It is unaffected with 502.

According to additional region 509 and 510 in other embodiments, is omitted.

Other descriptions of Fig. 9 A to Fig. 9 E are referred to the description of Fig. 5 A to Fig. 5 E and Fig. 6 A to Fig. 6 E, therefore, omit It is described to avoid redundancy.

According to the present invention, because each tape cell can be same column when reducing trap contact resistance and trap electrical sheet resistance In greater amount of bit location provide trap pick up, so while additional region for implement two N trap picking regions and For implementing relatively wide p-well picking region, but the quantity for the tape cell being the reduction of in same column.It therefore reduces with The gross area of tape cell in the entire column of manufacture.For example, in one embodiment, a tape cell R21 ' can be from for 64 A bit location is increased to for 128 bit locations, wherein one in the comparative example for only including a N trap picking region Tape cell is used for 64 bit locations.Therefore, more many areas can be used for manufacturing bit location, be held with increasing the storage of semiconductor devices Amount.

In the above description, tape cell R21 (or tape cell R21 ') is described as two bit location R22 being located in same column Between.The invention is not limited thereto.In other embodiments, tape cell R21 (or tape cell R21 ') can be arranged in a column direction For neighbouring topmost bit location or lowest part bit location R22.In addition to only one bit location R22 be disposed adjacent to tape cell R21 (or Tape cell R21 ') rather than except two bit location R22 are arranged on the opposite side of tape cell R21 (or tape cell R21 '), this Kind configuration and the configuration with reference to described in Fig. 5 A to Fig. 9 E are essentially identical.Therefore, the descriptions thereof are omitted to avoid redundancy.

In other embodiments, tape cell R21 (or tape cell R21 ') may be used as top edge unit in a column direction And/or lower edge unit.In this case, above-described top edge unit area 131 and lower edge cellular zone is omitted Domain 132.

In the above description, 6T SRAM bit cell is shown as implementing the example of the bit location R22 of semiconductor devices 100.Root According to other embodiments, bit location R22 can be implemented based on other kinds of bit location, for example, the other kinds of bit location packet Include the 8T SRAM bit cell read transmission gate transistor RPG and read pull-down transistor RPD, wherein its circuit shown in Figure 10 A Figure；Or dual-port SRAM bit cell, wherein its circuit diagram is shown in Figure 10 B.Those skilled in the art should understand that 8T The layout of SRAM bit cell and dual-port SRAM bit cell, and by the descriptions thereof are omitted.

In the above examples, fin formula field effect transistor (FinFET) is described as implementing the transistor in semiconductor devices. The invention is not limited thereto.For example, can based on such as can with the other types transistor of planar transistor and loopful gate transistor, Implement the tape cell of embodiment according to the present invention in the semiconductor device.

In the above examples, such as in the semiconductor devices for memory device implement the band of embodiment according to the present invention Unit.The invention is not limited thereto.For example, can logic pick up for N-type trap and/or p-type trap provide bias voltage its Implement tape cell according to the embodiment in the semiconductor devices of his type.

In some embodiments, one or more p-type traps pick-up area of tape cell is arranged in the N trap picking region of tape cell On the opposite side in domain.Therefore, though in the presence of for example by fabrication error result in one or more p-type traps picking region into Translation, distortion, the expansion of the injection window of row heavily doped P-type impurity, at least one N trap picking region is not also affected. Therefore, compared with other non-return doped regions, trap contact resistance and/or trap electrical sheet resistance in region 520 is relatively large. Therefore, according to some embodiments, tape cell still can be effectively prevented or inhibit the voltage landing along column direction.It can press down Make or prevent the latch for causing semiconductor devices failure or performance to deteriorate.

In some embodiments, because compared with the example for only implementing a N trap picking region in tape cell, each Tape cell can also can be used in greater number of bit location, so while additional region is for implementing to be arranged at one or more The N trap on opposite sides picking region of a p-type trap picking region, and increase one or more p-type traps in tape cell and pick up The width in region is taken, but reduces the gross area required for all tape cells in same column.Therefore, more many areas can be used for Bit location is made to increase the memory capacity of semiconductor devices, to improve the memory capacity of semiconductor devices.

In one embodiment, semiconductor devices, comprising: the first trap has the first conduction type and along first party To extension；Second trap and third trap have the second conduction type and the opposite of first trap are arranged in a second direction On side；First array of bit location and the second array of bit location are arranged above first trap to the third trap；Band is single Member is arranged above first trap to the third trap and is arranged between first array and the second array, The tape cell includes: the first trap picking region and the second trap picking region, has first conduction type and is arranged Above first trap and separated from one another in said first direction, first trap picking region and second trap pick up The doping concentration in region is taken to be greater than the doping concentration of first trap；And third trap picking region and the 4th trap picking region, With being different from second conduction type of first conduction type, and it is separately positioned on second trap and described the Above three traps, and separated from one another in this second direction, third trap picking region and the 4th trap pick-up area The doping concentration in domain is greater than the doping concentration of second trap and the third trap；First conductive pattern and the second conductive pattern, Be respectively electrically connected to first trap picking region and second trap picking region and in first trap picking region and Extend above second trap picking region；And third conductive pattern, it is electrically connected to third trap picking region and described 4th trap picking region and extend above third trap picking region and the 4th trap picking region.Implement at one In example, the width of each of third trap picking region and the 4th trap picking region in said first direction is greater than The width of each of first trap picking region and second trap picking region in said first direction.In a reality It applies in example, semiconductor devices further comprises: the first power supply pattern, in first array, the tape cell and described second Extend along a first direction above array, and is electrically connected to first conductive pattern and second conductive pattern；And Second source pattern and third power supply pattern, above first array, the tape cell and the second array along First direction extends, and is electrically connected to the third conductive pattern.In one embodiment, the first power supply pattern is arranged in institute State between second source pattern and the third power supply pattern and be electrically connected to first array and the second array The first transistor of bit location and the source region of second transistor, wherein the first transistor and the second transistor Source region have second conduction type；Second source pattern is electrically connected to first array and the second array Bit location third transistor source region, wherein the source region of the third transistor has described first conductive Type；And third power supply pattern is electrically connected to the 4th transistor of the bit location of first array and the second array Source region, wherein the source region of the 4th transistor has first conduction type.In one embodiment, half Conductor device further comprises: the first bit line is above first array, the tape cell and the second array along institute First direction extension is stated, and is electrically connected to the source of the 5th transistor of the bit location of first array and the second array Polar region domain, wherein the source region of the 5th transistor has second conduction type；And second bit line described Extend above an array, the tape cell and the second array along the first direction, and is electrically connected to described first The source region of 6th transistor of array and the bit location of the second array, wherein the source area of the 6th transistor Domain has second conduction type.In one embodiment, semiconductor devices further comprises: gate electrode layer is described first Extend in array and the second array along the second direction；And pseudo- gate electrode layer, along institute in the tape cell State second direction extension.The gate electrode layer and the pseudo- gate electrode layer are arranged in same level and by identical material system At.In one embodiment, the pseudo- gate electrode layer further comprises: the multiple first pseudo- gate electrode layers are picked up in first trap Overlying regions are taken to extend；Multiple second pseudo- gate electrode layers, extend above second trap picking region；And multiple thirds are pseudo- Gate electrode layer extends above third trap picking region and the 4th trap picking region.The multiple third puppet grid electricity Each setting in the layer of pole is between the described first pseudo- gate electrode layer and the second pseudo- gate electrode layer and in the third trap Extend above picking region and the 4th trap picking region.In one embodiment, the pseudo- gate electrode layer includes: the first puppet Gate electrode layer extends above first trap picking region；Second pseudo- gate electrode layer, above second trap picking region Extend；And third puppet gate electrode layer, extend above third trap picking region and the 4th trap picking region, and 4th pseudo- gate electrode layer, is arranged in first trap picking region and third trap picking region and the 4th trap pick-up area Between domain；And the 5th pseudo- gate electrode layer, setting is in second trap picking region and third trap picking region and described Between 4th trap picking region.In one embodiment, the pseudo- gate electrode layer includes: the first pseudo- gate electrode layer, described the Extend above one trap picking region；Second pseudo- gate electrode layer, extends above second trap picking region；And third puppet grid Electrode layer, extends and the 6th pseudo- gate electrode layer above third trap picking region and the 4th trap picking region, if It sets between first trap picking region and first array；And the 7th pseudo- gate electrode layer, it is arranged in second trap Between picking region and the second array.In one embodiment, semiconductor devices further comprises: opposite doped region, It is arranged between first trap picking region and second trap picking region and is arranged in third trap picking region Between the 4th trap picking region.The opposite doped region is arranged on first trap and doped with described second Conduction type, the doping concentration of the second conductivity type dopant in the opposite doped region are greater than the in first trap The doping concentration of one conductivity type dopant.

In embodiment, each of third trap picking region and the 4th trap picking region are in the first party Upward width is greater than each of first trap picking region and second trap picking region in said first direction Width.

In embodiment, semiconductor devices further comprises: the first power supply pattern, in first array, the band list Extend along a first direction above the first and described second array, and is electrically connected to first conductive pattern and described second and leads Electrical pattern；And second source pattern and third power supply pattern, in first array, the tape cell and second gust described Column top extends along a first direction, and is electrically connected to the third conductive pattern.

In embodiment, the first power supply pattern is arranged between the second source pattern and the third power supply pattern And it is electrically connected to the first transistor of the bit location of first array and the second array and the source electrode of second transistor Region, wherein the source region of the first transistor and the second transistor has second conduction type；Second electricity Source pattern is electrically connected to the source region of the third transistor of the bit location of first array and the second array, wherein The source region of the third transistor has first conduction type；And third power supply pattern, it is electrically connected to described The source region of 4th transistor of an array and the bit location of the second array, wherein the source electrode of the 4th transistor Region has first conduction type.

In embodiment, semiconductor devices further comprises: the first bit line, first array, the tape cell and Extend above the second array along the first direction, and is electrically connected to first array and the second array The source region of 5th transistor of bit location, wherein the source region of the 5th transistor has second conductive-type Type；And second bit line, prolong above first array, the tape cell and the second array along the first direction It stretches, and is electrically connected to the source region of the 6th transistor of the bit location of first array and the second array, wherein The source region of 6th transistor has second conduction type.

In embodiment, semiconductor devices further comprises: gate electrode layer, in first array and the second array In along the second direction extend；And pseudo- gate electrode layer, extend in the tape cell along the second direction, In, the gate electrode layer and the pseudo- gate electrode layer are arranged in same level and are manufactured from the same material.

In embodiment, the pseudo- gate electrode layer further comprises: the multiple first pseudo- gate electrode layers are picked up in first trap Overlying regions are taken to extend；Multiple second pseudo- gate electrode layers, extend above second trap picking region；And multiple thirds are pseudo- Gate electrode layer, extends above third trap picking region and the 4th trap picking region and the multiple third is pseudo- Each of gate electrode layer, setting is between the described first pseudo- gate electrode layer and the second pseudo- gate electrode layer.

In embodiment, the pseudo- gate electrode layer includes: the first pseudo- gate electrode layer, above first trap picking region Extend；Second pseudo- gate electrode layer, extends above second trap picking region；And third puppet gate electrode layer, described Extension and the 4th pseudo- gate electrode layer, are arranged in first trap above three trap picking regions and the 4th trap picking region Between picking region and third trap picking region and the 4th trap picking region；And the 5th pseudo- gate electrode layer, setting Between second trap picking region and third trap picking region and the 4th trap picking region.

In embodiment, the pseudo- gate electrode layer includes: the first pseudo- gate electrode layer, above first trap picking region Extend；Second pseudo- gate electrode layer, extends above second trap picking region；And third puppet gate electrode layer, described Extension and the 6th pseudo- gate electrode layer, are arranged in first trap above three trap picking regions and the 4th trap picking region Between picking region and first array；And the 7th pseudo- gate electrode layer, setting second trap picking region with it is described Between second array.

In embodiment, semiconductor devices further comprises: opposite doped region, is arranged in first trap picking region Between second trap picking region and it is arranged between third trap picking region and the 4th trap picking region, Wherein, the opposite doped region is arranged on first trap and doped with second conduction type, described to mix on the contrary The doping concentration of the second conductivity type dopant in miscellaneous region is greater than the first conductivity type dopant in first trap Doping concentration.

In one embodiment, semiconductor devices includes: the first trap and the second trap, has the first conduction type and the It is separated from one another on one direction；Third trap has the second conduction type, and including being arranged in first trap and described second First part on the side of trap, the second part being arranged on the other side of first trap and second trap and will The first part and the second part are connected to each other and the third between first trap and second trap are arranged in Part；First array of bit location is arranged in above first part and the second part of first trap and the third trap；Position The second array of unit is arranged in above first part and the second part of second trap and the third trap；Tape cell, if It sets above first trap, second trap and the third trap and is arranged in first array and the second array Between, the tape cell includes: the first trap picking region and the second trap picking region, has first conduction type, respectively It is arranged above first trap and second trap, and separated from one another in said first direction, first trap picks up The doping concentration of region and second trap picking region is taken to be greater than the doping concentration of first trap and second trap；And Third trap picking region has second conduction type, is arranged above the third trap and is arranged in first trap Between picking region and second trap picking region, the doping concentration of third trap picking region is greater than the third trap Doping concentration；First conductive pattern and the second conductive pattern, are electrically connected to first trap picking region and second trap picks up Region is taken, and is extended above first trap picking region and second trap picking region respectively；And third is conductive Pattern is electrically connected to third trap picking region, and extends above third trap picking region.In one embodiment In, semiconductor devices further comprises: the first power supply pattern, in first array, the tape cell and the second array Top extends along the first direction, and is electrically connected to first conductive pattern and second conductive pattern；And Second source pattern and third power supply pattern, along institute above first array, the tape cell and the second array First direction extension is stated, and is electrically connected to the third conductive pattern.In one embodiment, first power supply pattern is set It sets between second source pattern and the third power supply pattern and is electrically connected to first array and the second array Bit location the first transistor and second transistor source region, wherein the first transistor and second crystal The source region of pipe has second conduction type；Second source pattern is electrically connected to first array and described second The source region of the third transistor of the bit location of array, wherein the source region of the third transistor has described first Conduction type；Third power supply pattern is electrically connected to the 4th transistor of the bit location of first array and the second array Source region, wherein the source region of the 4th transistor have first conduction type.The semiconductor devices is also Include: the first bit line, prolongs above first array, the tape cell and the second array along the first direction It stretches, and is electrically connected to the source region of the 5th transistor of the bit location of first array and the second array, wherein The source region of 5th transistor has second conduction type；And second bit line, in first array, described Extend above tape cell and the second array along the first direction, and is electrically connected to first array and described the The source region of 6th transistor of the bit location of two arrays, wherein the source region of the 6th transistor has described the Two conduction types.In one embodiment, the width of third trap picking region in said first direction is greater than described the The width of one trap picking region and second trap picking region in said first direction.In one embodiment, semiconductor Device further comprises: gate electrode layer, extends in first array and the second array along the second direction；It is pseudo- Gate electrode layer extends in the tape cell along the second direction.The gate electrode layer and the pseudo- gate electrode layer setting In same level and it is manufactured from the same material.

In embodiment, semiconductor devices further comprises: the first power supply pattern, in first array, the band list Extend above first and described second array along the first direction, and is electrically connected to first conductive pattern and described the Two conductive patterns；And second source pattern and third power supply pattern, in first array, the tape cell and described second Extend above array along the first direction, and is electrically connected to the third conductive pattern.

In embodiment, first power supply pattern is arranged between second source pattern and the third power supply pattern simultaneously And it is electrically connected to the first transistor of the bit location of first array and the second array and the source area of second transistor Domain, wherein the source region of the first transistor and the second transistor has second conduction type；Second source Pattern is electrically connected to the source region of the third transistor of the bit location of first array and the second array, wherein institute The source region for stating third transistor has first conduction type；Third power supply pattern is electrically connected to first array With the source region of the 4th transistor of the bit location of the second array, wherein the source region of the 4th transistor has There is first conduction type；And the semiconductor devices further include: the first bit line, in first array, the band list Extend above first and described second array along the first direction, and is electrically connected to first array and second gust described The source region of 5th transistor of the bit location of column, wherein the source region of the 5th transistor has described second to lead Electric type；And second bit line, along the first party above first array, the tape cell and the second array To extension, and it is electrically connected to the source region of the 6th transistor of the bit location of first array and the second array, Wherein, the source region of the 6th transistor has second conduction type.

In embodiment, the width of third trap picking region in said first direction is picked up greater than first trap The width of region and second trap picking region in said first direction.

In embodiment, semiconductor devices further comprises: gate electrode layer, in first array and the second array In along the second direction extend；Pseudo- gate electrode layer extends in the tape cell along the second direction, wherein institute It states gate electrode layer and the pseudo- gate electrode layer is arranged in same level and is manufactured from the same material.

In one embodiment, semiconductor devices includes: the first trap and the second trap, with the first conduction type, and It is separated from one another on first direction；Third trap has the second conduction type, and including setting in first trap and described the First part on the side of two traps, the second part being arranged on the other side of first trap and second trap and will The third that the first part and the second part are connected to each other and are separated from each other first trap and second trap Part；Bit location is arranged in above first part and the second part of first trap and the third trap；Tape cell, if It sets above first trap, second trap and the third trap, the tape cell includes: the first trap picking region and second Trap picking region has first conduction type, is separately positioned on above first trap and second trap, and in institute State separated from one another on first direction, the doping concentration of first trap picking region and second trap picking region is greater than institute State the doping concentration of the first trap and second trap；And third trap picking region, there is second conduction type, setting exists Above the third trap and it is arranged between first trap picking region and second trap picking region, the third trap The doping concentration of picking region is greater than the doping concentration of the third trap；First conductive pattern and the second conductive pattern, are connected to First trap picking region and second trap picking region, and respectively in first trap picking region and described second Extend above trap picking region；And third conductive pattern, it is electrically connected to third trap picking region, and in the third Extend above trap picking region.Institute's bitcell is provided only on the side of the tape cell.In one embodiment, semiconductor Device further comprises: the first power supply pattern, extends above institute's bitcell and the tape cell along the first direction, And it is electrically connected to first conductive pattern and second conductive pattern；And second source pattern and third power supply diagram Case extends above institute's bitcell and the tape cell along the first direction, and it is conductive to be electrically connected to the third Pattern.In one embodiment, first power supply pattern is arranged in the second source pattern and the third power supply pattern Between and be electrically connected to the first transistor of institute's bitcell and the source region of second transistor, wherein described first is brilliant The source region of body pipe and the second transistor has second conduction type；Second source pattern is electrically connected to described The source region of the third transistor of bit location, wherein the source region of the third transistor has first conductive-type Type；Third power supply pattern is electrically connected to the source region of the 4th transistor of institute's bitcell, wherein the 4th transistor Source region have first conduction type.The semiconductor devices further include: the first bit line, in institute's bitcell and institute It states and extends above tape cell along the first direction, and be electrically connected to the source area of the 5th transistor of institute's bitcell Domain, wherein the source region of the 5th transistor has second conduction type；And second bit line, in institute's rheme list Extend above the first and described tape cell along the first direction, and is electrically connected to the source of the 6th transistor of institute's bitcell Polar region domain, wherein the source region of the 6th transistor has second conduction type.In one embodiment, described The width of third trap picking region in said first direction is greater than first trap picking region and second trap pick-up area The width of each of domain in said first direction.In one embodiment, semiconductor devices further comprises: gate electrode Layer extends in first array and the second array along the second direction；Pseudo- gate electrode layer, in the tape cell In along the second direction extend.The gate electrode layer and the pseudo- gate electrode layer are arranged in same level and by identical Material is made.

In embodiment, semiconductor devices further comprises: the first power supply pattern, in institute's bitcell and the tape cell Top extends along the first direction, and is electrically connected to first conductive pattern and second conductive pattern；And Second source pattern and third power supply pattern extend above institute's bitcell and the tape cell along the first direction, And it is electrically connected to the third conductive pattern.

In embodiment, first power supply pattern setting the second source pattern and the third power supply pattern it Between and be electrically connected to the first transistor of institute's bitcell and the source region of second transistor, wherein the first crystal The source region of pipe and the second transistor has second conduction type；Second source pattern is electrically connected to institute's rheme The source region of the third transistor of unit, wherein the source region of the third transistor has first conduction type； Third power supply pattern is electrically connected to the source region of the 4th transistor of institute's bitcell, wherein the source of the 4th transistor Polar region domain has first conduction type；And the semiconductor devices further include: the first bit line, in institute's bitcell and institute It states and extends above tape cell along the first direction, and be electrically connected to the source area of the 5th transistor of institute's bitcell Domain, wherein the source region of the 5th transistor has second conduction type；And second bit line, in institute's rheme list Extend above the first and described tape cell along the first direction, and is electrically connected to the source of the 6th transistor of institute's bitcell Polar region domain, wherein the source region of the 6th transistor has second conduction type.

In embodiment, the width of third trap picking region in said first direction is picked up greater than first trap The width of each of region and second trap picking region in said first direction.

In embodiment, semiconductor devices further comprises: gate electrode layer, in first array and the second array In along the second direction extend；Pseudo- gate electrode layer extends in the tape cell along the second direction, wherein institute It states gate electrode layer and the pseudo- gate electrode layer is arranged in same level and is manufactured from the same material.

Above-described term " embodiment " or " multiple embodiments " do not refer to identical embodiment or multiple identical embodiments, And the term is provided to emphasize the special characteristic or feature that are different from multiple other embodiments or multiple embodiments.This field skill Art personnel are it should be understood that unless provide opposite or opposite description, otherwise above-described " embodiment " or " multiple embodiments " It should be considered as implementing by all or part of combination each other.

Foregoing has outlined the feature of several embodiments so that those skilled in the art may be better understood it is of the invention each Aspect.It should be appreciated by those skilled in the art that they can easily be used for using based on the present invention to design or modify Implement and other process and structures in the identical purpose of this introduced embodiment and/or the identical advantage of realization.Art technology Personnel it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from of the invention In the case where spirit and scope, they can make a variety of variations, replace and change herein.