阅读说明：本技术 存储单元结构及半导体器件 (Memory cell structure and semiconductor devices ) 是由 谢启银 于 2019-08-08 设计创作，主要内容包括：本发明提供了一种存储单元结构及半导体器件,包括衬底及位于所述衬底上的若干存储单元,所述存储单元包括两个栅极结构,每个所述栅极结构包括一层叠体及围绕所述层叠体的栅介质层,所述层叠体包括顺次重叠的栅氧化层、浮栅层及控制栅层,所述栅氧化层较所述控制栅层更靠近所述衬底,其中,所述浮栅层的上下表面均呈波浪形,从而在器件尺寸缩小的同时能够保证浮栅层的面积足够,增加了浮栅层存储电子的能力,且可以利用浮栅层表面的形状使两个所述栅极结构的浮栅层相对的两端向上翘起以形成浮栅尖端,结构更加简单。(The present invention provides a kind of memory cell structure and semiconductor devices, several storage units including substrate and on the substrate, the storage unit includes two gate structures, each gate structure includes a laminated body and the gate dielectric layer around the laminated body, the laminated body includes the gate oxide being sequentially overlapped, floating gate layer and control grid layer, the gate oxide control grid layer is closer to the substrate, wherein, the upper and lower surface of the floating gate layer is wavy, to guarantee that the area of floating gate layer is enough while device dimensions shrink, increase the ability of floating gate layer storage electronics, and the both ends that the shape that can use floating gate layer surface keeps the floating gate layer of two gate structures opposite are upturned to form floating gate tip, structure is simpler.)

1. a kind of memory cell structure, which is characterized in that several storage units including substrate and on the substrate, it is described Storage unit includes two gate structures, and each gate structure includes a laminated body and the gate medium around the laminated body Layer, the laminated body includes the gate oxide, floating gate layer and control grid layer being sequentially overlapped, the gate oxide control gate Layer is closer to the substrate, wherein the upper and lower surface of the floating gate layer is wavy, and the floating gate of two gate structures The opposite both ends of layer are upturned to form floating gate tip.

2. memory cell structure as described in claim 1, which is characterized in that the floating gate layer of two gate structures is opposite The surface at both ends has upward curved profile, so that the opposite both ends of the floating gate layer of described two gate structures are tilted upward It rises.

3. memory cell structure as described in claim 1, which is characterized in that be formed in the substrate be arranged alternately it is several Source region and several drain regions, the gate structure is between the source region and the drain region.

4. memory cell structure as claimed in claim 3, which is characterized in that two gate structures share the drain region, Word line structure is formed on substrate between two gate structures, the word line structure is opposite with the position of the source region It answers.

5. memory cell structure as claimed in claim 3, which is characterized in that the floating gate of the floating gate layer of two gate structures Tip is directed at the word line structure.

6. memory cell structure as claimed in claim 5, which is characterized in that the memory cell structure further includes a medium Layer, the dielectric layer are located on the substrate, and two gate structures are respectively positioned in the dielectric layer.

7. memory cell structure as claimed in claim 6, which is characterized in that be also formed in the dielectric layer several conductive slotting Plug, the conductive plunger is connect with the source region, drain region and word line structure, by the source region, drain region and the word line structure It draws.

8. memory cell structure as claimed in claim 7, which is characterized in that the conductive plunger and the source region, drain region or An ohmic contact layer is additionally provided between word line structure, the material of the ohmic contact layer is metal silicide.

9. memory cell structure as described in claim 1, which is characterized in that the material of the gate oxide is silica, institute The material for stating floating gate layer and the control grid layer is polysilicon.

10. a kind of semiconductor devices, which is characterized in that including memory cell structure as claimed in any one of claims 1-9 wherein.

Technical field

The present invention relates to technical field of semiconductors more particularly to a kind of memory cell structures and semiconductor devices.

Background technique

Memory can substantially be divided into two major classes: volatile (volatile) and non-volatile (non-volatile).It is volatile to deposit Reservoir loses immediately when system is closed is stored in interior information: it needs lasting power supply to supply to maintain data.It is most of Random access memory (RAM) belong to it is such.Nonvolatile storage is closed in system or non-transformer for remaining to keep data at once Information, wherein floating gate type flash memory is exactly a kind of nonvolatile storage.

In general, floating gate type flash memory suffers from similar original unit framework, they have the gate structure of stacking, should Gate structure includes floating gate (or floating grid) and at least partly covers the control gate of floating gate (control grid), wherein floating gate is used In storage electronics, control gate controls the storage and release of the electronics in floating gate by coupling.In floating gate type flash memory, floating gate Area is one of the factor of ability for determining storage electronics.It is miniature with dimensions of semiconductor devices, floating gate type flush memory device Size is smaller and smaller, causes the area of floating gate also smaller and smaller, is unfavorable for the storage of electronics.

Summary of the invention

The purpose of the present invention is to provide a kind of memory cell structure and semiconductor devices, while device size reduces It can guarantee that the area of floating gate is enough, improve the ability of device storage electronics.

In order to achieve the above object, the present invention provides a kind of memory cell structure, including substrate and it is located at the substrate On several storage units, the storage unit include two gate structures, each gate structure include a laminated body and Around the gate dielectric layer of the laminated body, the laminated body includes the gate oxide, floating gate layer and control grid layer being sequentially overlapped, institute The gate oxide control grid layer is stated closer to the substrate, wherein the upper and lower surface of the floating gate layer is wavy, and The opposite both ends of the floating gate layer of two gate structures are upturned to form floating gate tip.

Optionally, the surface at the opposite both ends of the floating gate layer of two gate structures has upward curved profile, with The both ends for keeping the floating gate layer of described two gate structures opposite are upturned.

Optionally, several source regions being arranged alternately and several drain regions are formed in the substrate, the gate structure is located at Between the source region and the drain region.

Optionally, two gate structures share the drain region, are formed on the substrate between two gate structures There is word line structure, the word line structure is corresponding with the position of the source region.

Optionally, the floating gate tip of the floating gate layer of two gate structures is directed at the word line structure.

Optionally, the memory cell structure further includes a dielectric layer, and the dielectric layer is located on the substrate, two institutes Gate structure is stated to be respectively positioned in the dielectric layer.

Optionally, be also formed with several conductive plungers in the dielectric layer, the conductive plunger and the source region, drain region and Word line structure connection, the source region, drain region and the word line structure are drawn.

Optionally, an ohmic contact layer is additionally provided between the conductive plunger and the source region, drain region or word line structure, The material of the ohmic contact layer is metal silicide.

Optionally, the material of the gate oxide is silica, and the material of the floating gate layer and the control grid layer is Polysilicon.

The present invention also provides a kind of semiconductor devices, including the memory cell structure.

In memory cell structure provided by the invention and semiconductor devices, if including substrate and on the substrate Dry storage unit, the storage unit include two gate structures, and each gate structure is including a laminated body and surrounds institute The gate dielectric layer of laminated body is stated, the laminated body includes the gate oxide, floating gate layer and control grid layer being sequentially overlapped, the grid oxygen Change the layer control grid layer closer to the substrate, wherein the upper and lower surface of the floating gate layer is wavy, thus in device It can guarantee that the area of floating gate layer is enough while part size reduction, increase the ability of floating gate layer storage electronics, and can benefit It is upturned with the both ends that the shape of floating gate layer surface keeps the floating gate layer of two gate structures opposite to form floating gate tip, Structure is simpler.

Detailed description of the invention

Fig. 1 is the structural schematic diagram of memory cell structure provided in an embodiment of the present invention；

Fig. 2 is the enlarged drawing at floating gate tip provided in an embodiment of the present invention；

Wherein, appended drawing reference are as follows:

10- substrate；11- fleet plough groove isolation structure；S- source region；The drain region D-；21- gate oxide；22- floating gate layer；221- is floating Grid tip；23-ONO structure；24- control grid layer；25- gate dielectric layer；30- word line structure；40- ohmic contact layer；50- conduction is inserted Plug；

Specific embodiment

A specific embodiment of the invention is described in more detail below in conjunction with schematic diagram.According to following description and Claims, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and Using non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.

As shown in Figure 1, present embodiments provide a kind of memory cell structure, including substrate 10 and it is located on the substrate 10 Several storage units, the storage unit includes two gate structures, and each gate structure includes a laminated body and enclosing Around the gate dielectric layer 25 of the laminated body, the laminated body includes the gate oxide 21, floating gate layer 22 and control gate being sequentially overlapped Layer 24, the gate oxide 21 control grid layer 24 is closer to the substrate 10, wherein the upper following table of the floating gate layer 22 Face is wavy, and the opposite both ends of floating gate layer 22 of two gate structures are upturned to form floating gate tip 221.

Specifically, the substrate 10 is silicon substrate 10, the shallow trench of isolation active area S is also formed in the silicon substrate 10 Isolation structure 11 also forms several source region S and several drain region D being arranged alternately by ion implanting in the substrate 10, The gate structure is on the substrate 10 between the source region S and the drain region D, the source region of each gate structure and its left and right S and drain region D collectively forms a storage position, it is seen then that in the memory cell structure, there are two storages for a storage unit tool Position, two storage positions share drain region D.

Further, the laminated body includes the gate oxide 21, floating gate layer 22 and control grid layer 24 being sequentially overlapped, the grid Oxide layer 21 covers the substrate 10, and the floating gate layer 22 covers the gate oxide 21, and the control grid layer 24 covers described Floating gate layer 22 is also additionally provided with an ONO structure 23 between the floating gate layer 22 and the control grid layer 24.In the present embodiment, institute The upper and lower surface for stating floating gate layer 22 is wavy, that is to say, that the floating gate layer 22 is whole be considered as one it is wavy Film layer, to be capable of increasing the area of floating gate layer 22 in the case where 22 width and thickness of floating gate layer is constant.Also, such as Fig. 2 institute Show, the surface at the opposite both ends of the floating gate layer 22 of two gate structures has upward curved profile, so that described two The both ends that the floating gate layer 22 of the gate structure is opposite are upturned.That is, the upper and lower surface of the floating gate layer 22 is Recess is alternate with protrusion, it is only necessary to which the end for guaranteeing the floating gate layer 22 is recess, then can guarantee the floating gate layer 22 There is floating gate tip 221 in end.

Optionally, two gate structures share the drain region D, shape on the substrate 10 between two gate structures At there is word line structure 30, the word line structure 30 is corresponding with the position of the source region S, the floating gate layer of two gate structures 22 floating gate tip 221 is directed at the word line structure 30, by applying voltage, that is, erasable institute on the word line structure 30 State the electronics stored in floating gate layer 22.

Optionally, the memory cell structure further includes a dielectric layer, and the dielectric layer is located on the substrate 10, and two The gate structure is respectively positioned in the dielectric layer.Several conductive plungers 50 are also formed in the dielectric layer, it is described conductive slotting Plug 50 is connect with the source region S, drain region D and word line structure 30, and the source region S, drain region D and the word line structure 30 are drawn Out.

Further, one ohm is additionally provided between the conductive plunger 50 and the source region S, drain region D or word line structure 30 Contact layer 40, the material of the ohmic contact layer 40 are metal silicide, and the material of the gate oxide 21 is silica, described The material of floating gate layer 22 and the control grid layer 24 is polysilicon.

Based on this, the present embodiment additionally provides a kind of semiconductor devices, including the memory cell structure.

To sum up, in memory cell structure provided in an embodiment of the present invention and semiconductor devices, including substrate and be located at institute Several storage units on substrate are stated, the storage unit includes two gate structures, and each gate structure includes one layer Stack and gate dielectric layer around the laminated body, the laminated body includes the gate oxide, floating gate layer and control being sequentially overlapped Grid layer, the gate oxide control grid layer is closer to the substrate, wherein the upper and lower surface of the floating gate layer is in wave Shape wave increases floating gate layer storage electronics to can guarantee that the area of floating gate layer is enough while device dimensions shrink Ability, and the shape that the can use floating gate layer surface both ends that keep the floating gate layer of two gate structures opposite be upturned with Floating gate tip is formed, structure is simpler.

The above is only a preferred embodiment of the present invention, does not play the role of any restrictions to the present invention.Belonging to any Those skilled in the art, in the range of not departing from technical solution of the present invention, to the invention discloses technical solution and Technology contents make the variation such as any type of equivalent replacement or modification, belong to the content without departing from technical solution of the present invention, still Within belonging to the scope of protection of the present invention.