阅读说明：本技术 垂直半导体装置 (Vertical semiconductor device ) 是由 李炅奂 姜昌锡 金容锡 林濬熙 金森宏治 于 2019-04-08 设计创作，主要内容包括：公开了一种垂直半导体装置,该垂直半导体装置包括其中绝缘图案和导电图案交替且重复地堆叠在基底上的导电图案结构。导电图案结构包括具有阶梯形状的边缘部分。导电图案中的每个导电图案包括与边缘部分中的阶梯的上表面对应的垫区域。垫导电图案被设置为接触垫区域的上表面的一部分。掩模图案设置在垫导电图案的上表面上。接触塞穿透掩模图案以接触垫导电图案。(A kind of vertical semiconductor device is disclosed, which includes that wherein insulating pattern and conductive pattern replace and be repeatedly stacked on the conductive pattern structure in substrate.Conductive pattern structure includes having the marginal portion of stairstepping.Each conductive pattern in conductive pattern includes pad area corresponding with the upper surface of the ladder in marginal portion.Pad conductive pattern is arranged to contact a part of the upper surface of pad area.Mask pattern is arranged on the upper surface of pad conductive pattern.Contact plug penetrates mask pattern with engagement pad conductive pattern.)

1. a kind of vertical semiconductor device, the vertical semiconductor device include:

Substrate；

Conductive pattern structure, in conductive pattern structure, insulating pattern and conductive pattern replace and are repeatedly stacked in substrate, Wherein, conductive pattern structure includes having the marginal portion of stairstepping, and each conductive pattern in conductive pattern includes having The pad area of upper surface corresponding with the upper surface of the ladder in marginal portion；

Conductive pattern is padded, a part of the upper surface of pad area is contacted；

Mask pattern, on the upper surface of pad conductive pattern；And

Contact plug penetrates mask pattern with engagement pad conductive pattern.

2. vertical semiconductor device according to claim 1, wherein the pad area with a conductive pattern in conductive pattern The pad conductive pattern of the part contact of the upper surface in domain includes that another conductive pattern in adjacent steps separates together.

3. vertical semiconductor device according to claim 1,

Wherein, conductive pattern longitudinally extends on the first direction parallel with the upper surface of substrate,

Wherein, the at the edge part in a first direction of each conductive pattern of the pad conductive pattern in conductive pattern and pad area The upper surface in domain contacts.

4. vertical semiconductor device according to claim 1, the vertical semiconductor device further include:

Spacer covers the side wall of the ladder of the marginal portion of conductive pattern structure.

5. vertical semiconductor device according to claim 4, wherein pad conductive pattern is arranged far from spacer.

6. vertical semiconductor device according to claim 1, wherein conductive pattern includes identical material with pad conductive pattern Material or different materials.

7. vertical semiconductor device according to claim 1,

Wherein, conductive pattern includes polysilicon or metal,

Wherein, pad conductive pattern includes polysilicon or metal.

8. vertical semiconductor device according to claim 1, wherein mask pattern includes silicon nitride or silica.

9. vertical semiconductor device according to claim 1,

Wherein, conductive pattern is upwardly extended in the first party parallel with the upper surface of substrate,

Wherein, the pad area of conductive pattern has stairstepping in a first direction.

10. vertical semiconductor device according to claim 1,

Wherein, conductive pattern longitudinally extends on the first direction parallel with the upper surface of substrate,

Wherein, the pad area of conductive pattern is in a first direction and parallel in vertical with first direction and with substrate upper surface Second direction on have stairstepping.

11. vertical semiconductor device according to claim 10, the vertical semiconductor device further include:

First spacer contacts corresponding with the upper surface of uppermost ladder in a second direction on the wall of upper ladder The first pad area；And

Second spacer, on the wall of upper ladder, contact and the ladder being located at below uppermost ladder in a second direction Corresponding second pad area in upper surface,

Wherein, the first spacer longitudinally extends in a second direction,

Wherein, the second spacer includes the first part longitudinally extended in a second direction and longitudinally extends in a first direction Second part.

12. vertical semiconductor device according to claim 11, wherein pad conductive pattern includes setting far from the first spacer The the first pad conductive pattern set and the second pad conductive pattern far from the setting of the second spacer.

13. vertical semiconductor device according to claim 12, wherein the first pad conductive pattern and the second pad conductive pattern The area of upper surface be equal to each other or different from each other.

14. vertical semiconductor device according to claim 1, the vertical semiconductor device further include:

Interlayer insulating film, covering conductive pattern structure, pad conductive pattern and mask pattern,

Wherein, interlayer insulating film has flat upper surfaces,

Wherein, contact plug penetrates interlayer insulating film and mask pattern.

15. a kind of vertical semiconductor device, the vertical semiconductor device include:

Substrate；

Conductive pattern structure, in conductive pattern structure, insulating pattern and conductive pattern replace and are repeatedly stacked in substrate, Wherein, conductive pattern is upwardly extended in the first party parallel with the upper surface of substrate, and the marginal portion of conductive pattern is in first party There is stairstepping, conductive pattern upwards and in the parallel second direction in vertical with first direction and with substrate upper surface Respectively include pad area corresponding with the upper surface of ladder；

Conductive pattern is padded, is located on the pad area of conductive pattern；

Mask pattern is located on pad conductive pattern；And

Contact plug, difference engagement pad conductive pattern, and it is electrically connected respectively to conductive pattern.

16. vertical semiconductor device according to claim 15, the vertical semiconductor device further include:

First spacer contacts corresponding with the upper surface of uppermost ladder in a second direction on the wall of upper ladder Pad area in each pad area；And

Second spacer, on the wall of upper ladder, contact and the ladder being located at below uppermost ladder in a second direction The corresponding pad area in upper surface in each pad area.

17. vertical semiconductor device according to claim 16, wherein pad conductive pattern includes setting far from the first spacer The the first pad conductive pattern set and the second pad conductive pattern far from the setting of the second spacer.

18. vertical semiconductor device according to claim 15, the vertical semiconductor device further include:

Second pad conductive pattern and the second mask pattern on the second pad conductive pattern, cover the most upper of conductive pattern structure The insulating pattern in face.

19. a kind of vertical semiconductor device, the vertical semiconductor device include:

Substrate；

Conductive pattern structure, in conductive pattern structure, insulating pattern and conductive pattern replace and are repeatedly stacked in substrate, Wherein, conductive pattern structure includes having the marginal portion of stairstepping, and each conductive pattern in conductive pattern includes and side The corresponding pad area in upper surface of ladder in edge point；

Spacer, on the wall of ladder；

Conductive pattern is padded, is located on pad area and far from spacer；

Mask pattern, on the upper surface of pad conductive pattern；And

Contact plug penetrates mask pattern with engagement pad conductive pattern.

20. vertical semiconductor device according to claim 19, wherein mask pattern includes silicon nitride or silica.

Technical field

The example embodiment of the disclosure is related to vertical semiconductor device, more particularly, to hanging down with structural stability Straight semiconductor device.

Background technique

The vertical semiconductor device of the vertical stacking memory cell in substrate is developed.Vertical semiconductor device can To include the contact plug for being electrically connected respectively to memory cell.

Summary of the invention

According to example embodiment, open to be related to a kind of vertical semiconductor device, which includes: substrate； Conductive pattern structure, in conductive pattern structure, insulating pattern and conductive pattern replace and are repeatedly stacked in substrate, In, conductive pattern structure includes having the marginal portion of stairstepping, each conductive pattern in conductive pattern include have with The pad area of the corresponding upper surface in the upper surface of ladder in marginal portion；Conductive pattern is padded, the upper surface of pad area is contacted A part；Mask pattern, on the upper surface of pad conductive pattern；And contact plug, mask pattern is penetrated with engagement pad conduction Pattern.

According to example embodiment, open to be related to a kind of vertical semiconductor device, which includes: substrate； Conductive pattern structure, in conductive pattern structure, insulating pattern and conductive pattern replace and are repeatedly stacked in substrate, In, conductive pattern is upwardly extended in the first party parallel with the upper surface of substrate, and the marginal portion of conductive pattern is in a first direction Above and in the parallel second direction in vertical with first direction and with substrate upper surface there is stairstepping, conductive pattern point It does not include pad area corresponding with the upper surface of ladder；Conductive pattern is padded, is located on the pad area of conductive pattern；Mask artwork Case is located on pad conductive pattern；And contact plug, difference engagement pad conductive pattern, and it is electrically connected respectively to conductive pattern.

According to example embodiment, open to be related to a kind of vertical semiconductor device, which includes: substrate； Conductive pattern structure, in conductive pattern structure, insulating pattern and conductive pattern replace and are repeatedly stacked in substrate, In, conductive pattern structure includes having the marginal portion of stairstepping, and each conductive pattern in conductive pattern includes and edge The corresponding pad area in the upper surface of ladder in part；Spacer, on the wall of ladder；Conductive pattern is padded, pad area is located at Upper and separate spacer；Mask pattern, on the upper surface of pad conductive pattern；And contact plug, penetrate mask pattern with Engagement pad conductive pattern.

Detailed description of the invention

Fig. 1 is the cross-sectional view for showing vertical semiconductor device according to example embodiment.

Fig. 2A, Fig. 2 B and Fig. 2 C are the cross-sectional views for showing a part of vertical semiconductor device according to example embodiment.

Fig. 3 and Fig. 4 is the plan view and perspective view for showing vertical semiconductor device according to example embodiment.

Fig. 5 to Figure 18 is the cross-sectional view for showing the method for manufacturing vertical semiconductor device according to example embodiment, plane Figure and perspective view.

Figure 19 to Figure 21 is the cross-sectional view for showing the method for manufacture vertical semiconductor device according to example embodiment.

Figure 22 is the cross-sectional view for showing vertical semiconductor device according to example embodiment.

Figure 23 to Figure 25 is the cross-sectional view for showing the method for manufacture vertical semiconductor device according to example embodiment.

Figure 26 is the cross-sectional view for showing vertical semiconductor device according to example embodiment.

Figure 27 is the cross-sectional view for showing vertical semiconductor device according to example embodiment.

Specific embodiment

Various example embodiments are more fully described now with reference to the attached drawing for showing some example embodiments.However, Inventive concept can by it is many it is selectable in the form of implement, and should not be construed as limited to the implementation of the example that illustrates herein Example.

Fig. 1 is the cross-sectional view for showing vertical semiconductor device according to example embodiment.Fig. 2A, Fig. 2 B and Fig. 2 C are to show The cross-sectional view of a part of vertical semiconductor device according to example embodiment.Fig. 3 and Fig. 4 are shown according to example embodiment The plan view and perspective view of vertical semiconductor device.In Fig. 4, contact plug is omitted.

Referring to figs. 1 to Fig. 4, in vertical semiconductor device according to example embodiment, conductive pattern structure 106a can be with It is arranged in substrate 100.Conductive pattern structure 106a may include submitting in the third direction vertical with the upper surface of substrate 100 It replaces and is repeatedly stacked on the insulating pattern 102a in substrate 100 and conductive pattern 104a.The marginal portion of conductive pattern 104a It can have stairstepping.For example, between insulating pattern 102a and conductive pattern 104a and substrate 100 along third direction Distance increase, insulating pattern 102a and conductive pattern 104a can have shorter and shorter length.Each conductive pattern 104a It may include pad area corresponding with the upper surface of each ladder.Pad conductive pattern 112a and 112b can be set to contact each pad A part of the upper surface in region.Mask pattern 116a can be set to the upper surface of covering pad conductive pattern 112a and 112b. Contact plug 134 can be set to penetrate mask pattern 116a with engagement pad conductive pattern 112a and 112b.Contact plug 134 can electricity It is connected to each conductive pattern 104a.Vertical semiconductor device can also include channel structure 128 and one or more intervals Part 110, the channel structure 128 penetrate conductive pattern structure 106a, and one or more spacer 110 covers conductive pattern The side wall of the stepped portion (or marginal portion) of case structure 106a.As it is used herein, the object for being described as " being electrically connected " is by structure It makes to make electric signal that can be transferred to another object from an object.As it is used herein, unless context is it is further noted that otherwise Term " contact ", which refers to, is directly connected to (that is, touching).

Substrate 100 can be semiconductor base, for example, silicon base, germanium substrate or silicon-Germanium base.

Conductive pattern structure 106a can longitudinally extend on the first direction parallel with the upper surface of substrate 100.It is multiple Conductive pattern structure 106a can divide each other in second direction vertical with first direction and parallel with the upper surface of substrate 100 Separatedly arrange.Opening 136 can be set between conductive pattern structure 106a.Because cell block is divided by opening 136, institute It can be configured as unit of cell block by opening 136.Be described as object, layer that " longitudinal direction " in particular directions extend or A part of person's object or layer has length and the width vertical with the direction on the specific direction, wherein length is big In width.

Each conductive pattern 104a may include the part not being stacked with other conductive pattern 104a.Conductive pattern 104a's Stacked part not can be set to pad area.Pad area can be located at different level.

In some embodiments, conductive pattern structure 106a can have rank in a first direction and in a second direction Trapezoidal shape.It may include multiple conductive pattern 104a in a ladder in a first direction in conductive pattern structure 106a. For example, each ladder of conductive pattern structure 106a may include more than one conductive pattern 104a.Conductive pattern 104a exists The stacking quantity in a ladder on first direction can be equal to the quantity of ladder in a second direction.As shown in the figure, Two conductive pattern 104a may include in a ladder in a first direction, in such a case, it is possible in second direction Two ladders of upper formation.In such embodiments, nethermost ladder in a second direction can only include single conductive Pattern 104a.

In some embodiments, conductive pattern 104a may include polysilicon.In some embodiments, conductive pattern 104a May include can be by metal or metallic compound that dry etching is readily removable.For example, conductive pattern 104a can wrap Include titanium, titanium nitride, tantalum or tantalum nitride.

In some embodiments, conductive pattern 104a may include ground selection line (GSL), string selection line (SSL) and position Wordline between GSL and SSL.

Spacer 110 may include the first spacer 110a and the second spacer 110b.

Referring to Fig. 3 and Fig. 4, the first spacer 110a be can be set on the wall of upper ladder, contact in a second direction Uppermost ladder the corresponding pad area in upper surface.Here, upper ladder can refer to and be formed with thereon the single order of spacer Ladder is adjacent and is located at than the ladder at the ladder higher level.For example, the first spacer 110a can be set in a first direction On upper ladder wall on.First spacer 110a can longitudinally extend in a second direction.

Second spacer 110b can be set on the wall of upper ladder, contact with it is uppermost positioned in a second direction The corresponding pad area in the upper surface of ladder below ladder.Second spacer 110b can be separately positioned on ladder in first party On upward wall and on the wall in a second direction of ladder.Referring to Fig. 3, the second spacer 110b may include in second direction The second part that the upper first part longitudinally extended and the end from first part longitudinally extend in a first direction.In plan view In, the second spacer 110b can have curved shape at the part that first part and second part intersect.For example, first Divide and the intersection of second part can form right angle.

Pad conductive pattern 112a and 112b can be set to upper with the end of corresponding conductive pattern 104a or marginal portion Surface contact.Pad conductive pattern 112a and 112b can be separated with the wall of upper ladder, contact corresponding pad area.For example, pad Conductive pattern 112a and 112b can be separated and be electrically isolated with the side wall of adjacent upper ladder and downstairs, so that pad conductive pattern The lower surface of case 112a and 112b can only contact the marginal portion of corresponding conductive pattern 104a, and pad conductive pattern 112a and The side wall of 112b can not contact the side wall of adjacent conductive patterns 104a.When watching in the plan view, conductive pattern 112a is padded The edge of corresponding conductive pattern 104a can not extended across in the first direction and a second direction with 112b.

In some embodiments, pad conductive pattern 112a and 112b may include polysilicon.In some embodiments, pad is led Electrical pattern 112a and 112b may include can be by metal or metallic compound that dry etching is readily removable.For example, pad Conductive pattern 112a and 112b may include titanium, titanium nitride, tantalum or tantalum nitride.

In some embodiments, pad conductive pattern 112a and 112b may include material identical with conductive pattern 104a. In some embodiments, pad conductive pattern 112a and 112b may include the material different from conductive pattern 104a.

As an example, conductive pattern 104a and pad conductive pattern 112a and 112b may include polysilicon.As another Example, conductive pattern 104a may include polysilicon, and pad conductive pattern 112a and 112b may include titanium, titanium nitride, tantalum, nitridation Tantalum or tungsten.

In some embodiments, pad conductive pattern 112a and 112b can be set to separate with spacer 110.For example, Pad conductive pattern 112a and 112b can be separated with spacer 110 in the first direction and a second direction.

Pad conductive pattern 112a and 112b may include the first pad conductive pattern far from the first spacer 110a setting 112a and the second pad conductive pattern 112b being arranged far from the second spacer 110b.Corresponding conductive pattern 104a can be exposed to the One pad conductive pattern 112a and the first spacer 110a between and second pad conductive pattern 112b and the second spacer 110b it Between.When watching in the plan view, conductive pattern 104a's pads between conductive pattern 112a and the first spacer 110a first The shape of exposed upper surface and being padded between conductive pattern 112b and the second spacer 110b cruelly second for conductive pattern 104a The shape of the upper surface of dew can be different from each other.Conductive pattern 104a's pads conductive pattern 112a and the first spacer first The upper surface of exposure can have the shape longitudinally extended in a second direction between 110a.Conductive pattern 104a's pads second The upper surface of exposure can have curved shape between conductive pattern 112b and the second spacer 110b, and be included in first party The upward part longitudinally extended and the part longitudinally extended in a second direction.For example, conductive pattern 104a's leads in the second pad The upper surface of exposure can have the first part at right angle of shape each other and the between electrical pattern 112b and the second spacer 110b Two parts.

In some embodiments, the area of the upper surface of the first pad conductive pattern 112a can be equal to the second pad conductive pattern The area of the upper surface of 112b.In this case, the upper surface of the pad area below conductive pattern 112b is padded positioned at second Area can be greater than the area of the upper surface for the pad area being located at below the first pad conductive pattern 112a.In some embodiments, The area of the upper surface of first pad conductive pattern 112a can be different from the second pad area of upper surface of conductive pattern 112b.Nothing By which kind of situation, the area of the upper surface of the pad area below the first pad conductive pattern 112a can be greater than corresponding first pad The area of conductive pattern 112a, and the area of the upper surface of the pad area below the second pad conductive pattern 112b can be big In the area of corresponding second pad conductive pattern 112b.

In some embodiments, thickness in each of the first pad conductive pattern 112a and the second pad conductive pattern 112b can With 0.5 times of thickness more than or equal to each conductive pattern 104a, and can be less than conductive pattern structure 106a the The height of a ladder on one direction.In some embodiments, the height of a ladder in a first direction can be two The combined altitudes that a insulating pattern 102a and two conductive pattern 104a is stacked.

Mask pattern 116a can be set on pad conductive pattern 112a and 112b, and can cover pad conductive pattern The upper surface of 112a and 112b.In some embodiments, mask pattern 116a may include relative to pad conductive pattern 112a and 112b, conductive pattern 104a and insulating pattern 102a have the material of high etch-selectivity.Mask pattern 116a may include Nitride, for example, silicon nitride.In this case, mask pattern 116a may be used as etch stop pattern.

In some embodiments, mask pattern 116a may include such as silica.

The insulating pattern in conductive pattern structure 106a can be set in upper pad conductive pattern 113a and mask pattern 116a On uppermost insulating pattern 102a in 102a.For example, upper pad conductive pattern 113a can be formed in uppermost insulation figure On the entire upper surface of case 102a, mask pattern 116a can be formed on pad conductive pattern 113a.Upper pad conductive pattern 113a can be set to the illusory conductive pattern not used substantially in operation.

The shape of the shape of mask pattern 116a and the first pad conductive pattern 112a and the second pad conductive pattern 112b can To be changed according to etch process.

For example, as shown in fig. 1, mask pattern 116a can not cover the top of spacer 110.In this case, Pad conductive pattern 112a and 112b and mask pattern 116a can be provided only on conductive pattern 104a.

In some embodiments, as shown in Figure 2 A, mask pattern 116a can cover one of the top of spacer 110 Point.For example, pad conductive pattern 112a and 112b and mask pattern 116a can be formed in conductive pattern 104a upper surface and On the upper surface of spacer 110.

In some embodiments, as shown in Figure 2 A, the conduction between conductive pattern 112a and 112b and spacer 110 is padded Pattern 104a can be exposed.In other embodiments, as shown in Figure 2 B, it is located at pad conductive pattern 112a and 112b and interval The thickness (thickness in vertical direction or third direction) of conductive pattern 104a between part 110 can reduce.Other In embodiment, as shown in FIG. 2 C, pad conductive pattern 112a and 112b it is a part of can be retained in pad conductive pattern 112a and Between 112b and spacer 110, padding conductive pattern 104a between conductive pattern 112a and 112b and spacer 110 can not be by Exposure.

Interlayer insulating film 120 can be set to covering conductive pattern structure 106a on first.For example, layer insulation on first Layer 120 can be set to top surface and the side surface, the top surface of spacer 110 and side table of covering conductive pattern structure 106a Face, the top surface of the side surface of upper pad conductive layer 113 and mask pattern 116a and side surface.Interlayer insulating film 120 on first Upper surface can be flat.Interlayer insulating film 120 may include such as silica on first.As used herein, art Language " flat " can refer to surface flat and along the formation of single plane.The upper surface of interlayer insulating film 120 can be put down on first Row is in the upper surface of substrate 100.

Channel structure 128 can be set to penetrate on first interlayer insulating film 120 and conductive pattern structure 106a to be electrically connected It is connected to substrate 100.For example, channel structure 128 can be set to penetrate interlayer insulating film 120 on first, mask pattern 116a, on The pad conductive pattern 113a and insulating pattern 102a and conductive pattern 104a being alternately stacked.Channel structure 128 can be set In the part of not formed ladder in conductive pattern structure 106a.

In some embodiments, semiconductor pattern 122 can be set between substrate 100 and channel structure 128.Semiconductor Pattern 122 may include such as monocrystalline silicon or polysilicon.The lower surface of semiconductor pattern 122 can be contacted with substrate 100.

Channel structure 128 may include dielectric structure 124a, channel 124b and buried insulation pattern 124c and upper conduction Pattern 126.Channel 124b can have hollow cylindrical shape or cup-like shape.Channel 124b may include polysilicon or monocrystalline Silicon.Buried insulation pattern 124c can fill the inside of channel 124b.Dielectric structure 124a can have covering channel 124b's The shape of lateral wall.Although not shown in FIG. 1, dielectric structure 124a may include leading from the lateral wall direction of channel 124b Tunnel insulation layer, charge storage layer and the barrier layer that electrical pattern 104a sequence stacks.Upper conductive pattern 126 can be set in dielectric On structure 124a, channel 124b and buried insulation pattern 124c.

Interlayer insulating film 130 can be set on first on interlayer insulating film 120 on second.Interlayer insulating film on second Interlayer insulating film 120 may be collectively termed as interlayer insulating film 132 on 130 and first.In some embodiments, interlayer is exhausted on first Interlayer insulating film 130 can be set to an interlayer insulating film in edge layer 120 and second.

Contact plug 134 can be set to penetrate on first interlayer insulating film 130 on interlayer insulating film 120 and second and cover Mould pattern 116a is with the upper surface of engagement pad conductive pattern 112a and 112b.In some embodiments, contact plug 134 can be set On pad the conductive pattern 112a and 112b of each level.For example, contact plug 134 can be set in stair-stepping conductive pattern The upper surface of engagement pad conductive pattern 112a and 112b at each step of structure 106a.In some embodiments, contact plug 134 It may include barrier metal pattern and metal pattern.

The lower surface of contact plug 134 can be set pad conductive pattern 112a and 112b upper surface on or in (for example, setting Set on the upper surface of the composite structure of pad conductive pattern 112a and 112b and conductive pattern 104a below or in).Therefore, The height (height on third direction) in the region that the lower surface of contact plug 134 is located at can be relative to the upper of substrate 100 Surface increases, and therefore, the height (height on third direction) of contact plug 134 can reduce.Therefore, process margin can increase Greatly, allow to reduce the contact failure of contact plug 134.

In addition, contact plug 134 can penetrate mask pattern 116a.Because mask pattern 116a is arranged to etch stop Layer, so the lower surface of contact plug 134 can be readily formed on pad conductive pattern 112a and 112b.Therefore, it is possible to reduce The contact of contact plug 134 is failed.

The upper table for being electrically connected to contact plug 134 on interlayer insulating film 130 on second can be set in wiring (not shown) Face.Wiring can extend in a second direction.

Fig. 5 to Figure 18 is the cross-sectional view for showing the method for manufacturing vertical semiconductor device according to example embodiment, plane Figure and perspective view.Fig. 5, Fig. 7, Fig. 8, Figure 11 to Figure 14, Figure 16 and Figure 18 be cross-sectional view.Figure 10, Figure 15 and Figure 17 are plan views. Fig. 6 and Fig. 9 is perspective view.

Referring to figure 5 and figure 6, wherein insulating layer 102 and conductive layer 104 can be made to be alternately stacked into initial in substrate 100 Conductive pattern structure 106 is formed as having stairstepping in its at the edge part.For example, insulating layer 102 and conductive layer 104 can be with With with the length for increasing at a distance from third direction between substrate 100 in insulating layer 102 and conductive layer 104 and gradually shortening Degree.It can be in the upper surface of the at the edge part of initial conduction patterning 106 exposure conductive layer 104.It can be in initial conduction Insulating layer 102 is formed at the uppermost layer of patterning 106.For example, the nethermost layer of initial conduction patterning 106 and Every layer in uppermost layer can be insulating layer 102.

Specifically, insulating layer 102 and conductive layer 104 can alternately and be repeatedly stacked in substrate 100.In some implementations In example, insulating layer 102 can be formed by silica or such as oxide material of silicon oxide carbide or fluorine silica.In some realities It applies in example, conductive layer 104 can be formed by polysilicon.In some embodiments, conductive layer 104 can be by that can be lost by dry method It carves the metal being readily removable or metallic compound is formed.For example, conductive layer 104 may include titanium, titanium nitride, tantalum or nitridation Tantalum.

Can stepwise etching isolation layer 102 and conductive layer 104 part, allow to initial conduction patterning 106 are formed as stairstepping in its at the edge part.In some embodiments, the formation of initial conduction patterning 106 can be made To have stairstepping in a first direction and in a second direction.

For example, the part of conductive layer 104 and insulating layer 102 can be etched in order to form initial conduction patterning 106, Allow to be formed separation groove to form ladder in a second direction.Thereafter, conductive layer 104 and insulation can sequentially be etched The part of layer 102 to form ladder in a first direction.Therefore, conductive layer 104 and insulating layer 102 can be by separating groove There is stairstepping in a first direction and in a second direction.

As another example, in order to form initial conduction patterning 106, conductive layer 104 and insulating layer 102 can be etched Part in a first direction have stairstepping.Thereafter, it can etch sudden and violent at each ladder formed in a first direction The conductive layer 104 of dew and the part of insulating layer 102, to have stairstepping in a second direction.

It, can be by the upper surface of each conductive layer 104 of exposure at each ladder in initial conduction patterning 106 It is set as initial pad area.Initial pad area can be set as including leading in a memory cell by subsequent technique The pad area of electrical pattern.

It in some embodiments, as shown in the figure, can shape in a first direction in initial conduction patterning 106 At ladder in include two conductive layers 104.In such a case, it is possible to form two ladders in a second direction.When When the quantity for the ladder that two sides are upwardly formed increases, the quantity including the conductive layer 104 in a ladder in a first direction It can increase.However, unrestricted with the quantity of the ladder formed in each direction in second direction in a first direction.

It in some embodiments, as shown in the figure, can be at the topmost of initial conduction patterning 106 in first party It include a conductive layer 104 in a upward ladder.

Referring to Fig. 7, spacer layers 108 can be formed to cover upper surface and the side wall of initial conduction patterning 106.

Spacer layers 108 can be by relative to conductive layer 104 there is the material of etching selectivity to be formed.In some embodiments In, spacer layers 108 can be formed by the nitride of such as silicon nitride.In some embodiments, spacer layers 108 may include Silica.

Referring to Fig. 8 to Figure 10, spacer layers 108 can be etched anisotropically through to be formed and cover initial conduction patterning The spacer 110 of 106 side wall.

It can be formed on the wall of each ladder of the step shape part (or marginal portion) of initial conduction patterning 106 Spacer 110, to cover the part corresponding with the wall of each ladder of conductive layer 104 and insulating layer 102.Furthermore it is possible to exposure With the conductive layer 104 corresponding with the adjacent upper surface of each ladder of spacer 110 of initial conduction patterning 106.One In a little embodiments, a part of of the upper surface of conductive layer 104 can be covered by spacer 110.

Spacer 110 may include the first spacer 110a and the second spacer 110b.

Can form the first spacer 110a on the wall of upper ladder, the first spacer 110a contact in second party The corresponding initial pad area in the upper surface of upward uppermost ladder.For example, can be on the wall of ladder in a first direction First spacer 110a is set.

Can form the second spacer 110b on the wall of upper ladder, the second spacer 110b contact be located at the The corresponding initial pad area in upper surface of the ladder below uppermost ladder on two directions.It can respectively in a first direction Ladder wall and second direction on ladder wall on the second spacer 110b is set.

In the plan view, the first spacer 110a can be formed as longitudinal extension in a second direction, the second spacer 110b It may include that the first part longitudinally extended in a second direction and the end from first part are bent and along first along first direction The second part that direction longitudinally extends.

Referring to Fig.1 1, pad conductive layer 111 can be formed to cover initial conduction patterning 106 and spacer 110.It can be with Pad conductive layer 111 is formed along the surface profile of initial conduction patterning 106 and spacer 110.

In some embodiments, pad conductive layer 111 can be formed by polysilicon.In some embodiments, pad conductive layer 111 It can be formed by the material that can be readily removable by dry etching.For example, pad conductive layer 111 may include titanium, titanium nitride, Tantalum or tantalum nitride.

In some embodiments, pad conductive layer 111 may include material identical with conductive layer 104.In some embodiments In, pad conductive layer 111 may include the material different from conductive layer 104.

Pad conductive pattern can be set by pad conductive layer 111 by subsequent technique.When pad conductive layer 111 is thin, connect Touching nargin can reduce due to thin pad conductive layer 111.When pad conductive layer 111 is thick, can be difficult to adjust going for pad conductive layer 111 Except thickness.In some embodiments, pad conductive layer 111 can be greater than or equal to 0.5 times of the thickness thickness of conductive layer 104, and It can be thinner than the height of a ladder on first direction.In some embodiments, the height of a ladder on first direction It can be the combined altitudes that two insulating layers 102 and two conductive layers 104 stack.

Referring to Fig.1 2, initial mask layer can be formed on pad conductive layer 111.It can make the flat upper of initial mask layer Surface A is selectively hardened to form mask layer 114.Mask layer can be conformally formed along the surface profile of pad conductive layer 111 114。

Mask layer 114 can be by relative to pad conductive layer 111 there is the insulating materials of high etch-selectivity to be formed.

In some embodiments, mask layer 114 can be formed by the nitride of such as silicon nitride.When mask layer 114 includes When nitride, mask layer 114 can have high etch-selectivity relative to silica.Therefore, mask layer 114 can connect in formation It is used as etching stopping layer in the subsequent technique of contact hole.

In some embodiments, initial mask layer may include the silicon nitride comprising hydrogen.Select the surface of initial mask layer The technique of selecting property hardening may include such as plasma-treating technology.It, can be to first when executing plasma-treating technology The flat upper surfaces A of beginning mask layer carries out corona treatment.When executing plasma-treating technology, initial mask layer is put down Smooth upper surface A can be plasma treated, and the initial mask layer on spacer 110 can not be plasma treated.It is logical Corona treatment is crossed, can remove includes hydrogen in silicon nitride in the flat upper surfaces A of initial mask layer, to make just The hardening of beginning mask layer.However, relatively great amount of hydrogen may include the silicon nitride in the surface of the initial mask layer on spacer 110 In.For example, the surface of the initial mask layer on spacer 110 can not be hardened.Initial mask layer on spacer 110 can be with Between adjacent flat upper surfaces A.Initial mask layer on spacer 110 may include horizontal component and vertical component two Person, and flat upper surfaces A can only have horizontal component.

In some embodiments, mask layer 114 may include silica.In such a case, it is possible to pass through plasma Silica in flat upper surfaces A of the treatment process to make initial mask layer is hardened to form mask layer 114.

Referring to Fig.1 3, it can be with the uncured part of etching mask layer 114, to form original mask pattern 116.Pass through etching The part comprising hydrogen of technique, mask layer 114 can have relatively high etch-rate.In the etch process, it can etch and cover Part on the pad conductive layer 111 of mold layer 114 being located on spacer 110.

In some embodiments, original mask pattern 116 can have the shape of the flat upper surfaces of covering pad conductive layer 111 Shape.The part on spacer 110 of pad conductive layer 111 can be exposed.

Original mask pattern 116 can be used as etching mask to etch pad conductive layer 111 in 4 and Figure 15 referring to Fig.1 Exposed part allows pad conductive layer 111 to be separated into each layer.It therefore, can be with the upper surface of each ladder accordingly Initial pad conductive pattern 112 is formed on each conductive layer 104.

In the etch process, at least part on spacer 110 of pad conductive layer 111 can be removed.Furthermore it is possible to The conductive layer 104 positioned at 111 lower section of pad conductive layer is not removed in the etch process.

In some embodiments, initial pad conductive pattern can be formed on the upper surface of the marginal portion of conductive layer 104 112。

In some embodiments, the pad conductive layer 111 on spacer 110 can be removed, to form initial pad conductive pattern 112.Therefore, initially pad conductive pattern 112 can be set distance interval part 110 at a certain distance from.

As shown in Figure 15, initially pad conductive pattern 112 may include first be arranged far from the first spacer 110a The second part for dividing and being arranged far from the second spacer 110b.

The upper pad being formed on the uppermost part of initial conduction patterning 106 can not be removed in the etch process Conductive layer 113 and original mask pattern 116.Therefore, upper pad conductive layer 113 and original mask pattern 116, which can cover, initially leads The uppermost insulating layer 102 of electrical pattern structure 106.It can set illusory for upper pad conductive layer 113 by subsequent technique Conductive pattern.

The work below can be changed according to the shape of original mask pattern 116 and the etching degree of pad conductive layer 111 The shape of the pad conductive pattern formed in skill.

For example, original mask pattern 116 can not cover spacer 110.In this case, as shown in fig. 1, pad is led Electrical pattern 112a and mask pattern 116a can be made only on conductive pattern 104a.For example, as shown in Fig. 2A to Fig. 2 C, In In the case that original mask pattern 116 covers the top of spacer 110, pad conductive pattern 112a and mask pattern 116a can be with shape At on the upper surface of conductive pattern 104a and the upper surface of spacer 110.

For example, etching pad conductive layer 111 technique in, can make conductive layer 104 initially pad conductive pattern 112 and Exposure between spacing body 110.In some embodiments, in the technique of etching pad conductive layer 111, conductive layer 104 can be removed In the part initially between pad conductive pattern 112 and spacer 110, so that a part of of conductive pattern 104a can be as in Fig. 2 B It is shown thinning.In other embodiments, as shown in FIG. 2 C, according to the technique of etching pad conductive layer 111, pad conductive layer can be made 111 a part is retained between initial pad conductive pattern 112 and spacer 110, so that the thin of pad conductive pattern 112a is dashed forward Part can be with contact spacer 110 out.

Referring to Fig.1 6, interlayer insulating film 120 can be formed on first to cover initial conduction patterning 106.For example, can Top surface and the side surface, spacer 110 of initial conduction patterning 106 are covered with interlayer insulating film 120 in formation first Top surface and side surface, the top surface of the side surface of upper pad conductive layer 113 and mask pattern 116a and side surface.On first The upper surface of interlayer insulating film 120 can be flat.

It in some embodiments, can be by forming the oxide skin(coating) including silica, silicon oxide carbide or fluorine silica simultaneously And make oxide skin(coating) planarization to form interlayer insulating film 120 on first.Flatening process may include chemically mechanical polishing work Skill and/or etch-back technics.

Thereafter, channel hole can be formed to penetrate interlayer insulating film 120 and initial conduction patterning 106 on first, come Exposure substrate 100.Channel structure 128 can be formed in each channel hole respectively.It in some embodiments, can be in channel junction The semiconductor pattern 122 of contact substrate 100 is formed below structure 128.Thereafter, can on first interlayer insulating film 120 and initial Interlayer insulating film 130 on second is formed in conductive pattern structure 106.The upper surface of interlayer insulating film 130 can be flat on second Smooth.

Specifically, semiconductor can be formed by executing selective epitaxial process to the substrate 100 exposed by channel hole Pattern 122.Can be formed on semiconductor pattern 122 including dielectric structure 124a, channel 124b, buried insulation pattern 124c and The channel structure 128 of upper conductive pattern 126.Interlayer insulating film 130 on second can be formed on interlayer insulating film 120 on first To cover interlayer insulating film 120 on channel structure 128 and first.

Referring to Fig.1 7, can be etched anisotropically through on first on interlayer insulating film 120 and second interlayer insulating film 130 with And initial conduction patterning 106, to form the opening 136 longitudinally extended in a first direction.Can be formed opening 136 so that The cell block of memory device separates.

Therefore, initial conduction patterning 106 can be divided to form conduction at every side in the opposite side of opening 136 Patterning 106a.Conductive pattern structure 106a can longitudinally extend in a first direction.136 exposure substrate of opening can be passed through 100 upper surface.Conductive pattern structure 106a may include insulating pattern 102a and conductive pattern 104a.

In some embodiments, as shown in Figures 3 and 4, pad area can be set in the every of conductive pattern structure 106a On the upper surface of a ladder.When forming opening 136, initial pad conductive pattern 112 and original mask pattern can be etched together 116 pad conductive pattern 112a and 112b and mask pattern 116a to be formed.Furthermore it is possible to be cut by forming opening 136 Spacer 110.

In conductive pattern structure 106a, pad conductive pattern 112a and 112b may include setting far from the first spacer 110a The the first pad conductive pattern 112a set and the second pad conductive pattern 112b far from the second spacer 110b setting.

Because the second spacer 110b is formed on the wall of ladder in the first direction and a second direction, the second interval The area of the upper surface of the covering conductive pattern 104a of part 110b, which can be greater than, to be formed on the wall of the ladder on only first direction The first spacer 110a covering conductive pattern 104a upper surface area.

In some embodiments, the area of the upper surface of the second pad conductive pattern 112b can be with the first pad conductive pattern The area of the upper surface of 112a is identical.For this purpose, the area of the adjustable pad area being located at below the second pad conductive pattern 112b. It is led for example, the length of the pad area being located at below the second pad conductive pattern 112b in a second direction can be greater than positioned at the first pad The length of pad area in a second direction below electrical pattern 112a.

In some embodiments, the area of the upper surface of the second pad conductive pattern 112b can be with the first pad conductive pattern The area of the upper surface of 112a is different.

Referring to Fig.1 8, contact plug 134 can be formed to penetrate on first interlayer insulating film on interlayer insulating film 120 and second 130, come engagement pad conductive pattern 112a and 112b.In the etch process for being used to form contact plug 134, it is conductive that pad can be used Mask pattern 116a on pattern 112a and 112b is as etching mask.

Specifically, can etch on first on interlayer insulating film 120 and second interlayer insulating film 130 keeps pad conductive to be formed The initial contact hole of the upper surface exposure of mask pattern 116a on pattern 112a and 112b.Mask pattern 116a work can be used Interlayer insulating film 130 on interlayer insulating film 120 and second is etched on first for etching mask.Thereafter, mask artwork can be removed Case 116a by initial contact hole exposure part, allow to contact hole be formed as exposure pad conductive pattern 112a and 112b.On the inner surface that barrier metal layer is formed in contact hole and then formed on barrier metal layer metal layer it Afterwards, barrier metal layer and metal layer can be made to be planarized to expose the upper surface of interlayer insulating film 130 on second.

Because using mask pattern 116a as etching mask to form the upper surface for making to pad conductive pattern 112a and 112b Exposed contact hole, it is possible to prevent the not flaws of contact hole (that is, the upper surface of pad conductive pattern 112a and 112b are not By contact holes exposing).

The bottom surface of contact hole can be located at pad conductive pattern 112a and 112b upper surface on or in (for example, be located at pad On the upper surface of the composite structure of conductive pattern 112a and 112b and conductive pattern 104a below or in).Therefore, it is used for shape It can increase since the depth of contact hole reduces at the etching nargin of contact hole.That is, because pad conductive pattern 112a and 112b It is arranged on conductive pattern 104a, it is possible to reduce the contact failure of contact plug 134.

In some embodiments, in the case where mask pattern 116a includes silica, on mask pattern 116a and first Interlayer insulating film 120 can be merged into single insulating layer.

Wiring can be formed on interlayer insulating film 130 on second to be electrically connected to contact plug 134.Wiring can have The linearity configuration that second party upwardly extends.

Figure 19 to Figure 21 is the cross-sectional view for showing the method for manufacture vertical semiconductor device according to example embodiment.

Other than the method for being used to form mask pattern, the side of manufacture vertical semiconductor device according to example embodiment Method is identical as the method described referring to Fig. 5 to Figure 18.

Technique identical with the technique described referring to Fig. 5 to Figure 11 can be executed to form pad conductive layer 111.

Referring to Fig.1 9, mask layer 140 can be formed on pad conductive layer 111 to cover 106 He of initial conduction patterning Spacer 110.Mask layer 140 can be formed along the surface profile of pad conductive layer 111.Mask layer 140 may include flat And sloping portion.The part on spacer 110 of mask layer 140 can be sloping portion.In mask layer 140, flat part Dividing can be thicker than sloping portion.In some embodiments, the flat of mask layer 140 can have first thickness, mask layer 140 sloping portion can have the second thickness smaller than first thickness.It can be on third direction from the following table of mask layer 140 Face measures the thickness of flat to upper surface.It can be at a certain angle (for example, unanimously with inclination) from the following table of mask layer 140 Face measures the thickness of sloping portion to upper surface.

In some embodiments, mask layer 140 may include silicon nitride.In some embodiments, mask layer 140 can wrap Include silica.

Referring to Figure 20, original mask pattern can be formed at least part of the sloping portion of etching mask layer 140 140a.Etch process may include isotropic etching.In the etch process, mask layer 140 can be made to be etched at least Second thickness.

When executing etch process, the relatively thick flat that is formed as of mask layer 140 can be made to retain predetermined thickness, And the sloping portion of mask layer 140 can be removed.Therefore, original mask pattern 140a can cover the flat of pad conductive layer 111 Smooth upper surface.Furthermore, it is possible to a part on spacer 110 of exposure pad conductive layer 111.

Thereafter, the technique essentially identical with the technique of referring to Fig.1 4 to Figure 18 descriptions can be executed.Therefore, figure can be manufactured 1 to vertical semiconductor device shown in Fig. 4.

Figure 22 is the cross-sectional view for showing vertical semiconductor device according to example embodiment.

Referring to Figure 22, in addition to upper pad conductive pattern 113a and mask pattern 116a not set in conductive pattern structure it Outside, vertical semiconductor device according to example embodiment and the vertical semiconductor device described referring to figs. 1 to Fig. 4 are essentially identical.

Insulating pattern 102a can be set at the uppermost layer of conductive pattern structure 106a.In conductive pattern structure Insulating pattern 102a at the uppermost layer of 106a can be thicker than other insulating pattern 102a below.In the implementation of Figure 22 In example, interlayer insulating film 120 can not cover the uppermost layer including uppermost insulating pattern 102a on first, but can To cover the remaining step of conductive pattern structure 106a.

Figure 23 to Figure 25 is the cross-sectional view for showing the method for manufacture vertical semiconductor device according to example embodiment.

Referring to Figure 23, wherein insulating layer 102 and conductive layer 104 can be made to be stacked on the initial conduction pattern in substrate 100 Structure 106 is formed as having stairstepping in its at the edge part.It can be in the at the edge part of initial conduction patterning 106 The upper surface of exposure conductive layer 104.Insulating layer 102 can be formed at the uppermost layer of initial conduction patterning 106.In Insulating layer 102 at the uppermost layer of initial conduction patterning 106 can be thicker than other insulating layers 102 below.

Channel hole can be formed and expose the upper surface of substrate 100 to penetrate initial conduction patterning 106.It can be every Channel structure 128 is respectively formed in a channel hole.The technique for forming channel structure 128 can be with the technique base of referring to Fig.1 6 descriptions This is identical.

In some embodiments, channel structure 128 can be formed before forming initial conduction patterning 106.For example, Insulating layer 102 and conductive layer 104 alternately and are repeatedly stacked in substrate 100.Channel structure can be formed in substrate 100 128 to penetrate insulating layer 102 and conductive layer 104.Thereafter, insulating layer 102 and conductive layer 104 can be partly etched to form tool There is the initial conduction patterning 106 of stairstepping.

Referring to Figure 24, technique identical with the technique described referring to Fig. 7 to Figure 15 can be executed.It therefore, can be initial Spacer 110, initial pad conductive pattern 112 and original mask pattern 116 are formed in the stepped portion of conductive pattern structure 106. Pad conductive layer 113 and original mask pattern 116 can be formed to cover the uppermost insulation of initial conduction patterning 106 The upper surface of layer 102.

Referring to Figure 25, interlayer insulating film can be formed to cover initial conduction patterning 106.Interlayer insulating film can cover Cover upper pad conductive layer 113 and original mask pattern 116 in initial conduction patterning 106.

The top of interlayer insulating film can be removed by flatening process and positioned at initial conduction patterning 106 Upper pad conductive layer 113 and original mask pattern 116 on the part of the top.Therefore, upper pad conductive layer 113 and original mask pattern 116 can be not present in initial conduction patterning 106.As a result, the rank of covering initial conduction patterning 106 can be formed Interlayer insulating film 120 on the first of terraced part.Flatening process may include CMP process and/or etch-back technics.

Referring again to Figure 22, interlayer insulating film 130 on second can be formed on interlayer insulating film 120 on first.Thereafter, Technique identical with the technique described referring to Figure 17 and Figure 18 can be executed.Therefore, it can manufacture vertical half shown in Figure 22 Conductor device.

Figure 26 is the cross-sectional view for showing vertical semiconductor device according to example embodiment.

Referring to Figure 26, other than conductive pattern structure only has ladder in a first direction, according to example embodiment Vertical semiconductor device can be essentially identical with the vertical semiconductor device that describes referring to figs. 1 to Fig. 4.

Conductive pattern structure 107 can only have ladder in a first direction, therefore spacer 110 can be in second direction Upper longitudinal extension.In addition, conductive pattern 104a the upper surface of exposure can be between spacer 110 and pad conductive pattern 112a With the shape extended in a second direction.

It vertical can partly be led by being formed with the identical technique of technique that is described referring to Fig. 5 to Figure 18 or Figure 19 to Figure 21 Body device.However, it is possible to which conductive pattern structure 107 is formed as only in a first direction by executing photoetching and etch process With ladder.

Figure 27 is the cross-sectional view for showing vertical semiconductor device according to example embodiment.

Referring to Figure 27, other than conductive pattern structure only has ladder in a first direction, vertical semiconductor device can With essentially identical with the vertical semiconductor device referring to Figure 22 description.

Conductive pattern structure 107 can only have ladder in a first direction, therefore spacer 110 can be in second direction Upper longitudinal extension.In addition, conductive pattern 104a the upper surface of exposure can be between spacer 110 and pad conductive pattern 112a With the shape extended in a second direction.

Vertical semiconductor device can be formed by technique identical with the technique described referring to Figure 23 to Figure 25.So And conductive pattern structure 107 can be formed as to only have ladder in a first direction by executing photoetching and etch process.

Although present inventive concept, ability are specifically illustrated and described referring to the example embodiment of present inventive concept Domain ordinarily skilled artisan will understand that, the spirit and scope being defined by the following claims for not departing from the disclosure the case where Under, it can wherein make various changes in form and details.