阅读说明：本技术 一种基于低压cmos工艺的数字电平转换电路 (A kind of digital level conversion circuit based on low voltage CMOS process ) 是由 肖正 胡胜发 于 2019-09-30 设计创作，主要内容包括：本发明公开了一种基于低压CMOS工艺的数字电平转换电路,包括第一PMOS管组、第一NMOS开关管、第二NMOS开关管和反相器,所述基于低压CMOS工艺的数字电平转换电路具有第一直流电源输入端、第二直流电源输入端、数字信号输入端、第一数字信号输出端和第二数字信号输出端。本发明能够基于低压CMOS工艺实现高压输入情况下多电平输出、能够有效减小芯片面积和功耗、并且能够有效避免电路的击穿风险。(The invention discloses a kind of digital level conversion circuit based on low voltage CMOS process, including the first PMOS tube group, the first NMOS switch pipe, the second NMOS switch pipe and phase inverter, the digital level conversion circuit based on low voltage CMOS process has the first DC supply input, the second DC supply input, digital signal input end, the first digital signal output end and the second digital signal output end.The breakdown risk that the present invention can be exported based on more level in the case of low voltage CMOS process realization high input voltage, can be effectively reduced chip area and power consumption and can effectively avoid circuit.)

1. a kind of digital level conversion circuit based on low voltage CMOS process, which is characterized in that including the first PMOS tube group, first NMOS switch pipe, the second NMOS switch pipe and phase inverter, the digital level conversion circuit based on low voltage CMOS process have First DC supply input, the second DC supply input, digital signal input end, the first digital signal output end and second Digital signal output end；

The first PMOS tube group includes the first PMOS switch pipe, the second PMOS switch pipe and M to PMOS tube, each PMOS tube Source electrode is shorted with the substrate of itself, and the grid of each PMOS tube is shorted with the drain electrode of itself；Wherein, M is more than or equal to 1 Integer；

The source electrode of the first PMOS switch pipe, the source electrode of the second PMOS switch pipe and the first source electrode to PMOS tube with it is described The connection of first DC supply input；The grid of the first PMOS tube of the grid and the first side of the first PMOS switch pipe is connected It connects, the drain electrode of the first PMOS switch pipe is connect with the grid of second side most end PMOS tube；The second PMOS switch pipe Grid be connected with the grid of the first PMOS tube of second side, the drain electrode of the second PMOS switch pipe and the first side most end The grid of PMOS tube connects；The two neighboring PMOS tube of the same side is to be connected by series diode mode；

The drain electrode of the most end PMOS tube of first side, the drain electrode of the first NMOS switch pipe are believed with first number The connection of number output end, the drain electrode of the most end PMOS tube of described second side, the drain electrode of the second NMOS switch pipe with it is described The connection of second digital signal output end；The grid of the first NMOS switch pipe, the phase inverter input terminal with the number The connection of word signal input part；The output end of the phase inverter is connect with the grid of the second NMOS switch pipe；The phase inverter Power end connect with second DC supply input；The source electrode of the first NMOS switch pipe, the 2nd NMOS are opened The source electrode for closing pipe is grounded with the ground terminal of the phase inverter altogether.

2. the digital level conversion circuit according to claim 1 based on low voltage CMOS process, which is characterized in that described It further include J series diode side between the drain electrode and the drain electrode of the first NMOS switch pipe of the most end PMOS tube of first side The PMOS tube of formula connection, between the drain electrode and the drain electrode of the second NMOS switch pipe of the most end PMOS tube of described second side It further include the PMOS tube that J series diode mode connects, the source electrode of each PMOS tube is shorted with the substrate of itself, each The grid of PMOS tube is shorted with the drain electrode of itself；Wherein, J is the integer more than or equal to 0.

3. the digital level conversion circuit according to claim 1 based on low voltage CMOS process, which is characterized in that described It further include the PMOS tube that N number of series diode mode connects between first PMOS tube group and first DC supply input； Wherein, N is the integer more than or equal to 0.

4. a kind of digital level conversion circuit based on low voltage CMOS process, which is characterized in that including first resistor group, first NMOS switch pipe, the second NMOS switch pipe and phase inverter, the digital level conversion circuit based on low voltage CMOS process have First DC supply input, the second DC supply input, digital signal input end, the first digital signal output end and second Digital signal output end；

The first resistor group includes the first PMOS switch pipe, the second PMOS switch pipe and M to resistance；Wherein, M is to be greater than or wait In 1 integer；

The source electrode of the first PMOS switch pipe, the source electrode of the second PMOS switch pipe and the first first end to resistance with it is described The connection of first DC supply input；The second end of the first resistance of the grid and the first side of the first PMOS switch pipe is connected It connects, the drain electrode of the first PMOS switch pipe is connect with the second end of second side most end resistance；The second PMOS switch pipe Grid be connected with the second end of the first resistance of second side, the drain electrode of the second PMOS switch pipe and the first side most end The second end of resistance connects；The two neighboring resistance of the same side is to be connected in series；

The drain electrode of the second end of the most end resistance of first side, the first NMOS switch pipe is believed with first number The connection of number output end, the second end of the most end resistance of described second side, the second NMOS switch pipe drain electrode with it is described The connection of second digital signal output end；The grid of the first NMOS switch pipe, the phase inverter input terminal with the number The connection of word signal input part；The output end of the phase inverter is connect with the grid of the second NMOS switch pipe；The phase inverter Power end connect with second DC supply input；The source electrode of the first NMOS switch pipe, the 2nd NMOS are opened The source electrode for closing pipe is grounded with the ground terminal of the phase inverter altogether.

5. the digital level conversion circuit according to claim 4 based on low voltage CMOS process, which is characterized in that described It further include the electricity of J series connection between the second end of the most end resistance of first side and the drain electrode of the first NMOS switch pipe Resistance further includes J string between the second end of the most end resistance of described second side and the drain electrode of the second NMOS switch pipe Join the resistance of connection；Wherein, J is the integer more than or equal to 0.

6. the digital level conversion circuit according to claim 4 based on low voltage CMOS process, which is characterized in that described It further include the resistance of N number of series connection between first resistor group and first DC supply input；Wherein, N be greater than or Integer equal to 0.

Technical field

The present invention relates to electronic circuit technology fields, and in particular to digital level conversion art.

Background technique

As MOS size is smaller and smaller, the voltage that can bear is lower and lower.Only pass through suitable level shifting circuit Just it is able to achieve effective control of the low pressure digital circuit to high-tension circuit module.Metal-oxide-semiconductor needs to bear in traditional level shifting circuit Maximum voltage be equal to supply voltage, so supply voltage not above metal-oxide-semiconductor safe voltage, otherwise will lead to metal-oxide-semiconductor breakdown.

Summary of the invention

Technical problem to be solved by the present invention lies in provide a kind of digital level conversion electricity based on low voltage CMOS process Road, the output of more level can be realized based on low voltage CMOS process, can effectively reduce chip area and power consumption and can be effective Avoid the breakdown risk of circuit.

In order to solve the above-mentioned technical problems, the present invention provides a kind of, and the digital level based on low voltage CMOS process converts electricity Road, including the first PMOS tube group, the first NMOS switch pipe, the second NMOS switch pipe and phase inverter, it is described to be based on low voltage CMOS work The digital level conversion circuit of skill have the first DC supply input, the second DC supply input, digital signal input end, First digital signal output end and the second digital signal output end；

The first PMOS tube group includes the first PMOS switch pipe, the second PMOS switch pipe and M to PMOS tube, each PMOS The source electrode of pipe is shorted with the substrate of itself, and the grid of each PMOS tube is shorted with the drain electrode of itself；Wherein, M be greater than or Integer equal to 1；

The source electrode of the first PMOS switch pipe, the source electrode of the second PMOS switch pipe and the first source electrode to PMOS tube with The first DC supply input connection；The grid of the first PMOS tube of the grid and the first side of the first PMOS switch pipe It is connected, the drain electrode of the first PMOS switch pipe is connect with the grid of second side most end PMOS tube；2nd PMOS is opened The grid for closing pipe is connected with the grid of the first PMOS tube of second side, and the drain electrode of the second PMOS switch pipe and the first side are most The grid connection of last PMOS tube；The two neighboring PMOS tube of the same side is to be connected by series diode mode；

The drain electrode of the most end PMOS tube of first side, the drain electrode of the first NMOS switch pipe are counted with described first Word signal output end connection, the drain electrode of the most end PMOS tube of described second side, the drain electrode of the second NMOS switch pipe with The second digital signal output end connection；The grid of the first NMOS switch pipe, the phase inverter input terminal and institute State digital signal input end connection；The output end of the phase inverter is connect with the grid of the second NMOS switch pipe；It is described anti- The power end of phase device is connect with second DC supply input；The source electrode of the first NMOS switch pipe, described second The source electrode of NMOS switch pipe is grounded with the ground terminal of the phase inverter altogether.

Further, first side most end PMOS tube drain electrode and the drain electrode of the first NMOS switch pipe it Between further include PMOS tube that J series diode mode connects, described second side most end PMOS tube drain electrode with it is described It further include the PMOS tube that J series diode mode connects, the source electrode of each PMOS tube between the drain electrode of second NMOS switch pipe It is shorted with the substrate of itself, the grid of each PMOS tube is shorted with the drain electrode of itself；Wherein, J is whole more than or equal to 0 Number.

It further, further include N number of connect between the first PMOS tube group and first DC supply input The PMOS tube of diode fashion connection；Wherein, N is the integer more than or equal to 0.

Digital level in order to solve identical technical problem, the present invention also provides another kind based on low voltage CMOS process Conversion circuit, including first resistor group, the first NMOS switch pipe, the second NMOS switch pipe and phase inverter, it is described to be based on low pressure The digital level conversion circuit of CMOS technology has the first DC supply input, the second DC supply input, digital signal Input terminal, the first digital signal output end and the second digital signal output end；

The first resistor group includes the first PMOS switch pipe, the second PMOS switch pipe and M to resistance；Wherein, M be greater than Or the integer equal to 1；

The source electrode of the first PMOS switch pipe, the source electrode of the second PMOS switch pipe and the first first end to resistance with The first DC supply input connection；The second end of the first resistance of the grid and the first side of the first PMOS switch pipe It is connected, the drain electrode of the first PMOS switch pipe is connect with the second end of second side most end resistance；2nd PMOS is opened The grid for closing pipe is connected with the second end of the first resistance of second side, and the drain electrode of the second PMOS switch pipe and the first side are most The second end connection of last resistance；The two neighboring resistance of the same side is to be connected in series；

The drain electrode of the second end of the most end resistance of first side, the first NMOS switch pipe is counted with described first Word signal output end connection, the second end of the most end resistance of described second side, the second NMOS switch pipe drain electrode with The second digital signal output end connection；The grid of the first NMOS switch pipe, the phase inverter input terminal and institute State digital signal input end connection；The output end of the phase inverter is connect with the grid of the second NMOS switch pipe；It is described anti- The power end of phase device is connect with second DC supply input；The source electrode of the first NMOS switch pipe, described second The source electrode of NMOS switch pipe is grounded with the ground terminal of the phase inverter altogether.

Compared with the prior art, the invention has the following beneficial effects:

1, the present invention can realize more level outputs based on low voltage CMOS process.

2, the present invention only needs lesser chip area and lower power consumption.

3, the present invention does not need any external reference voltage.

4, breakdown risk is not present when input is any level in the present invention.

5, the present invention is suitable for KHz or less rank level conversion function, need to properly increase static state when conversion rate improves Power consumption.Metal-oxide-semiconductor high-voltage breakdown risk is not present when inputting constant.

Detailed description of the invention

Fig. 1 is level shifting circuit schematic diagram in the prior art；

Fig. 2 is the circuit signal for the digital level conversion circuit based on low voltage CMOS process that one embodiment of the invention provides Figure；

Fig. 3 is another circuit for the digital level conversion circuit based on low voltage CMOS process that one embodiment of the invention provides Schematic diagram；

Fig. 4 is the another circuit for the digital level conversion circuit based on low voltage CMOS process that one embodiment of the invention provides Schematic diagram；

Fig. 5 is the another circuit for the digital level conversion circuit based on low voltage CMOS process that one embodiment of the invention provides Schematic diagram；

Fig. 6 is the another circuit for the digital level conversion circuit based on low voltage CMOS process that one embodiment of the invention provides Schematic diagram.

Specific embodiment

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.