阅读说明：本技术 复杂可程序逻辑装置及其运作方法 (Complex programmable logic device and operation method thereof ) 是由 詹鹏 于 2019-08-30 设计创作，主要内容包括：本发明公开了一种复杂可程序逻辑装置,包括串行通用输入输出(SGPIO)解析电路、集成电路总线(I2C)解析电路及第一多工器。SGPIO解析电路具有多个端口解析电路、检测电路及处理电路。各个端口解析电路接收输入信号且输出第一数据。检测电路检测第一个端口解析电路的输入信号以输出检测信号。处理电路依据检测信号撷取至少一部分的端口解析电路所输出的第一数据的端口数据作为第一控制信号。I2C解析电路解析数据流以根据关联于地址信息的地址命令、控制命令及输入数据而输出第二控制信号。第一多工器依据侦测信号选择输出第一控制信号或第二控制信号。本发明还公开一种复杂可程序逻辑装置的运作方法。(The invention discloses a complex programmable logic device which comprises a Serial General Purpose Input and Output (SGPIO) analysis circuit, an integrated circuit bus (I2C) analysis circuit and a first multiplexer. The SGPIO analyzing circuit includes a plurality of port analyzing circuits, a detecting circuit, and a processing circuit. Each port resolution circuit receives an input signal and outputs first data. The detection circuit detects an input signal of the first port resolution circuit to output a detection signal. The processing circuit captures at least a part of the port data of the first data output by the port analysis circuit as a first control signal according to the detection signal. The I2C parsing circuit parses the data stream to output a second control signal according to an address command, a control command, and input data associated with the address information. The first multiplexer selectively outputs the first control signal or the second control signal according to the detection signal. The invention also discloses an operation method of the complex programmable logic device.)

1. A complex programmable logic device, comprising:

A serial general purpose input output parser circuit, comprising:

A plurality of port analyzing circuits, each having an input end and an output end, wherein the input end is used for receiving a first input signal, and the output end is used for outputting a first data;

The detection circuit is electrically connected with the input end of a first port analysis circuit of the port analysis circuits and detects a first input signal of the first port analysis circuit to output a detection signal; and

The processing circuit is electrically connected with the output ends of the port analysis circuits and the detection circuit, and the processing circuit captures port data of first data output by at least one part of the output ends of the port analysis circuits according to the detection signal to be used as a first control signal;

An integrated circuit bus analysis circuit for analyzing a data stream to generate an address information, a control command and an input data, and outputting a second control signal according to an address command, the control command and the input data associated with the address information; and

A first multiplexer for selectively outputting the first control signal or the second control signal according to a detection signal.

2. the complex programmable logic device of claim 1, wherein the processing circuit comprises:

A first sub-circuit having an input terminal and an output terminal, the input terminal of the first sub-circuit being electrically connected to the output terminals of the port analyzing circuits, the first sub-circuit being configured to capture port data of first data output by a part of the port analyzing circuits;

A second sub-circuit having an input terminal and an output terminal, the input terminal of the second sub-circuit being electrically connected to the output terminals of the port analyzing circuits, the second sub-circuit being configured to capture port data of the first data output by each of the port analyzing circuits; and

And the second multiplexer is electrically connected with the output end of the first sub-circuit, the output end of the second sub-circuit and the first multiplexer, and conducts the path from the output end of the first sub-circuit or the output end of the second sub-circuit to the first multiplexer according to the detection signal.

3. The apparatus of claim 2, wherein the detection signal indicates whether the first input signal of the first port resolution circuit is a four-port signal or an eight-port signal.

4. the apparatus of claim 2, wherein the detection signal indicates that the first input signal of the first port resolution circuit is an eight-port signal, and the first sub-circuit extracts all port values in the port data of the first data output by the first port resolution circuit and extracts a part of port values in the port data of the first data output by another port resolution circuit according to the detection signal.

5. The apparatus of claim 2, wherein the detection signal indicates that the first input signal of the first port resolution circuit is a four-port signal, and the second sub-circuit retrieves partial port values in port data of the first data outputted by all of the port resolution circuits according to the detection signal.

6. A method for operating a complex programmable logic device, comprising:

Respectively receiving a first input signal by a plurality of port analysis circuits and correspondingly outputting a first data;

Detecting a first input signal of a first port analysis circuit of the port analysis circuits by a detection circuit so as to output a detection signal;

Capturing port data of first data output by at least one part of the port analysis circuits by a processing circuit according to the detection signal to be used as a first control signal;

Analyzing a data stream by an integrated circuit bus circuit to generate address information, a control command and input data, and outputting a second control signal according to the address command, the control command and the input data which are related to the address information; and

A first multiplexer selectively outputs the first control signal or the second control signal according to a detection signal.

7. The method as claimed in claim 6, wherein when the detection signal indicates that the first input signal of the first port resolution circuit is an eight-port signal, the using the processing circuit to extract port data of the first data output by at least one of the port resolution circuits according to the detection signal as the first control signal comprises:

A first sub-circuit in the processing circuit captures all port values in the port data of the first data output by the first port analyzing circuit according to the detection signal, and captures a part of port values in the port data of the first data output by the other port analyzing circuit.

8. the method as claimed in claim 6, wherein when the detection signal indicates that the first input signal of the first port resolution circuit is a four-port signal, the using the processing circuit to extract port data of the first data output by at least one of the port resolution circuits according to the detection signal as the first control signal comprises:

And a second sub-circuit in the processing circuit captures partial port values in the port data of the first data output by the port analysis circuits according to the detection signal.

Technical Field

the present invention relates to a complex programmable logic device, and more particularly, to a complex programmable logic device using I2C and SGPIO parsing module.

Background

At present, a Complex Programmable Logic Device (CPLD) of a hard disk backplane mainly executes hard disk lighting, hard disk power-on and power-off control, NVME timing control, hard disk state reading and the like. However, the I2C and SGPIO parsing modules used by complex programmable logic devices are rather complex and not compact enough, resulting in insufficient use of the resources of the complex programmable logic devices. If the hard disk backplane needs to support different types of interfaces (such as SATA and NVME), a higher-end complex programmable logic device is required, which, however, leads to an increase in the use cost.

furthermore, different types of hard disk backplanes are often required to be matched with different types of complex programmable logic devices. This results in a large number of versions of the required complex programmable logic device and its firmware, resulting in high maintenance costs. Therefore, there is a need for a complex programmable logic device that can integrate different types of hard disk backplanes while meeting the functional requirements of the different types of backplanes.

Disclosure of Invention

The invention provides a complex programmable logic device, which can simultaneously realize all functions of hard disk backplanes of different types by mainly adopting a specific I2C and SGPIO analysis mode, thereby achieving the function integration of the complex programmable logic device, reducing the consumption of a large number of resources and lowering the cost.

An embodiment of the present invention discloses a complex programmable logic device, which includes a serial general purpose input/output (usb) parser circuit, an integrated circuit bus parser circuit, and a first multiplexer (multiplexer). The serial general input/output analysis circuit comprises a plurality of port analysis circuits, a detection circuit and a processing circuit. Each port resolution circuit has an input terminal for receiving a first input signal and an output terminal for outputting first data. The detection circuit is electrically connected with the input end of a first port analysis circuit of the port analysis circuits, and detects an input signal of the first port analysis circuit to output a detection signal. The processing circuit is electrically connected with the output ends of the port analyzing circuits and the detection circuit, and captures port data of the first data output by at least one part of the output ends of the port analyzing circuits according to the detection signal to be used as a first control signal. The integrated circuit bus analysis circuit is used for analyzing the data stream to generate address information, control commands and input data, and outputting second control signals according to the address commands, the control commands and the input data which are related to the address information. The first multiplexer is used for selectively outputting a first control signal or a second control signal according to the detection signal.

another embodiment of the present invention discloses a method for operating a complex programmable logic device, comprising the steps of: respectively receiving the first input signal by a plurality of port analysis circuits and correspondingly outputting first data; detecting a first input signal of a first port analysis circuit of the port analysis circuits by using a detection circuit so as to output a detection signal; capturing, by the processing circuit, port data of the first data output by at least a part of the port analyzing circuits as a first control signal according to the detection signal; analyzing the data stream with an integrated circuit bus circuit to generate address information, control commands and input data, and outputting second control signals according to the address commands, control commands and input data associated with the address information; the first multiplexer selectively outputs the first control signal or the second control signal according to the detection signal.

in summary, in the complex programmable logic device and the operating method thereof provided by the present invention, on one hand, the detection circuit in the serial general input/output analysis circuit is used to detect what the input signal of the first port analysis circuit is (for example, a four-port or eight-port signal), and the processing circuit selectively retrieves at least a portion of the port data output by the port analysis circuit according to the signal type of the input signal to output the first control signal. On the other hand, the characteristics of the multi-address response of the circuit are resolved through the integrated circuit bus to output a second control signal. By means of the two analysis functions of the SGPIO and the I2C, the complex programmable logic device can simultaneously realize all functions of different types of hard disk backplanes under simplified module configuration, so as to achieve function integration of the complex programmable logic device, thereby reducing resource consumption and reducing cost.

The above description of the present invention and the following description of the embodiments are provided to illustrate and explain the spirit and principles of the present invention and to provide further explanation of the invention as claimed in the appended claims.

Drawings

FIG. 1 is a functional block diagram of a complex programmable logic device according to an embodiment of the present invention.

FIG. 2 is a detailed functional block diagram of the complex programmable logic device according to the embodiment of FIG. 1.

FIG. 3 is a flowchart illustrating a method of operating a complex programmable logic device according to an embodiment of the present invention.

Wherein, the reference numbers:

1 Complex programmable logic device

10 serial general purpose input/output analysis circuit

101-103 port analysis circuit

104 detection circuit

105 processing circuit

1051 a first sub-circuit

1052 second sub-circuit

1053 second multiplexer

11 integrated circuit bus analysis circuit

110. 111 multi-address response circuit

12 first multiplexer

IN1 input terminal

ON1 output terminal

S1-S3 first input signal

First data D1-D3

CN1 first control Signal

CN2 second control Signal

C1, C2 data stream

DS detection signal

Detailed Description

the detailed features and advantages of the present invention are described in detail in the embodiments below, which are sufficient for anyone skilled in the art to understand the technical contents of the present invention and to implement the present invention, and the related objects and advantages of the present invention can be easily understood by anyone skilled in the art according to the disclosure of the present specification, the protection scope of the claims and the attached drawings. The following examples further illustrate aspects of the present invention in detail, but are not intended to limit the scope of the invention in any way.

Referring to fig. 1, fig. 1 is a functional block diagram of a complex programmable logic device according to an embodiment of the present invention. As shown in fig. 1, the complex programmable logic device 1 includes a serial general purpose input/output analysis circuit 10, an integrated circuit bus analysis circuit 11, and a first multiplexer 12. The serial general purpose input/output analysis circuit 10 includes a plurality of port analysis circuits 101 to 103, a detection circuit 104, and a processing circuit 105. Each port resolution circuit has an input terminal and an output terminal, wherein the input terminal is used for receiving a first input signal, and the output terminal is used for outputting first data. In practice, the complex programmable logic device 1 may be disposed on a backplane (not shown), and provides different signal analysis functions according to the interface types supported by the backplane to perform different lighting operations on the hard disk LEDs.

for the embodiment shown IN fig. 1, the port analyzing circuit 101 has an input terminal IN1 and an output terminal ON1, the input terminal IN1 receives the first input signal S1 and the output terminal ON1 outputs the first data D1. The port resolution circuit 102 has an input terminal IN2 and an output terminal ON2, the input terminal IN2 receives the first input signal S2 and the output terminal ON1 outputs the first data D2. The port resolution circuit 103 has an input terminal IN3 and an output terminal ON3, the input terminal IN3 receives the first input signal S3 and the output terminal ON3 outputs the first data D3. In practice, the port resolution circuits 101-103 may be connected to a platform Path Controller (PCH) or a Host Bus Adapter (HBA), and the first input signals S1-S3 may be serial general input output (SGPIO) signals from the platform Path Controller (PCH) corresponding to an eight port signal (8port signal) or the Host Bus Adapter (HBA) corresponding to a four port signal (4port signal).

The detection circuit 104 is electrically connected to the input terminal IN1 of a first port analyzing circuit (i.e., the port analyzing circuit 101) of the port analyzing circuits 101-103, and the detection circuit 104 detects a first input signal S1 of the port analyzing circuit 101 to output a detection signal TS. In detail, the detecting circuit 104 is used for determining the port number of the first input signal S1 to generate a detecting result, and outputting the detecting signal TS according to the detecting result. In other words, in one embodiment, the detection signal TS may indicate what kind of signal (or how many port numbers are) the first input signal S1 belongs to, such as a four-port (4-port) signal or an eight-port (8-port) signal.

The processing circuit 105 is electrically connected to the output terminals ON 1-ON 3 of the port analyzing circuits 101-103 and the detecting circuit 104. The processing circuit 105 retrieves the port data of the first data outputted from at least a portion of the output terminals of the port analyzing circuits 101-103 according to the detecting signal TS as the first control signal CN 1. More specifically, the processing circuit 105 selects, as the first control signal CN1, port data for retrieving a part of the first data output by the port analyzing circuits or port data for retrieving all of the first data output by the port analyzing circuits according to the type (the number of ports) of the first input signal S1 indicated by the detection signal TS.

For example, if the detection signal TS indicates that the input signal S1 is an 8-port (8port) signal, which represents that the SATA interface is connected to the PCH, the processing circuit 105 retrieves the port data of the first data (e.g., the first data D1, D2) outputted by the outputs (e.g., the outputs ON1, ON2) of a part of the port resolution circuits (e.g., the port resolution circuits 101, 102) as the first control signal CN 1. If the detection signal TS indicates that the input signal S1 is a 4-port (4port) signal, which represents that the SATA interface is connected to the HBA, the processing circuit 105 retrieves port data of first data (e.g., the first data D1 through D3) outputted by all of the outputs (e.g., the outputs ON1 through ON3) of the port analyzing circuits (e.g., the port analyzing circuits 101 through 103) as the first control signal CN 1.

The integrated circuit bus parser 11 is used for parsing the data streams C1 and C2 to generate respective address information, control command and input data, and outputting a second control signal CN2 according to the respective address command, control command and input data associated with the address information. In practice, the ic bus parser circuit 11 is connected to one or more processors and receives data streams (e.g., data streams C1, C2) from the one or more processors. In the embodiment of fig. 1, the ic bus parser circuit 11 obtains the address information, the control command and the input data respectively by parsing the data streams C1 and C2, and outputs the second control signal CN2 according to the address command, the control command and the input data respectively related to the address information.

the first multiplexer 12 is used for selectively outputting the first control signal CN1 or the second control signal CN2 according to the detection signal DS. The detection signal DS may indicate whether SATA or NVME is supported by the current backplane, so as to determine whether to output the first control signal CN1 or the second control signal CN2, where the first control signal CN1 and the second control signal CN2 are respectively used for lighting the LEDs of SATA and NVME. For example, SATA corresponds to a signal level of 1 and NVME corresponds to a signal level of 0. When the detection signal DS indicates a signal level of 1, the first multiplexer 12 conducts the path from the serial general purpose input output analyzer circuit 10 to the output terminal of the first multiplexer 12 to output the first control signal CN 1. Conversely, when the detection signal DS indicates that the signal level is 0, the first multiplexer 12 turns on the path from the integrated circuit bus analyzer circuit 11 to the output terminal of the first multiplexer 12, so as to output the second control signal CN 2.

By executing the lighting of the hard disk LED through the structure of the complex programmable logic device 1 provided by the invention, the number of the independent analysis circuits under the traditional architecture can be greatly reduced, and the purpose of saving resources is achieved in a simplified circuit configuration mode.

Referring to fig. 2, fig. 2 is a detailed functional block diagram of the complex programmable logic device according to the embodiment of fig. 1. FIG. 1 and FIG. 2 have substantially the same architecture, except that the processing circuit 105 of FIG. 2 includes a first sub-circuit 1051, a second sub-circuit 1052 and a second multiplexer 1053, and the integrated circuit bus resolution circuit 11 includes multiple address response circuits 110, 111. The first sub-circuit 1051 has an input terminal P1 and an output terminal Q1, and the input terminal P1 of the first sub-circuit 1051 is electrically connected to the output terminals ON 1-ON 3. The first sub-circuit 1051 is used for retrieving port data of the first data outputted by a part of the port analyzing circuits 101-103.

the second sub-circuit 1052 has an input terminal P2 and an output terminal Q2, and the input terminal P2 of the second sub-circuit 1052 is electrically connected to the output terminals ON1 to ON 3. The second sub-circuit 1052 is used for retrieving the port data of the first data output by each port parsing circuit.

The second multiplexer 1053 is electrically connected to the output Q1 of the first sub-circuit 1501, the output Q2 of the second sub-circuit 1502, and the first multiplexer 12. The second multiplexer 1053 turns on the path from the output Q1 of the first sub-circuit 1051 or the output Q2 of the second sub-circuit 1052 to the first multiplexer 12 according to the detection signal TS.

In one embodiment, when the detection signal TS indicates that the input signal S1 is an 8-port (8-port) signal, the first sub-circuit 1051 extracts the port data of the first data D1 and D2 outputted by the port analyzing circuits 101-102 as the first control signal CN 1. In another situation, when the detection signal TS indicates that the input signal S1 is a 4-port (4-port) signal, the second sub-circuit 1052 extracts the port data of the first data D1-D3 outputted by the port analyzing circuits 101-103 as the first control signal CN 1.

on the other hand, the multi-address response circuits 110, 111 respectively analyze the data streams C1, C2 to respectively obtain the corresponding address information (address), input data (value) and control command (command). The multi-address response circuits 110 and 111 have a plurality of preset addresses respectively preset therein. The multi-address response circuits 110, 111 respectively determine which of the preset addresses the address information responds to (or corresponds to), record the corresponding preset address, and output the recorded preset address as an address command. The multiple address response circuits 110, 111 respectively output corresponding data by using address commands and control commands based on the input data, and the output data can be used as the second control signal CN 2. By the multi-address response characteristic, the use number of the integrated circuit bus slave modules (I2C slave) under the traditional architecture can be reduced, and the resource occupation of the complex programmable logic device is greatly reduced.

In one embodiment, the detection signal TS indicates that the first input signal S1 of the first port parsing circuit 101 is an eight-port signal, and the first sub-circuit 1051 retrieves all the port values in the port data of the first data D1 output by the first port parsing circuit 101 and retrieves some of the port values in the port data of the first data output by another port parsing circuit according to the detection signal TS. In detail, when the input signal of the first port analyzing circuit 101 is determined to be an eight-port signal, the first sub-circuit 1051 retrieves all port values, such as an eight-port value (8-port data), in the port data of the first data D1 output by the port analyzing circuit 101. On the other hand, the first sub-circuit 1051 also retrieves the port values of four of the eight ports in the port data of the first data D1 outputted by the port resolution circuit 102.

In this case, the second sub-circuit 1052 does not capture the port data of the first data outputted from any port analyzing circuit, the first sub-circuit 1051 outputs the captured port values, and the second multiplexer 1053 can pass the first sub-circuit 1051 to the output terminal of the second multiplexer 1053 according to the detecting signal TS to output the port values as the first control signal CN 1.

In another embodiment, the detection signal TS indicates that the first input signal S1 of the first port analysis circuit 101 is a four-port signal, and the second sub-circuit 1052 extracts partial port values in the port data of the first data outputted by all the port analysis circuits according to the detection signal TS. Specifically, when the input signal of the first port analyzing circuit 101 is determined to be a four-port signal, the first sub-circuit 1051 retrieves a portion of the port values in the port data of the first data D1-D3 outputted by all of the port analyzing circuits 101-103. For example, the port values of four ports of the eight ports in the port data of the first data D1-D3 of each of the port resolution circuits 101-103 are retrieved. That is, the port values of the four ports are respectively taken from the port data (eight-port signal) of the first data outputted from the port analyzing circuits.

In this case, the first sub-circuit 1051 does not extract any port data of the first data outputted from the port analyzing circuit, the second sub-circuit 1052 outputs the extracted port values, and the second multiplexer 1053 can output the port values as the first control signal CN1 by turning on the path from the first sub-circuit 1051 to the output terminal of the second multiplexer 1053 according to the detecting signal TS.

Referring to fig. 3, fig. 3 is a flowchart illustrating a method of operating a complex programmable logic device according to an embodiment of the present invention, which is suitable for the complex programmable logic device 1 of fig. 1 and 2. As shown in the drawing, in step S11, the plurality of port resolution circuits 101-103 respectively receive the first input signals S1-S3 and correspondingly output the first data D1-D3. In step S12, the detection circuit 104 detects a first input signal S1 of a first one 101 of the port analyzing circuits 101-103 to output a detection signal TS. In step S13, the processing circuit 105 retrieves the port data of the first data outputted by at least a part of the port analyzing circuits 101 to 103 according to the detecting signal TS as the first control signal CN 1. In step S14, the integrated circuit bus circuit 11 parses the data stream to generate address information, control commands and input data, and outputs a second control signal CN2 according to the address commands, control commands and input data associated with the address information. In step S15, the first multiplexer 12 selectively outputs the first control signal CN1 or the second control signal CN2 according to the detection signal DS.

In an embodiment, when the detection signal TS indicates that the input signal of the first port analyzing circuit 101 is an eight-port signal, the step of extracting, by the processing circuit 105, the port data of the first data output by at least one part of the port analyzing circuits according to the detection signal TS as the first control signal CN1 includes: the first sub-circuit 1051 in the processing circuit 105 extracts all the port values in the port data of the first data D1 outputted from the first port analyzing circuit 101 and extracts some port values in the port data of the first data (e.g. the first data D2) outputted from another port analyzing circuit (e.g. the port analyzing circuit 102) according to the detecting signal TS.

In an embodiment, when the detection signal TS indicates that the input signal S1 of the first port analyzing circuit 101 is a four-port signal, the step of the processing circuit 105 extracting the port data of the first data outputted by at least a part of the port analyzing circuits according to the detection signal TS as the first control signal CN1 includes: a second sub-circuit 1052 of the processing circuit 105 retrieves partial port values of the port data of the first data D1-D3 outputted from all of the port analyzing circuits 101-103 according to the detecting signal TS.

In summary, in the complex programmable logic device and the operating method thereof provided by the present invention, on one hand, the detection circuit in the serial general input/output analysis circuit is used to detect what the input signal of the first port analysis circuit is (for example, a four-port or eight-port signal), and the processing circuit selectively retrieves at least a portion of the port data output by the port analysis circuit according to the signal type of the input signal to output the first control signal. On the other hand, the characteristics of the multi-address response of the circuit are resolved through the integrated circuit bus to output a second control signal. By means of the two analysis functions of the SGPIO and the I2C, the complex programmable logic device can simultaneously realize all functions of different types of hard disk backplanes under simplified module configuration, so as to achieve function integration of the complex programmable logic device, thereby reducing resource consumption and reducing cost.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.