阅读说明：本技术 一种双口地址总线的软件寻址方法及装置 (Software addressing method and device for double-port address bus ) 是由 刘安宁 赵鹏 于 2019-08-13 设计创作，主要内容包括：本发明提供一种双口地址总线的软件寻址方法,应用于通过双口RAM的第一口与RAM通信的处理器,第一口为双口RAM地址总线取反一端,双口RAM的第二口为双口RAM地址总线未取反一端,其特征在于,包括：获取处理器输入的输入地址；获取处理器的输出地址总线的第一最低位和处理器输入地址总线的第二最低位；根据第一最低位和第二最低位,将输入地址转化为第一口访问双口的地址。本发明针对双口RAM的两套地址总线一端取反,一端未取反的硬件状态,利用软件方法找到相对应的储存器单元地址。(The invention provides a software addressing method of a double-port address bus, which is applied to a processor communicating with an RAM through a first port of the double-port RAM, wherein the first port is the inverted end of the double-port RAM address bus, and a second port of the double-port RAM is the non-inverted end of the double-port RAM address bus, and is characterized by comprising the following steps: acquiring an input address input by a processor; acquiring a first lowest bit of an output address bus of a processor and a second lowest bit of an input address bus of the processor; and converting the input address into an address of the first port access double port according to the first lowest bit and the second lowest bit. The invention uses software method to find out the corresponding memory unit address aiming at the hardware state that one end of two sets of address buses of the double-port RAM is negated and the other end is not negated.)

1. A software addressing method of a dual-port address bus is applied to a processor which communicates with an RAM through a first port of the dual-port RAM, the first port is an inverted end of the dual-port RAM address bus, a second port of the dual-port RAM is an un-inverted end of the dual-port RAM address bus, and the software addressing method is characterized by comprising the following steps:

Acquiring an input address input by a processor;

Acquiring a first lowest bit of an output address bus of a processor and a second lowest bit of an input address bus of the processor;

and converting the input address into an address of the first port access double port according to the first lowest bit and the second lowest bit.

2. the method of claim 1, wherein converting the input address to an address of the first port access dual port based on the first least significant bit and the second least significant bit comprises:

Determining a right shift number m according to the second lowest bit, wherein m is an integer;

Determining a left shift number n according to the first lowest bit, wherein n is an integer;

and (3) shifting the input address to the right by m bits according to a binary system, negating the address of the second port after the right shift, and shifting the negated address to the left by n bits to obtain the base address of the first port access double port.

3. the method of claim 2, further comprising:

the difference between the base address and the first least significant bit is calculated to obtain the offset address.

4. The method of claim 2, wherein m and n are determined by the formula:

m＝log(Y/8)；n＝log(X/8)；

Wherein Y is the second lowest bit; x is the first lowest bit.

5. A software addressing device of a dual-port address bus is applied to a processor which communicates with an RAM through a first port of the dual-port RAM, the first port is an inverted end of the dual-port RAM address bus, and a second port of the dual-port RAM is an un-inverted end of the dual-port RAM address bus, and is characterized by comprising:

The acquisition module is used for acquiring an input address input by the processor; acquiring a first lowest bit of an output address bus of a processor and a second lowest bit of an input address bus of the processor;

and the conversion module is used for converting the input address into an address of the first port access double port according to the first lowest bit and the second lowest bit.

6. the apparatus of claim 5, wherein the conversion module comprises:

a determining unit, configured to determine a right shift number m according to the second lowest bit, where m is an integer; the left shift number n is determined according to the first lowest bit, and n is an integer;

and the processing unit is used for right shifting the input address by m bits according to the binary system, negating the address of the second port after right shifting, and left shifting the negated address by n bits to obtain the base address of the first port access double port.

7. The apparatus of claim 6, further comprising:

And the calculating module is used for calculating the difference between the base address and the first lowest bit to obtain the offset address.

8. The apparatus of claim 6, wherein the formula for determining m and n is:

m＝log(Y/8)；n＝log(X/8)；

Wherein Y is the second lowest bit; x is the first lowest bit.

9. a computer-readable storage medium, in which a program capable of being run by a computer is stored, wherein the computer program is executed by a processor to implement the method according to any one of claims 1 to 4.

Technical Field

the invention belongs to the technical field of computer bus communication, and relates to a software addressing method and device for a double-port address bus.

background

The dual-port RAM is a memory with two read-write ports, and each port has a set of independent data, address and control buses, so that two processors are allowed to operate the memory to realize data sharing. The address space allocated by the two processor hardware needs to ensure that the same memory location is accessible to the respective software, otherwise sharing data will be in error. In the conventional design, the address codes sent by the two processors are consistent, so that the correct memory unit accessed by the software can be ensured. However, there may be a design in which the address is inverted by hardware (a line driver or FPGA logic) at the sending end or the receiving end of the dual port, and the other end is not inverted, and there is a difference in the software addressing methods of the two ports.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the hardware state that one end of two sets of address buses of the double-port RAM is inverted and the other end is not inverted, the corresponding memory unit address is found by using a software method.

the technical scheme of the invention is as follows:

the invention provides a software addressing method of a double-port address bus, which is applied to a processor communicating with an RAM through a first port of the double-port RAM, wherein the first port is the inverted end of the double-port RAM address bus, and a second port of the double-port RAM is the non-inverted end of the double-port RAM address bus, and comprises the following steps:

Acquiring an input address input by a processor;

acquiring a first lowest bit of an output address bus of a processor and a second lowest bit of an input address bus of the processor;

And converting the input address into an address of the first port access double port according to the first lowest bit and the second lowest bit.

Further, converting the input address into an address of the first port access dual port according to the first least significant bit and the second least significant bit includes:

determining a right shift number m according to the second lowest bit, wherein m is an integer;

Determining a left shift number n according to the first lowest bit, wherein n is an integer;

and (3) shifting the input address to the right by m bits according to a binary system, negating the address of the second port after the right shift, and shifting the negated address to the left by n bits to obtain the base address of the first port access double port.

Further, the method further comprises:

the difference between the base address and the first least significant bit is calculated to obtain the offset address.

further, the formula for determining m and n is:

m＝log(Y/8)；n＝log(X/8)；

wherein Y is the second lowest bit; x is the first lowest bit.

The invention provides a software addressing device of a double-port address bus, which is applied to a processor communicating with an RAM through a first port of the double-port RAM, wherein the first port is the inverted end of the double-port RAM address bus, and a second port of the double-port RAM is the non-inverted end of the double-port RAM address bus, and the software addressing device comprises:

the acquisition module is used for acquiring an input address input by the processor; acquiring a first lowest bit of an output address bus of a processor and a second lowest bit of an input address bus of the processor;

and the conversion module is used for converting the input address into an address of the first port access double port according to the first lowest bit and the second lowest bit.

Further, the conversion module comprises:

A determining unit, configured to determine a right shift number m according to the second lowest bit, where m is an integer; the left shift number n is determined according to the first lowest bit, and n is an integer;

And the processing unit is used for right shifting the input address by m bits according to the binary system, negating the address of the second port after right shifting, and left shifting the negated address by n bits to obtain the base address of the first port access double port.

Further, the apparatus further comprises:

and the calculating module is used for calculating the difference between the base address and the first lowest bit to obtain the offset address.

further, the formula for determining m and n is:

m＝log(Y/8)；n＝log(X/8)；

Wherein Y is the second lowest bit; x is the first lowest bit.

The present invention provides a computer-readable storage medium storing a computer-executable program, which is executed by a processor to implement the method of any one of the present invention.

the invention has the beneficial effects that:

1. the dual-port with the address line inversion design is operated by a software method under the condition that hardware is not changed.

2. The method has wide applicability to address units with different bit widths.

Drawings

fig. 1 is a hardware interface schematic diagram of a software addressing method of a dual-port address bus according to the present invention.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

As shown in FIG. 1, it is assumed that the non-inverted side of the address bus of the dual port RAM is the A port (the second port) and the inverted side of the address bus is the B port (the first port). Firstly, determining the memory address allocated by the port A, and then determining the data bit width X represented by the lowest bit of the processor output address bus of the port B and the data bit width Y represented by the lowest bit of the input double-port RAM address bus of the port B.

and obtaining the base address and the offset address of the B port access double port according to the following operations:

the port A address is right shifted by log2(Y/8) bit, then inverted according to bit, and then left shifted by log2(X/8) bit, thus obtaining the access base address of port B, and other addresses of the memory space are obtained according to the base address-X/8.