阅读说明：本技术 一种cmos电平转换器、运行方法、装置、设备 (CMOS level converter, operation method, device and equipment ) 是由 苏杰 汤剑桥 徐祎喆 朱勇 于 2019-10-08 设计创作，主要内容包括：本发明公开了一种CMOS电平转换器、运行方法、设备,属于电子与通信技术领域。该CMOS电平转换器由两个低压到高压转换器、四个非门、一个与非门和一个或非门构成。本发明应用于芯片系统设计及含有该芯片的设备时,在实现对电源管理单元(PMU)提供高电平信号的前提下,极大地减小了芯片面积,降低了漏电,进一步降低了电路的功耗。(The invention discloses a CMOS level converter, an operation method and equipment, and belongs to the technical field of electronics and communication. The CMOS level shifter is composed of two low-voltage to high-voltage shifters, four NOT gates, one NAND gate and one NOR gate. When the invention is applied to chip system design and equipment containing the chip, on the premise of providing a high-level signal for a Power Management Unit (PMU), the chip area is greatly reduced, the electric leakage is reduced, and the power consumption of a circuit is further reduced.)

1. A CMOS level shifter comprising a first not gate, a second not gate, a third not gate, a fourth not gate, a nand gate, and a nor gate, further comprising:

A first low-voltage to high-voltage converter which converts a low-level signal into a high-level signal without a low-voltage power supply;

a second low-voltage to high-voltage converter which converts a low-level signal into a high-level signal when a low-voltage power supply is available;

a first enable signal is input into a first not gate, the first low-voltage to high-voltage converter with two signal input ends is input through the output end of the first not gate, the other signal input end of the first low-voltage to high-voltage converter receives a second enable signal, the signal output by the first low-voltage to high-voltage converter is input into one signal input end of the nor gate,

The first enable signal is input into the second low-voltage to high-voltage converter with two signal input terminals, the other signal input terminal of the second low-voltage to high-voltage converter receives the second enable signal, the signal output by the second low-voltage to high-voltage converter is input into the second not gate, and the other signal input terminal of the nor gate is input through the output terminal of the second not gate,

the signal output by the nor gate is input into the third not gate, and is input into one signal input end of the nand gate through the output end of the third not gate, the other signal input end of the nand gate receives the first enable signal, the signal output by the nand gate is input into the fourth not gate, and the level converter is output through the fourth not gate.

2. The CMOS level shifter as claimed in claim 1, wherein said first low voltage to high voltage converter comprises a fifth NOT gate, a sixth NOT gate, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor, wherein said first NOT gate signal output terminal is connected to a signal input terminal of said fifth NOT gate, and to a gate of said fifth PMOS transistor via an output terminal of said fifth NOT gate, a source of said fifth PMOS transistor is connected to a first operating power supply, a drain of said fifth PMOS transistor is connected to an operating voltage positive terminal of said sixth NOT gate, a operating voltage negative terminal of said sixth NOT gate is connected to a ground line, and a source of said fourth PMOS transistor, a substrate of said fourth PMOS transistor, and a substrate of said fourth PMOS transistor are sequentially connected between a drain of said fifth PMOS transistor and said operating voltage positive terminal of said sixth NOT gate from a drain of said fifth NOT gate, The substrate of the second PMOS tube, the source electrode of the second PMOS tube, the substrate of the first PMOS tube, the source electrode of the third PMOS tube and the substrate of the third PMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected with the ground wire, the drain electrode of the fourth PMOS tube is communicated with the drain electrode of the first PMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are communicated and connected with the second enabling signal receiving end, the grid electrode of the second PMOS tube, the drain electrode of the third PMOS tube and the signal input end of the sixth NOT gate are communicated and connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with the ground wire, the grid electrode of the third PMOS tube is connected with the grid electrode of the second NMOS tube and connected with the drain electrode of the first NMOS tube, the signal output end of the sixth NOT gate is connected with the signal output end of the first low-voltage to high-voltage converter, the signal output end of the sixth NOT gate is further connected with the drain electrode of the third NMOS tube, the source electrode of the third NMOS tube is connected with a ground wire, the grid electrode of the third NMOS tube is connected with an enabling end, the substrate of the third NMOS tube is communicated with the ground wire connecting end of the first low-voltage to high-voltage converter, and from the substrate of the third NMOS tube, the negative electrode of the sixth NOT gate, the substrate of the second NMOS tube, the source electrode of the second NMOS tube, the substrate of the first NMOS tube and the source electrode of the first NMOS tube are sequentially connected between the substrate of the third NMOS tube and the ground wire connecting end of the first low-voltage to high-voltage converter.

3. The CMOS level shifter of claim 2, wherein the first operating supply voltage is 3.3V, and wherein an enable signal of the gate connection of the third NMOS transistor is the same as the fifth not gate output signal.

4. the CMOS level shifter of claim 1, wherein the second low voltage to high voltage converter comprises a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, and a ninth PMOS transistor, the first enable signal input terminal is connected to the signal input terminal of the seventh NOT gate, the seventh NOT gate signal output terminal is connected to the gate of the ninth PMOS transistor, the source of the ninth PMOS transistor is connected to the positive working voltage terminal of the seventh NOT gate and to the first working power supply, the drain of the ninth PMOS is connected to the source of the eighth PMOS, the drain of the eighth PMOS is connected to the signal output terminal of the second low voltage to high voltage converter, and the source of the sixth PMOS and the source of the seventh PMOS are sequentially connected between the drain of the ninth PMOS and the source of the eighth PMOS, a grid electrode of the sixth PMOS tube is connected with a drain electrode of the seventh PMOS tube, a drain electrode of the sixth PMOS tube is connected with a grid electrode of the seventh PMOS tube, a drain electrode of the sixth PMOS tube is also connected with a drain electrode of the fourth NMOS tube, a source electrode of the fourth NMOS tube is connected with a ground wire, a drain electrode of the seventh PMOS tube is also connected with a drain electrode of the fifth NMOS tube, a source electrode of the fifth NMOS tube is connected with a ground wire, the drain electrode of the sixth NMOS tube and the drain electrode of the seventh NMOS tube are sequentially connected between the drain electrode of the eighth PMOS tube and a signal output end of the second low-voltage to high-voltage converter from the drain electrode of the eighth PMOS tube, the grid electrode of the sixth NMOS tube is communicated with the grid electrode of the eighth PMOS tube and is connected with the drain electrode of the fourth NMOS tube, the source electrode of the sixth NMOS tube is connected with the ground wire, the drain electrode of the seventh NMOS tube is connected with the ground wire, the grid electrode of the seventh NMOS tube is connected with an enable end, and the second enable signal is input into a signal input end of the eighth, and the signal output end of the eighth not gate is connected with the grid electrode of the fifth NMOS tube and the signal input end of the ninth not gate, and the signal output end of the ninth not gate is connected with the grid electrode of the fourth NMOS tube.

5. the CMOS level shifter of claim 4, wherein said eighth NOT gate and said ninth NOT gate are connected to a second operating supply voltage, said second operating supply voltage being lower than said first operating supply voltage.

6. The CMOS level shifter of claim 4, wherein an enable signal of a gate connection of said seventh NMOS transistor is the same as said seventh NOT gate output signal.

7. The CMOS level shifter of any one of claims 1 to 6, wherein said first NOT gate, said second NOT gate, said third NOT gate, said fourth NOT gate, said fifth NOT gate, said sixth NOT gate, said seventh NOT gate, said NAND gate, and said NOR gate have an operating voltage of 3.3V.

8. A method of operating a CMOS level shifter according to any of claims 1 to 6, comprising the steps of:

Turning on a power supply, and powering on the CMOS level converter;

the voltage of the second enabling signal is gradually increased from zero, the first voltage-to-high voltage converter is in a working state and outputs a 3.3V signal, and the signal output by the first voltage-to-high voltage converter sequentially passes through the NOR gate, the third NOT gate, the NAND gate and the fourth NOT gate to output the level converter;

when the voltage of the second enable signal is 1.2V, the second voltage-to-high voltage converter starts to be in a working state and outputs a 3.3V signal, the signal output by the second voltage-to-high voltage converter sequentially passes through the nor gate, the third not gate, the nand gate and the fourth not gate to output the level shifter, the first not gate receives a delay signal, and the first voltage-to-high voltage converter keeps in the working state;

After the second voltage-to-high voltage converter works stably, the first NOT gate receives a disconnection signal, and the first voltage-to-high voltage converter stops working.

9. A chip comprising a CMOS level shifter according to any one of claims 1 to 6.

10. A wireless communication device comprising the chip of claim 8.

Technical Field

the invention relates to the technical field of electronics and communication, in particular to a CMOS level converter, an operation method, a device and equipment.

Background

in a bluetooth low energy chip system (BLE SOC), a Power Management Unit (PMU) receives a control signal of 3.3V, but a register of a digital chip System (SOC) that controls the PMU is a 1.2V signal. When the PMU is just powered up, the 1.2V power supply for supplying power to the digital circuit is not yet established, and therefore a level shifter without 1.2V is required to convert the 1.2V control signal into a 3.3V control signal.

Fig. one shows a conventional 1.2V to 3.3V level shifter without a 1.2V power supply, which is composed of an NMOS transistor (M1) and a load resistor R. The input 1.2V signal is input from the grid electrode and output from the drain electrode of the NMOS tube (M1). In order to keep the current as low as possible, the load resistance R is typically in the order of mega ohms, occupying a large area. Such level shifters generate leakage at high input levels, have inherent leakage current, and occupy a large chip area.

Fig. two shows a conventional 1.2V to 3.3V level shifter, which needs to supply 1.2V power and 3.3V power simultaneously when operating. The input 1.2V signal is connected to the grid of the 3.3V NMOS tube through the two-stage inverter. And then output through the drain electrode of the NMOS tube. The drain load of the 3.3V NMOS tube is a cross-coupled 3.3V PMOS tube. This 1.2V to 3.3V level transition does not work without a 1.2V supply voltage and therefore cannot be used at the EN signal port of the control PMU.

Disclosure of Invention

The invention mainly solves the technical problem of providing a CMOS level converter, an operation method, a device and equipment, which reduce the area of a chip and reduce leakage current on the premise of ensuring that a PMU continuously receives high-level signals.

2. In order to achieve the above purpose, the invention adopts a technical scheme that: provided is a CMOS level shifter, which comprises a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a NAND gate and a NOR gate, and is characterized by further comprising:

a first low-voltage to high-voltage converter which converts a low-level signal into a high-level signal without a low-voltage power supply;

a second low-voltage to high-voltage converter which converts a low-level signal into a high-level signal when a low-voltage power supply is available;

A first enable signal is input into a first not gate, the first low-voltage to high-voltage converter with two signal input ends is input through the output end of the first not gate, the other signal input end of the first low-voltage to high-voltage converter receives a second enable signal, the signal output by the first low-voltage to high-voltage converter is input into one signal input end of the nor gate,

the first enable signal is input into the second low-voltage to high-voltage converter with two signal input terminals, the other signal input terminal of the second low-voltage to high-voltage converter receives the second enable signal, the signal output by the second low-voltage to high-voltage converter is input into the second not gate, and the other signal input terminal of the nor gate is input through the output terminal of the second not gate,

The signal output by the nor gate is input into the third not gate, and is input into one signal input end of the nand gate through the output end of the third not gate, the other signal input end of the nand gate receives the first enable signal, the signal output by the nand gate is input into the fourth not gate, and the level converter is output through the fourth not gate.

preferably, the first low-voltage to high-voltage converter comprises a fifth not gate, a sixth not gate, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor, wherein the first not gate signal output terminal is connected to the signal input terminal of the fifth not gate, the signal output terminal is connected to the gate of the fifth PMOS transistor through the output terminal of the fifth not gate, the source of the fifth PMOS transistor is connected to a first working power supply, the drain of the fifth PMOS transistor is connected to the positive working voltage of the sixth not gate, the negative working voltage of the sixth not gate is connected to a ground, and the source of the fourth PMOS transistor, the substrate of the second PMOS transistor, the source of the second PMOS transistor, the substrate of the third PMOS transistor, the drain of the fifth PMOS transistor, and the positive working voltage of the sixth not gate are sequentially connected between the drain of the fifth PMOS transistor and the positive working voltage of the fifth not gate, The substrate of the first PMOS tube, the source electrode of the third PMOS tube and the substrate of the third PMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected with the ground wire, the drain electrode of the fourth PMOS tube is communicated with the drain electrode of the first PMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are communicated and connected with the second enable signal receiving end, the grid electrode of the second PMOS tube, the drain electrode of the third PMOS tube and the signal input end of the sixth NOT gate are communicated and connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with the ground wire, the grid electrode of the third PMOS tube and the grid electrode of the second NMOS tube are connected with the drain electrode of the first NMOS tube and connected with the signal output end of the first low-to-high voltage converter, the signal output end of the sixth NOT gate is further connected with the drain electrode of a third NMOS tube, the source electrode of the third NMOS tube is connected with a ground wire, the grid electrode of the third NMOS tube is connected with an enabling end, the substrate of the third NMOS tube is communicated with the ground wire connecting end of the first low-voltage-to-high-voltage converter, and from the substrate of the third NMOS tube, the negative electrode of the sixth NOT gate, the substrate of the second NMOS tube, the source electrode of the second NMOS tube, the substrate of the first NMOS tube and the source electrode of the first NMOS tube are sequentially connected between the substrate of the third NMOS tube and the ground wire connecting end of the first low-voltage-to-high-voltage converter.

Preferably, the first operating power supply voltage is 3.3V, and an enable end signal connected to the gate of the third NMOS transistor is the same as the fifth not gate output signal.

Preferably, the second low-voltage to high-voltage converter includes a seventh not gate, an eighth not gate, a ninth not gate, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, and a ninth PMOS transistor, the first enable signal input terminal is connected to the signal input terminal of the seventh not gate, the seventh not gate signal output terminal is connected to the gate of the ninth PMOS transistor, the source of the ninth PMOS transistor is connected to the positive working voltage terminal of the seventh not gate and to the first working power supply, the drain of the ninth PMOS transistor is connected to the source of the eighth PMOS transistor, the drain of the eighth PMOS transistor is connected to the signal output terminal of the second low-voltage to high-voltage converter, and from the drain of the ninth PMOS transistor, the source of the sixth PMOS transistor and the source of the seventh PMOS transistor are sequentially connected between the drain of the ninth PMOS transistor and the source of the eighth PMOS transistor, a grid electrode of the sixth PMOS tube is connected with a drain electrode of the seventh PMOS tube, a drain electrode of the sixth PMOS tube is connected with a grid electrode of the seventh PMOS tube, a drain electrode of the sixth PMOS tube is also connected with a drain electrode of the fourth NMOS tube, a source electrode of the fourth NMOS tube is connected with a ground wire, a drain electrode of the seventh PMOS tube is also connected with a drain electrode of the fifth NMOS tube, a source electrode of the fifth NMOS tube is connected with a ground wire, the drain electrode of the sixth NMOS tube and the drain electrode of the seventh NMOS tube are sequentially connected between the drain electrode of the eighth PMOS tube and a signal output end of the second low-voltage to high-voltage converter from the drain electrode of the eighth PMOS tube, the grid electrode of the sixth NMOS tube is communicated with the grid electrode of the eighth PMOS tube and is connected with the drain electrode of the fourth NMOS tube, the source electrode of the sixth NMOS tube is connected with the ground wire, the drain electrode of the seventh NMOS tube is connected with the ground wire, the grid electrode of the seventh NMOS tube is connected with an enable end, and the second enable signal is input into a signal input end of the eighth, and the signal output end of the eighth not gate is connected with the grid electrode of the fifth NMOS tube and the signal input end of the ninth not gate, and the signal output end of the ninth not gate is connected with the grid electrode of the fourth NMOS tube.

Preferably, the eighth not gate and the ninth not gate are connected to a second operating power supply, and the second operating power supply voltage is lower than the first operating power supply voltage.

Preferably, the enable end signal connected to the gate of the seventh NMOS transistor is the same as the seventh not gate output signal.

Preferably, the operating voltage of the first not gate, the second not gate, the third not gate, the fourth not gate, the fifth not gate, the sixth not gate, the seventh not gate, the nand gate, and the nor gate is 3.3V.

In order to achieve the above object, the second technical solution adopted by the present invention is: there is provided a method of operating a CMOS level shifter, comprising the steps of:

Turning on a power supply, and powering on the CMOS level converter;

the voltage of the second enabling signal is gradually increased from zero, the first voltage-to-high voltage converter is in a working state and outputs a 3.3V signal, and the signal output by the first voltage-to-high voltage converter sequentially passes through the NOR gate, the third NOT gate, the NAND gate and the fourth NOT gate to output the level converter;

When the voltage of the second enable signal is 1.2V, the second voltage-to-high voltage converter starts to be in a working state and outputs a 3.3V signal, the signal output by the second voltage-to-high voltage converter sequentially passes through the nor gate, the third not gate, the nand gate and the fourth not gate to output the level shifter, the first not gate receives a delay signal, and the first voltage-to-high voltage converter keeps in the working state;

After the second voltage-to-high voltage converter works stably, the first NOT gate receives a disconnection signal, and the first voltage-to-high voltage converter stops working.

In order to achieve the above object, the third technical solution adopted by the present invention is: a chip is provided, which includes the CMOS level shifter according to the first embodiment.

In order to achieve the above object, a fourth technical solution adopted by the present invention is: a wireless communication device is provided, which comprises the chip in the third technical proposal.

the invention has the beneficial effects that: on the premise of providing a high-level signal for a Power Management Unit (PMU), the invention greatly reduces the chip area, reduces the electric leakage and further reduces the power consumption of the circuit.

drawings

FIG. 1 is a schematic diagram of a conventional 1.2V to 3.3.V level shifter without a 1.2V power supply;

FIG. 2 is a schematic diagram of a conventional 1.2V to 3.3V level shifter requiring a 1.2V power supply;

FIG. 3 is a schematic diagram of a CMOS level shifter of the present invention;

the parts in the drawings are numbered as follows: 101-a first not gate, 102-a first low-to-high voltage converter, 103-a second low-to-high voltage converter, 104-a second not gate, 105-a nor gate, 106-a third not gate, 107-a nand gate, 108-a fourth not gate

FIG. 4 is a schematic diagram of a first low-to-high voltage converter of the present invention;

the parts in the drawings are numbered as follows: 201-fifth NOT gate, 202-fifth PMOS tube, 203-fourth PMOS tube, 204-second PMOS tube, 205-third PMOS tube, 206-first PMOS tube, 207-first NMOS tube, 208-second NMOS tube, 209-sixth NOT gate, 210-third NMOS tube

FIG. 5 is a schematic diagram of a second low-to-high voltage converter of the present invention;

The parts in the drawings are numbered as follows: 301-seventh not gate, 302-ninth PMOS tube, 303-sixth PMOS tube, 304-seventh PMOS tube, 305-eighth PMOS tube, 306-eighth not gate, 307-ninth not gate, 308-fourth NMOS tube, 309-fifth NMOS tube, 310-sixth NMOS tube, and 311-seventh NMOS tube.

Detailed Description

The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.

Fig. 3 shows a CMOS level shifter. The CMOS level shifter includes a first not gate 101, a first low voltage to high voltage converter 102, a second low voltage to high voltage converter 103, a second not gate 104, a nor gate 105, a third not gate 106, a nand gate 107, and a fourth not gate 108.

A first enable signal is input to the first not gate 101, a first low voltage to high voltage converter 102 having two signal inputs is input through an output terminal of the first not gate 101, the other signal input terminal of the first low voltage to high voltage converter 102 receives a second enable signal, a signal output from the first low voltage to high voltage converter 102 is input to one signal input terminal of the nor gate 105,

the first enable signal is inputted to the second low-voltage to high-voltage converter 103 having two signal input terminals, the other signal input terminal of the second low-voltage to high-voltage converter 103 receives the second enable signal, the signal outputted from the second low-voltage to high-voltage converter 103 is inputted to the second not gate 104, the other signal input terminal of the nor gate 105 is inputted via the output terminal of the second not gate 104,

The output signal of the nor gate 105 is input to the third not gate 106, and is input to one signal input terminal of the nand gate 107 through the output terminal of the third not gate 106, another signal input terminal of the nand gate 107 receives the first enable signal, the output signal of the nand gate 107 is input to the fourth not gate 108, and the CMOS level converter is output through the fourth not gate 108.

The first low-to-high voltage converter converts a low level signal to a high level signal in the absence of a low voltage power supply (1.2V). The PMOS transistor comprises a fifth NOT gate 201, a fifth PMOS transistor 202, a fourth PMOS transistor 203, a second PMOS transistor 204, a third PMOS transistor 205, a first PMOS transistor 206, a first NMOS transistor 207, a second NMOS transistor 208, a sixth NOT gate 209 and a third NMOS transistor 210. The signal output end of the first not gate 101 is connected with the signal input end of a fifth not gate 201, the gate of a fifth PMOS transistor 202 is connected through the output end of the fifth not gate 201, the source of the fifth PMOS transistor 202 is connected with a first working power supply (3.3V), the drain of the fifth PMOS transistor 202 is connected with the working voltage anode of a sixth not gate 209, the working voltage cathode of the sixth not gate 209 is connected with the ground, starting from the drain of the fifth PMOS transistor 202, the source of the fourth PMOS transistor 203, the substrate of the second PMOS transistor 204, the source of the second PMOS transistor 204, the substrate of the first PMOS transistor 206, the source of the third PMOS transistor 205 and the substrate of the third PMOS transistor 205 are sequentially connected between the drain of the fifth PMOS transistor 202 and the working voltage anode of the sixth not gate 209, the drain of the second PMOS transistor 204 is connected with the source of the first PMOS transistor 206, the drain of the first PMOS transistor 206 is connected with the drain of the first NMOS transistor 207, the source of the first NMOS transistor 207 is connected with the ground, the drain of the fourth PMOS transistor 203 is connected to the drain of the first PMOS transistor 206, the gate of the fourth PMOS transistor 203, the gate of the first PMOS transistor 206 and the gate of the first NMOS transistor 207 are connected to a second enable signal receiving terminal, the gate of the second PMOS transistor 204, the drain of the third PMOS transistor 205 and the signal input terminal of the sixth not gate 209 are connected to the drain of the second NMOS transistor 208, the source of the second NMOS transistor 208 is connected to the ground, the gate of the third PMOS transistor 205 and the gate of the second NMOS transistor 208 are connected to the drain of the first NMOS transistor 207, the signal output terminal of the sixth not gate 209 is connected to the signal output terminal of the first low-voltage-to-high-voltage converter 102, the signal output terminal of the sixth not gate 209 is further connected to the drain of the third NMOS transistor 210, the source of the third NMOS transistor 210 is connected to the ground, the gate of the third NMOS transistor 210 is connected to an enable terminal, and the signal of the enable terminal is the same as the output signal of the fifth not gate 201. The substrate of the third NMOS transistor 210 is communicated with the ground connection end of the first low-voltage to high-voltage converter 102, and from the substrate of the third NMOS transistor 210, the negative electrode of the sixth not gate 209, the substrate of the second NMOS transistor 208, the source electrode of the second NMOS transistor 208, the substrate of the first NMOS transistor 207, and the source electrode of the first NMOS transistor 207 are sequentially connected between the substrate of the third NMOS transistor 210 and the ground connection end of the first low-voltage to high-voltage converter 102.

in the working state of the first low-voltage to high-voltage converter, a 3.3V first enable signal is input to the input end of the fifth not gate 201, a 0V signal is output after conversion and is transmitted to the gate of the fifth PMOS transistor 202, the fifth PMOS transistor 202 is turned on, an external 3.3V voltage signal is transmitted to the first low-voltage to high-voltage converter 102, and working voltages are sequentially provided for the source electrode of the fourth PMOS transistor 203, the source electrode of the second PMOS transistor 204, the source electrode of the third PMOS transistor 205 and the sixth not gate 209.

When the voltage of the second enable signal is lower than 1.2V, the signal is transmitted to the gate of the fourth PMOS transistor 203, the gate of the first PMOS transistor 206, and the gate of the first NMOS transistor 207, the fourth PMOS transistor 203 is connected to the first PMOS transistor 206, the first NMOS transistor 207 is disconnected, and the fourth PMOS transistor 203 is connected to the first PMOS transistor 206, which further causes the second NMOS transistor 208 to be connected, the third PMOS transistor 205 is disconnected, the input signal of the sixth not gate 209 is 0V, and the output signal thereof is 3.3V.

The second low-to-high voltage converter converts the low level signal to a high level signal when there is a low voltage power supply (1.2V). The PMOS transistor comprises a seventh NOT gate 301, a ninth PMOS transistor 302, a sixth PMOS transistor 303, a seventh PMOS transistor 304, an eighth PMOS transistor 305, an eighth NOT gate 306, a ninth NOT gate 307, a fourth NMOS transistor 308, a fifth NMOS transistor 309, a sixth NMOS transistor 310 and a seventh NMOS transistor 311. A first enable signal input end is connected with a signal input end of the seventh not gate 301, a signal output end of the seventh not gate 301 is connected with a grid electrode of the ninth PMOS tube 302, a source electrode of the ninth PMOS tube 302 is communicated with a working voltage anode of the seventh not gate 301 and is connected with a first working power supply (3.3V), a drain electrode of the ninth PMOS tube 302 is connected with a source electrode of the eighth PMOS tube 305, a drain electrode of the eighth PMOS tube 305 is connected with a signal output end of the second low-voltage to high-voltage converter 103, starting from a drain electrode of the ninth PMOS tube 302, a source electrode of the sixth PMOS tube 303 and a source electrode of the seventh PMOS tube 304 are sequentially connected between the drain electrode of the ninth PMOS tube 302 and the source electrode of the eighth PMOS tube 305, a grid electrode of the sixth PMOS tube 303 is connected with a drain electrode of the seventh PMOS tube 304, a drain electrode of the sixth PMOS tube 303 is also connected with a grid electrode of the seventh PMOS tube 304, a drain electrode of the sixth PMOS tube 303 is also connected with a drain electrode of the fourth NMOS tube 308, a source electrode of the fourth NMOS tube 308 is connected with a, the source of the fifth NMOS 309 is connected to the ground, the drain of the sixth NMOS 310 and the drain of the seventh NMOS 311 are sequentially connected between the drain of the eighth PMOS 305 and the signal output terminal of the second low-voltage to high-voltage converter 103 from the drain of the eighth PMOS 305, the gate of the sixth NMOS 310 is connected to the gate of the eighth PMOS 305 and to the drain of the fourth NMOS 308, the source of the sixth NMOS 310 is connected to the ground, the drain of the seventh NMOS 311 is connected to the ground, the gate of the seventh NMOS 311 is connected to an enable terminal, and the signal of the enable terminal is the same as the signal output by the seventh not gate 301. The second enable signal is input to the signal input terminal of the eighth not gate 306, the signal output terminal of the eighth not gate 306 is connected to the gate of the fifth NMOS transistor 309 and the signal input terminal of the ninth not gate 307, and the signal output terminal of the ninth not gate 307 is connected to the gate of the fourth NMOS transistor 308.

In the working state of the second low-voltage to high-voltage converter, a 3.3V first enable signal is input to the input terminal of the seventh not gate 301, and after conversion, a 0V signal is output and transmitted to the gate of the ninth PMOS transistor 302, the ninth PMOS transistor 302 is turned on, a 3.3V voltage signal is transmitted to the source of the eighth PMOS transistor 305, and the gate of the seventh NMOS transistor 311 receives a voltage signal which is the same as the output signal of the seventh not gate 301 and is also 0V, so that the seventh NMOS transistor 311 is turned off.

when the 1.2V second enable signal (i.e., IN-LV) is inputted to the eighth not gate 306, and is converted to output a 0V signal to the signal input terminal of the ninth not gate 307 and the gate of the fifth NMOS transistor 309, which results IN the fifth NMOS transistor 309 being turned off, the ninth not gate 307 outputs a high voltage signal to the gate of the fourth NMOS transistor 308, which results IN the fourth NMOS transistor 308 being turned on, which further results IN the eighth PMOS transistor 305 being turned on, and the sixth NMOS transistor 310 being turned off, and the 3.3V voltage signal is outputted to the second low-voltage to high-voltage converter 103 through the eighth PMOS transistor 305.

in the CMOS level shifter operating state, the operating voltages of the first not gate 101, the first low-voltage to high-voltage converter 102, the first operating voltage of the second low-voltage to high-voltage converter 103, the second not gate 104, the third not gate 106, the fourth not gate 108, the fifth not gate 201, the sixth not gate 209, the seventh not gate 301, the nand gate 107, and the nor gate 105 are 3.3V, and the second operating voltage of the second low-voltage to high-voltage converter 103 is lower than 3.3V.

The CMOS level converter can be applied to a low-power-consumption Bluetooth chip-level system (BLE SOC), can also be applied to other chips which need low level conversion to high level, is further applied to wireless communication equipment such as Bluetooth products and wireless routers, and can reduce the size of the chips and the related wireless communication equipment, reduce electric leakage and reduce power consumption.

The operating principle of the CMOS level shifter will be described in detail below by taking the signal conduction in the operating state of the CMOS level shifter as an example.

the power supply is turned on, the CMOS level converter is powered on, the first low-voltage to high-voltage converter starts to work, a low-level enabling signal is converted from the input end of the first NOT gate 101 and then outputs a 3.3V signal, the input end of a fifth NOT gate 201 in the first low-voltage to high-voltage converter 102 is input, the fifth NOT gate 201 is converted and then outputs a 0V signal to the grid electrode of a fifth PMOS (P-channel metal oxide semiconductor) tube 202, at the moment, the fifth PMOS tube 202 is conducted, meanwhile, a second enabling signal lower than 1.2V is input into the first low-voltage to high-voltage converter 102, the 3.3V signal is output after the internal signal processing of the first low-voltage to high-voltage converter 102, the signal input end of the NOR gate 105 is further input, and the CMOS level converter is output after the processing of the third NOT gate 106, the NAND gate;

With the voltage of the second enable signal rising to 1.2V, the second low-voltage to high-voltage converter 103 starts to work, the enable signal of 3.3 is processed by the second low-voltage to high-voltage converter 103 to output a 3.3V signal, and is further input to the second not gate 104, converted into a 0V signal, input to one signal input end of the nor gate 105, and sequentially processed by the third not gate 106, the nand gate 107 and the fourth not gate 108 to output a CMOS level converter;

When the voltage of the second enable signal is stabilized to 1.2V, the second low-voltage to high-voltage converter 103 is under stability, and provides a 3.3V enable signal to be input to the first not gate 101, and after conversion, a 0V signal is output, so that the first low-voltage to high-voltage converter stops working.

The design mode of switching the first low-voltage to high-voltage converter and the second low-voltage to high-voltage converter is used, so that the occupied area of a chip is reduced on the premise of providing a 3.3V voltage signal for the PMU, and the area of a current-carrying chip in the SMIC55nm process is one third of the original area; the leakage current is reduced, and the power consumption of the analog circuit part is reduced to 200 nanoamperes from 400 nanoamperes, and is reduced by 50%. .

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structural changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.