阅读说明：本技术 具有集成存储器一致性互连的存储器和存储控制器 (Memory and memory controller with integrated memory coherency interconnect ) 是由 纳尔辛·克里希纳·维贾伊拉奥 克里斯蒂安·马库斯·彼得森 于 2021-04-30 设计创作，主要内容包括：本申请涉及具有集成存储器一致性互连的存储器和存储控制器。公开了一种控制器设备。该控制器设备包括通信接口,该通信接口被配置成经由互连总线接收数据操作请求。该控制器设备包括集成互连协议组件,该集成互连协议组件被配置为处理经由互连总线的通信,该集成互连协议组件支持控制器设备外部的多个不同处理设备之间的一致性。同一控制器设备上的集成存储器或存储控制器组件被配置成处理数据操作请求,包括被配置成管理与控制器设备外部的存储器或数据存储设备的通信。(The application relates to a memory and a memory controller with an integrated memory coherence interconnect. A controller device is disclosed. The controller device includes a communication interface configured to receive a data operation request via an interconnection bus. The controller device includes an integrated interconnect protocol component configured to handle communications via an interconnect bus, the integrated interconnect protocol component supporting coherency between a plurality of different processing devices external to the controller device. An integrated memory or memory controller component on the same controller device is configured to process data operation requests, including being configured to manage communications with a memory or data storage device external to the controller device.)