阅读说明：本技术 一种扫描测试交换网络和扫描测试方法 (Scanning test switching network and scanning test method ) 是由 张心标 曾辉 于 2021-09-13 设计创作，主要内容包括：本发明公开了一种扫描测试交换网络和扫描测试方法,该扫描测试交换网络包括：I/O输入单元,用于提供对待测试模块的扫描测试通道进行测试的输入数据；配置单元,用于控制I/O输入单元的端口输入/输出状态,并生成配置信号；扫描交换网络,由多个交换单元组成,用于根据配置信号确定输入数据在交换单元之间的映射交换路径,以将I/O输入单元与扫描测试通道进行选通；I/O输出单元,用于接收所述扫描测试通道的测试结果数据。本发明的技术方案能够在测试后期根据实际需求进行模式划分,方便灵活地配置实现路由选通,提高了扫描测试效率,降低设计成本。(The invention discloses a scanning test switching network and a scanning test method, wherein the scanning test switching network comprises: the I/O input unit is used for providing input data for testing a scanning test channel of the module to be tested; the configuration unit is used for controlling the port input/output state of the I/O input unit and generating a configuration signal; the scanning switching network consists of a plurality of switching units and is used for determining a mapping switching path of input data among the switching units according to the configuration signal so as to gate the I/O input unit and the scanning test channel; and the I/O output unit is used for receiving the test result data of the scanning test channel. The technical scheme of the invention can divide the modes according to the actual requirements at the later stage of the test, conveniently and flexibly configure and realize the routing gating, improve the scanning test efficiency and reduce the design cost.)

1. A scan test switching network, comprising:

the I/O input unit is used for providing input data, and the input data is used for testing a scanning test channel of a module to be tested;

the configuration unit is used for controlling the port input/output state of the I/O input unit and generating a configuration signal for the scanning switching network; and

the scanning switching network consists of a plurality of switching units and is used for determining mapping switching paths of the input data among the switching units according to the configuration signals so as to gate the I/O input unit and a scanning test channel of a module to be tested;

and the I/O output unit is used for receiving the test result data of the scanning test channel.

2. The scan test switching network of claim 1, wherein the plurality of switching elements form a multi-level interconnect network according to a predefined topological relationship.

3. The scan test switching network of claim 1, wherein the configuration unit is coupled to a plurality of switching units in the scan switching network, the plurality of switching units receiving the configuration signal to determine a mapped switching path of the input data between the plurality of switching units.

4. The scan test switching network of claim 2, wherein the multi-stage interconnect network is a non-blocking switching network.

5. The scan test switching network of claim 1, wherein the scan switching network is disposed between the I/O output unit and a scan output channel of the module under test.

6. The scan test switching network of claim 1, wherein the scan switching network comprises a first scan switching network and a second scan switching network;

the first scanning exchange network is used for gating the I/O input unit and a scanning input channel of the module to be tested;

and the second scanning exchange network is used for gating the scanning output channel of the module to be tested and the I/O output unit.

7. A scan test method based on the scan test switching network of any one of claims 1 to 6, comprising:

determining a configuration signal of the scanning switching network according to a module to be tested;

inputting the determined configuration signal into a scanning switching network to generate a selection path of a scanning test channel, wherein the selection path is formed by combining mapping switching paths;

and scanning and testing the module to be tested through the I/O input unit according to the generated gating path.

8. The scan test method of claim 7, wherein an input/output state control signal is provided to the I/O input unit by the configuration unit after the generation of the selection path of the scan test channel.

9. The scan test method of claim 7, wherein prior to determining the configuration signal for the scan switch network, the method further comprises: and designating an I/O input port of the I/O input unit and a scan-in channel of the module to be tested.

10. The scan test method of claim 7, wherein the scanning and testing the module under test through the I/O input unit further comprises: and sending the input data to the scanning test channel to be tested from the external I/O port of the I/O input unit through the corresponding mapping switching paths of the plurality of switching units.

Technical Field

The invention relates to the field of design and test of semiconductor digital integrated circuits, in particular to a scan test switching network and a scan test method.

Background

With the rapid development of large-scale digital chips, design for testability (DFT) is becoming more and more important in large-scale digital chip design and testing. With the increasing chip scale, in SCAN test (SCAN), the number of SCAN test channels is increasing, and the number of external ports required is also increasing. Since the number of external ports is limited, the number of ports required per test module cannot exceed the number of available external ports. Thus requiring a division into multiple tests, each testing a different module. In order to solve the problem of limited number of external ports, a common method at present is to use a Multiplexer (MUX) to perform port multiplexing, and in each test mode, a fixed corresponding relationship is established between the mapping of a module scan test channel and the external port. The MUX multiplexing approach described above, however, lacks flexibility. If the design at the early stage is unreasonable and the corresponding test mode is lacked, the test can not be carried out when some modules need to be tested at the later stage. Or if the port division is not reasonable, the division needs to be carried out again, the design structure needs to be modified again, and the progress of the design test is seriously influenced.

Disclosure of Invention

In view of the above, the present invention provides a scan test switching network and a corresponding scan test method, which do not require pre-division in the early stage, and directly perform division in the later stage according to test requirements, and meanwhile, ensure free gating of an external port and a scan test channel.

The present invention provides in a first aspect a scan test switching network comprising:

the I/O input unit is used for providing input data, and the input data is used for testing a scanning test channel of a module to be tested;

the configuration unit is used for controlling the port input/output state of the I/O input unit and generating a configuration signal for the scanning switching network; and

the scanning switching network consists of a plurality of switching units and is used for determining mapping switching paths of the input data among the switching units according to the configuration signals so as to gate the I/O input unit and a scanning test channel of a module to be tested;

and the I/O output unit is used for receiving the test result data of the scanning test channel.

Preferably, the plurality of switching units form a multi-level interconnection network according to a predefined topological relation.

Preferably, the configuration unit is connected to a plurality of switching units in the scan switch network, and the plurality of switching units receive the configuration signal to determine a mapping switch path of the input data between the plurality of switching units.

Preferably, the multi-stage internetwork is a non-blocking switching network.

Preferably, the scan switching network is disposed between the I/O output unit and a scan output channel of the module under test.

Preferably, the scan switching network comprises a first scan switching network and a second scan switching network;

the first scanning exchange network is used for gating the I/O input unit and a scanning input channel of the module to be tested;

and the second scanning exchange network is used for gating the scanning output channel of the module to be tested and the I/O output unit.

Another aspect of the present invention provides a scan test method for a scan test switching network based on the foregoing aspect, including:

determining a configuration signal of the scanning switching network according to a module to be tested;

inputting the determined configuration signal into a scanning switching network to generate a selection path of a scanning test channel, wherein the selection path is formed by combining mapping switching paths;

and scanning and testing the module to be tested through the I/O input unit according to the generated gating path.

Preferably, after generating the selection path of the scan test channel, an input/output state control signal is provided to the I/O input unit through the configuration unit.

Preferably, before determining the configuration signal of the scanning switching network, the method further comprises: and designating an I/O input port of the I/O input unit and a scan-in channel of the module to be tested.

Preferably, the scanning and testing the module to be tested through the I/O input unit further includes: and sending the input data to the scanning test channel to be tested from the external I/O port of the I/O input unit through the corresponding mapping switching paths of the plurality of switching units.

It can be seen that the freely gated scan test switching network and scan test method of the present invention can arbitrarily assign the I/O port and scan test channel at the later stage, i.e. can implement route gating by configuration, which is convenient and flexible, and meets different test requirements, and meanwhile, the relation between the test mode and the pin allocation does not need to be determined at the initial stage of design, and the design cost is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of a switching network structure for scan test according to the present invention.

Fig. 2 is a schematic diagram of an internal structure of a scan exchange unit according to the present invention.

Fig. 3 is a schematic diagram of an extended scan test switching network structure according to the present invention.

Fig. 4 is a flowchart of a method for performing scan testing based on the scan test switching network structure of fig. 1 according to the present invention.

Fig. 5 is a flowchart of a method for performing scan testing based on the scan test switching network structure of fig. 3 according to the present invention.

Detailed Description

In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.

It should be understood that the described embodiments are merely exemplary of some, but not all embodiments of the invention, and that numerous specific details are set forth in order to provide a thorough understanding of the invention. In addition, some methods, means, components and applications thereof known to those skilled in the art are not described in detail in order to highlight the gist of the present invention, but the implementation of the present invention is not affected. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The inventor finds in long-term research that a scan test switching network can refer to a networking idea of a multi-stage interconnection network (MIN) in the communication field. The multi-stage interconnection network is formed by connecting a large number of basic switching units with each other according to a specific topological structure, and cell switching can be realized by establishing channels in a switching network. The multi-stage interconnection network can realize free gating from the input end to the output end, and can change the state of each stage of node switch in real time according to the requirement of full-channel sequencing through a specific routing algorithm. In view of this, the external I/O port and the scan _ channel to be tested are designated by freely gating the external port and the test channel, so that a corresponding mapping switching path can be obtained, and the requirement of the scan test switching network can be met without the need of the previous mode division. Based on the method, the invention provides a hardware-implementable scan test switching network based on a multi-level interconnection network structure.

The scanning test switching network provided by the invention builds a scanning switching unit, builds a scanning test switching network based on a multilevel interconnection network, and obtains configuration data of the scanning test switching network through a network routing algorithm according to the position of an external I/O port and a scanning channel to be tested in the scanning test switching network. When the scanning test is carried out, the free route gating of the test mode can be realized by carrying out corresponding configuration on the scanning test switching network.

Example one

Fig. 1 shows a scan test switching network structure for scan test input channel free gating, which includes an I/O unit, a configuration unit (CONFIG), and a scan switching network (MAPPING). The I/O unit further includes an I/O input unit and an I/O output unit. The output end of the I/O input unit is connected with the scanning switching network through a data bus, and the output end of the configuration unit is connected with the scanning switching network. The I/O output unit is used for receiving the test result data of the scanning test channel.

The output end of the scan switching network is connected with a plurality of scan input channel modules 1-1 _ n to be tested (herein referred to as modules to be tested). The scan input channel module to be tested may be a functional module of a chip.

The I/O input unit is used for providing input data (channel _ in [ n-1:0]) of a scan test channel, and the input data is used for testing the scan test channel in the scan input channel module to be tested. Specifically, the input data may be input from the outside by a user or an upper computer, and may be used to specify one or more modules _1 to module _ n that need to be tested. When a user needs to test module _ x, i.e. the xth channel _ x, the following commands can be used as input data:

CHANNELTEST x testdata。

testdata may be the actual test data used to scan the test channel. It will be understood by those skilled in the art that the above commands are for exemplary purposes only and are not intended to limit the command format of the present invention.

For the purpose of illustrating the principles of the present invention, each of the modules under test shown in fig. 1 corresponds to one scan test channel. It should be understood by those skilled in the art that each module under test may correspond to a plurality of scan test channels, respectively.

The configuration unit (CONFIG) is used for controlling the port input/output state of the I/O unit and generating configuration signals (swap [ m:0]) for the scanning switching network, wherein m is the number of the configuration signals. And the scanning switching network determines a mapping switching path of the input data among the plurality of switching units according to the configuration signal so as to gate the I/O input unit and a scanning test channel of the module to be tested. That is, the scanning of the switching network uses the configuration signals to determine how the data signals are mapped in the switching network in steps, i.e., to determine the final data path. Specifically, as shown in fig. 1, the configuration unit is connected with a plurality of switching units, so that each of the plurality of switching units can receive the configuration signal.

The scanning switching network (MAPPING) is a non-blocking and freely-gated multi-stage interconnection network MIN which is composed of a plurality of switching units according to a certain topological relation. The example of fig. 1 illustrates a multi-level internetwork that is a benes network.

The internal structure of each switching unit is shown in fig. 2. The configuration signal is swap, the input is i _0, i _1, and the output is o _0, o _ 1. The configuration signal may control whether the switching elements are connected in parallel or in cross-connection. The connection relationship of the different switching units is controlled by a connection function. The structural form, namely the topological relation, of the whole scanning switching network can be determined according to the connection function.

Referring to fig. 1 again, N/2 switching units are respectively disposed at two sides of the benes network, two benes sub-networks of N/2 × N/2 are disposed in the middle, and each switching unit is connected to each sub-network by a link; and then, the intermediate sub-networks are continuously decomposed according to the method until the intermediate sub-networks are decomposed into 2 x 2 switching units, wherein N is a parameter representing the scale of the benes network. 2n-1 different paths exist between any pair of input ends and output ends, so that the occurrence of blockage can be avoided.

Through the scan switching network, the I/O input unit may be connected to a scan test channel (channel _ mapping _ in) of a module to be tested, and the plurality of scan input channel modules module _1 to module _ n are connected through the channel _ mapping _ in, where n represents the total number of scan input channel modules to be tested. Since the scan switch network is a benes network, it can be gated freely. When any I/O port and scan-in channel are designated, there is at least one strobe path. Therefore, different modules to be tested can be subjected to combined test at will according to the requirements.

Example two

In an extended embodiment, the scan test channels of the module under test include a scan input channel (channel _ mapping _ in) and a scan output channel (channel _ mapping _ out). The scan test switching network is provided with a switching network between the I/O port and the scan input channel, and a switching network between the scan output channel and the I/O port. Also, the number of scanning switching networks may be one or more. When the number of scan channels is large and the number of I/O ports is insufficient, a plurality of scan switch networks may be provided. Fig. 3 shows a schematic diagram of the free and non-blocking multi-stage interconnection network where the scan input channel and the scan output channel correspond to the scan switching network MAPPING. On the basis of fig. 1, a switching network between scanout lanes and I/O ports is added. And thus the same components as in fig. 1 will not be described again.

Referring to fig. 3, the scan test switching network may include a plurality of scan switching networks MAPPING, and may be divided into a first scan switching network MAPPING _ IN and a second scan switching network MAPPING _ OUT according to their functions. The first scan switching network MAPPING _ IN connects the I/O input cells to the scan input channels, and the second scan switching network MAPPING _ OUT connects the scan output channels to the I/O output cells. The scan input channel modules of the modules _1 to modules _ I are connected with the I/O input unit through the MIN _1 IN the first scan switching network MAPPING _ IN, and the scan output channel is connected with the I/O output unit through the MIN _2 IN the second scan switching network MAPPING _ OUT. IN one embodiment, the first scanning switching network MAPPING _ IN and the second scanning switching network MAPPING _ OUT are both benes networks constructed IN the foregoing scheme. Because the number of scanning test channels is large, the module _ j to module _ t scanning input channel modules construct the same network, namely the scanning input channel is connected with the I/O input unit through MIN _3 IN the first scanning switching network MAPPING _ IN, and the scanning output channel is connected with the I/O output unit through MIN _4 IN the second scanning switching network MAPPING _ OUT. Therefore, the structural complexity of a single internet can be reduced, and the network construction process is more flexible.

In the case where the number of scan switching networks is one or more, the configuration unit (CONFIG) has not only a function of configuring the scan switching networks but also a function of gating output of test result data from a plurality of scan switching networks. Specifically, the configuration unit (CONFIG) outputs a strobe signal sel to the multiplexer MUX, outputs a test result of the module to be tested to the MUX through the channel _ map _ out, and gates and outputs the test result to a designated external output I/O port in a multiplexing manner.

EXAMPLE III

According to another aspect of the present invention, based on the network structure of scan test switching capable of being gated freely as shown in fig. 1, the present invention provides the following exemplary first scan test method, referring to fig. 4, the specific flow includes:

step S101, determining a configuration signal of a scanning switching network according to a module (to-be-tested module) to be tested.

The user can divide the test patterns according to the requirements. When determining that a specific module or a plurality of modules need to be tested, firstly, an input I/O port and a scan input channel of the module to be tested are appointed, and configuration parameters needed by a switching network are calculated according to a connection function used for constructing the scan switching network, namely, the input/output of each switching unit of the given switching network is calculated. Preferably, the scan switch network may be a benes multi-level interconnect network or other type of non-blocking, freely-strobable multi-level interconnect network. The configuration parameters are stored in a configuration unit (CONFIG).

Step S102, inputting the determined configuration signal into a scanning exchange network, and generating a path selection path of a scanning test channel, wherein the path selection path is formed by combining mapping exchange paths.

When the scanning test starts, the corresponding configuration signal is input into the scanning exchange network through the configuration signal port (swap [ m:0]) of the configuration unit (CONFIG), so as to realize the routing gating. The scanning exchange network is a multi-stage interconnection network which is free from blocking and can be freely gated, so that the gating path for generating any pair of I/O ports and scanning input channels can be controlled according to the configuration signal. Since the scan switch network includes a plurality of switch units, by combining the mapped switch paths between the switch units, the selection path from the I/O input port to the scan input channel can be obtained. In addition, after the path selection path of the scanning test channel is generated, the configuration unit provides a control signal for the I/O input unit, and the control signal is used for controlling the input/output state of the I/O input unit.

And step S103, scanning and testing the module to be tested through the I/O input unit according to the generated gating path.

Because the scan switching network has realized the free gating of the external I/O port and the test channel of the I/O input unit, the input data for testing can be sent from the external I/O port to the scan test channel scan _ channel to be tested through the corresponding mapping switching path, thereby realizing the scan test of the module to be tested.

Example four

According to another aspect of the present invention, based on the scan test switching network structure capable of being gated freely as shown in fig. 3, the present invention provides the following exemplary second scan test method, with reference to fig. 5, the specific flow includes:

step S201, determining configuration signals of the first scan switching network and the second scan switching network according to a module to be tested (i.e. a module to be tested).

When determining that a specific module or a plurality of modules need to be tested, firstly, an input I/O port, a scan input channel of the module to be tested, a scan output channel of the module to be tested and an output I/O port are specified, and configuration parameters needed by the first scan switching network and the second scan switching network are calculated according to a connection function used for constructing the scan switching network, namely, the input/output of each switching unit of the given switching network is calculated. The first scanning exchange network is a scanning exchange network between the input I/O port and a scanning input channel of the module to be tested, and the second scanning exchange network is a scanning exchange network between a scanning output channel of the module to be tested and the output I/O port. The scan switching network may be a benes multi-tier interconnect network. The configuration parameters are stored in a configuration unit (CONFIG).

Step S202, inputting the determined configuration signal into a first scanning exchange network and a second scanning exchange network, and generating a first gating path of the scanning input channel and a second gating path of the scanning output channel, wherein the gating paths are formed by combining mapping exchange paths.

When the scanning test is started, corresponding configuration signals are independently input into the first scanning exchange network and the second scanning exchange network through a configuration signal port (swap) of a configuration unit (CONFIG), and the routing gating is realized. The scanning exchange network is a multi-stage interconnection network which is free from blocking and free from gating, so that the generation of the routing path of any pair of input I/O ports and scanning input channels and the routing path of any pair of scanning output channels and output I/O ports can be controlled according to the configuration signals. Since the first and second scan switch networks respectively include a plurality of switch units, by combining the mapped switch paths between the switch units in the first and second scan switch networks respectively, the selection path from the I/O input port to the scan-in channel and the selection path from the scan-out channel to the I/O output port can be obtained. In addition, after the path selection path of the scan test channel is generated, the configuration unit provides control signals for the I/O input unit and the I/O output unit, and the control signals are used for controlling the input/output states of the I/O input unit and the I/O output unit.

Step S203, according to the generated first and second gating paths, scanning and testing the module to be tested through the input I/O port (I/O input unit), and outputting the test result data of the module to be tested through the output I/O port (I/O output unit).

Because the first and second scan switching networks have realized the free gating of the external input and output I/O ports and the test channels, the test instruction can be sent from the designated external input I/O port to the scan test channel scan _ channel to be tested through the corresponding mapping switching path, the input data channel _ in for testing is input into the module to be tested, the scan test of the module to be tested is realized, the test result data of the module to be tested is output to the multiplexer MUX through one of the channel _ map _ out, and the data is gated and output to the designated external output I/O port in a multiplexing mode.

Although the multi-level interconnect network is described as a benes network, in practical implementation, the benes network may be replaced by other non-blocking and freely-gated multi-level interconnect networks, such as a battery-ban lan network, an extended ban lan network, etc., according to the size and the requirement of a chip scale. The present invention is applicable to the multi-stage interconnect network as long as it can realize free gating without blocking.

In addition, it should be understood by those skilled in the art that the present invention includes, but is not limited to, the above-described structure, when the number of scan test channels is too large, more scan switching networks may be built, and on the premise that various types of interconnection networks can all realize the non-blocking free gating function by hardware, different types of multi-stage interconnection networks may also be used in combination.

Meanwhile, the structure of the switching unit also includes, but is not limited to, the above structure as long as a unit suitable for the scan switching network can be configured. The switching unit may also be optimized according to the actual requirements.

Compared with the traditional scanning test structure, the scanning test switching network capable of being gated freely provided by the technical scheme of the invention can realize routing gating through configuration after an I/O port and a scanning test channel are assigned arbitrarily, is convenient and flexible, and meets different test requirements. Meanwhile, the test mode and the pin distribution relation are not required to be determined in the initial design stage, so that the design cost can be obviously reduced.

While various embodiments of the present invention have been described above, various alternatives described in the various embodiments can be combined and cross-referenced without conflict to extend the variety of possible embodiments that can be considered disclosed and disclosed in connection with the embodiments of the present invention.

Although the embodiments of the present invention have been disclosed, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.