阅读说明：本技术 三维存储器 (Three-dimensional memory ) 是由 姚兰 薛磊 华子群 胡思平 严孟 尹朋岸 张宇澄 于 2021-08-09 设计创作，主要内容包括：本申请公开了一种三维存储器,该三维存储器包括外围晶圆和阵列晶圆。外围晶圆包括第一外围结构和第二外围结构；阵列晶圆包括衬底以及位于衬底之上的待测试结构和多个互连部,其中,衬底中包括第一阱区和第二阱区,待测试结构包括第一连接端和第二连接端,多个互连部包括：第一互连部,将第一外围结构与第一阱区电连接；第二互连部,将第一外围结构与待测试结构的第一连接端电连接；第三互连部,将第二外围结构与第二阱区电连接；以及第四互连部,将第二外围结构与待测试结构的第二连接端电连接。(The application discloses a three-dimensional memory, which comprises a peripheral wafer and an array wafer. The peripheral wafer comprises a first peripheral structure and a second peripheral structure; the array wafer comprises a substrate, a structure to be tested and a plurality of interconnection portions, wherein the structure to be tested and the interconnection portions are located on the substrate, the substrate comprises a first well region and a second well region, the structure to be tested comprises a first connection end and a second connection end, and the interconnection portions comprise: a first interconnection electrically connecting the first peripheral structure with the first well region; the second interconnection part is used for electrically connecting the first peripheral structure with the first connection end of the structure to be tested; a third interconnect electrically connecting the second peripheral structure with the second well region; and a fourth interconnecting portion electrically connecting the second peripheral structure with the second connection terminal of the structure to be tested.)

1. A three-dimensional memory comprises a peripheral wafer and an array wafer,

the peripheral wafer comprises a first peripheral structure and a second peripheral structure;

the array wafer comprises a substrate, and a structure to be tested and a plurality of interconnection portions, wherein the structure to be tested and the plurality of interconnection portions are located on the substrate, the substrate comprises a first well region and a second well region, the structure to be tested comprises a first connection end and a second connection end, and the plurality of interconnection portions comprise:

a first interconnect electrically connecting the first peripheral structure with the first well region;

a second interconnection electrically connecting the first peripheral structure with the first connection terminal of the structure to be tested;

a third interconnect electrically connecting the second peripheral structure with the second well region; and

a fourth interconnecting part electrically connecting the second peripheral structure with the second connecting terminal of the structure to be tested.

2. The three-dimensional memory according to claim 1, wherein the structure under test is a three-dimensional memory array comprising one or more three-dimensional memory strings, and the first connection terminal and the second connection terminal of the structure under test respectively comprise two ends of a word line in the three-dimensional memory string.

3. The three-dimensional memory according to claim 1,

each of the plurality of interconnections includes: at least one group of array wafer connecting blocks and array wafer conductor layers which are alternately stacked in the direction that the structure to be tested is close to the peripheral wafer;

the array wafer further comprises: a plurality of array wafer bonding contacts at the array wafer contact surface proximate to the peripheral wafer, an

And the array wafer contact blocks are respectively used for electrically connecting the interconnection parts and the array wafer bonding contact parts.

4. The three-dimensional memory according to claim 3, wherein the second interconnections and the fourth interconnections have the same number and regular arrangement of stacked structures formed by alternately stacking the array wafer connection blocks and the array wafer conductor layers.

5. The three-dimensional memory according to claim 3, wherein the second interconnect and the fourth interconnect are each electrically connected to one of the array wafer bonding contacts through the same number and structure of the array wafer contact blocks, respectively.

6. The three-dimensional memory according to claim 3, wherein the first peripheral structure comprises: a first peripheral wafer bonding contact and a second peripheral wafer bonding contact located at the contact face of the peripheral wafer proximate to the array wafer, wherein,

the first peripheral wafer bonding contact is electrically connected with the array wafer bonding contact to which the first interconnect is electrically connected;

the second peripheral wafer bonding contact is electrically connected with the array wafer bonding contact to which the second interconnect is electrically connected.

7. The three-dimensional memory according to claim 6, wherein the first peripheral structure further comprises:

a first peripheral circuit; and

and the first peripheral wafer contact block and the second peripheral wafer contact block are positioned in the direction that the first peripheral circuit is close to the array wafer and are respectively used for electrically connecting the first peripheral circuit to the first peripheral wafer bonding contact part and the second peripheral wafer bonding contact part.

8. The three-dimensional memory according to claim 3, further comprising a first contact in the array wafer, the first contact being located on a side of the first well region adjacent to the peripheral wafer to electrically connect the first well region with the first interconnect.

9. The three-dimensional memory according to claim 3, wherein the second peripheral structure comprises: a third peripheral wafer bonding contact and a fourth peripheral wafer bonding contact located at the contact face of the peripheral wafer proximate to the array wafer, wherein,

the third peripheral wafer bonding contact is electrically connected with the array wafer bonding contact to which the third interconnect is electrically connected;

the fourth peripheral wafer bonding contact is electrically connected with the array wafer bonding contact to which the fourth interconnect is electrically connected.

10. The three-dimensional memory according to claim 9, wherein the second peripheral structure further comprises:

a second peripheral circuit; and

and the third peripheral wafer contact block and the fourth peripheral wafer contact block are positioned in the direction that the second peripheral circuit is close to the array wafer and are respectively used for electrically connecting the second peripheral circuit to the third peripheral wafer bonding contact part and the fourth peripheral wafer bonding contact part.

11. The three-dimensional memory according to claim 3, further comprising a second contact in the array wafer, the second contact being located on a side of the second well region adjacent to the peripheral wafer to electrically connect the second well region with the third interconnect.

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a three-dimensional memory.

Background

According to the conventional three-dimensional memory, the memory array and the peripheral circuit are arranged on the array wafer and the peripheral wafer respectively, so that the problem that the peripheral circuit is influenced by high temperature and high pressure when the memory array is processed can be effectively solved, and higher memory density, simpler process flow and shorter cycle time can be realized. In this structure, after the two wafers are prepared, the two wafers can be bonded, and the bonded array wafer and the peripheral wafer can be connected to each other at the bonding interface through the bonding contact portion respectively disposed in the array wafer and the bonding contact portion disposed in the peripheral wafer.

In some cases, it is necessary to test or analyze the function of the structure to be tested TS included in the array wafer to improve the reliability of the structure to be tested TS, where the structure to be tested TS is a storage array including one or more three-dimensional storage strings, the left and right ends of the word line to be tested in the structure to be tested TS are respectively connected to one bonding contact portion in the array wafer, and the bonding process connects the structure to be tested TS included in the array wafer to the peripheral wafer.

However, in the prior art, because the circuit environments of the bonding contact portions connected to the left and right ends of the word line to be tested in the structure to be tested TS before bonding are different, the two bonding contact portions connected to the two ends of the structure to be tested TS form an unbalanced load with respect to the structure to be tested TS, and thus the problem of abnormal bonding in the subsequent bonding process can be caused. For example, before bonding, a bonding contact portion connected to one connection end of the structure to be tested TS is connected only to a word line to be tested in the structure to be tested TS and is not connected to the well region, and a bonding contact portion connected to the other connection end of the structure to be tested TS is connected to the well region having a large amount of active electrons in addition to the word line to be tested in the structure to be tested TS. In the following bonding process, it is necessary to perform chemical mechanical polishing on the side of the bonding contact portion exposed on the wafer surface in the array wafer, then perform activation treatment on the surface of the bonding contact portion by using charged ions, and then perform cleaning on the wafer by using deionized water, since the material of the bonding contact portion is usually copper, the bonding contact portion connected to both ends of the structure to be tested can generate electrochemical reaction such as electroplating reaction in the cleaning process. Causing the metal on the bonding contact to dissolve and causing defects such as metal missing (missing) or metal voids (void) to occur in the contact patch to which the bonding contact is connected. Thereby causing package failure or causing bonding reliability problems, resulting in serious economic loss.

Disclosure of Invention

The present application provides a three-dimensional memory that can at least partially address the above-identified problems in the prior art to address one or more of the problems that arise in the bonding process of the bonding contacts of the array wafer and the peripheral wafer.

According to an embodiment of the present disclosure, a three-dimensional memory is provided, the three-dimensional memory including a peripheral wafer and an array wafer, the peripheral wafer including a first peripheral structure and a second peripheral structure; the array wafer comprises a substrate, and a structure to be tested and a plurality of interconnection portions, wherein the structure to be tested and the plurality of interconnection portions are located on the substrate, the substrate comprises a first well region and a second well region, the structure to be tested comprises a first connection end and a second connection end, and the plurality of interconnection portions comprise: a first interconnect electrically connecting the first peripheral structure with the first well region; a second interconnection electrically connecting the first peripheral structure with the first connection terminal; a third interconnect electrically connecting the second peripheral structure with the second well region; and a fourth interconnection electrically connecting the second peripheral structure with the second connection terminal.

In one embodiment, the structure to be tested is a three-dimensional memory array including one or more three-dimensional memory strings, and the first connection terminal and the second connection terminal of the structure to be tested respectively include two ends of a word line in the three-dimensional memory strings.

In one embodiment, each of the plurality of interconnection portions includes: at least one group of array wafer connecting blocks and array wafer conductor layers which are alternately stacked in the direction that the structure to be tested is close to the peripheral wafer; the array wafer further comprises: the array wafer bonding contact parts are positioned at the contact surfaces of the array wafers close to the peripheral wafer, and the array wafer contact blocks are respectively used for electrically connecting the interconnection parts and the array wafer bonding contact parts.

In one embodiment, the second interconnection portion and the fourth interconnection portion have the same number and regular arrangement of stacked structures, and the stacked structures are formed by alternately stacking the array wafer connection blocks and the array wafer conductor layers.

In one embodiment, the second interconnect and the fourth interconnect are each electrically connected to one of the array wafer bonding contacts through the same number and configuration of the array wafer contact blocks, respectively.

In one embodiment, the first peripheral structure comprises: a first peripheral wafer bonding contact and a second peripheral wafer bonding contact located at the contact face of the peripheral wafer proximate to the array wafer, wherein the first peripheral wafer bonding contact is electrically connected with the array wafer bonding contact to which the first interconnect is electrically connected; the second peripheral wafer bonding contact is electrically connected with the array wafer bonding contact to which the second interconnect is electrically connected.

In one embodiment, the first peripheral structure further comprises: a first peripheral circuit; and a first peripheral wafer contact block and a second peripheral wafer contact block located in the direction of the first peripheral circuit close to the array wafer, for electrically connecting the first peripheral circuit to the first peripheral wafer bonding contact portion and the second peripheral wafer bonding contact portion, respectively.

In one embodiment, the array wafer further includes a first contact located on a side of the first well region close to the peripheral wafer, and electrically connects the first well region and the first interconnect.

In one embodiment, the second peripheral structure comprises: a third peripheral wafer bonding contact and a fourth peripheral wafer bonding contact located at the contact face of the peripheral wafer proximate to the array wafer, wherein the third peripheral wafer bonding contact is electrically connected with the array wafer bonding contact to which the third interconnect is electrically connected; the fourth peripheral wafer bonding contact is electrically connected with the array wafer bonding contact to which the fourth interconnect is electrically connected.

In one embodiment, the second peripheral structure further comprises: a second peripheral circuit; and a third peripheral wafer contact block and a fourth peripheral wafer contact block located in the direction where the second peripheral circuit is close to the array wafer, for electrically connecting the second peripheral circuit to the third peripheral wafer bonding contact portion and the fourth peripheral wafer bonding contact portion, respectively.

In one embodiment, the array wafer further includes a second contact located on a side of the second well region close to the peripheral wafer, and electrically connects the second well region and the third interconnect.

According to the three-dimensional memory disclosed by the disclosure, two ends of the structure to be tested are respectively connected to corresponding test pins (Micro Pad) through peripheral wafer jumpers, and the two ends of the structure to be tested are provided with loads which are symmetrical relative to the structure to be tested.

The above summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:

fig. 1A shows a schematic block diagram of an example of a conventional three-dimensional memory 100;

FIG. 1B shows an electron microscope view of the bonding interface of a conventional three-dimensional memory 100; and

fig. 2 shows a schematic block diagram of an example of a three-dimensional memory 100 according to an embodiment of the present disclosure.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, a first side discussed in this application may also be referred to as a second side, and a first window may also be referred to as a second window, or vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.

A schematic block diagram of an example of a three-dimensional memory 100 according to an embodiment of the present disclosure is shown in fig. 2.

As shown in fig. 2, memory 100 may include an array wafer 110 and a peripheral wafer 120. The array wafer 110 and the peripheral wafer 120 may be bonded to each other with a bonding interface S0 shown in the figure. Specifically, the peripheral wafer 120 may include a first peripheral structure 121-1 and a second peripheral structure 121-2. The array wafer 110 may include a substrate and a structure to be tested TS and a plurality of interconnects 123-1, 123-2, 123-3, and 123-4 over the substrate, and further, may include a first well region 115-1 and a second well region 115-2 therein. It should be noted that, for simplicity of illustration, fig. 2 only schematically illustrates the relative positions and connection relationships between the peripheral structures and the interconnection portions, and between the structures to be tested and the well regions, and the specific structures such as the substrate are not illustrated, and the content illustrated in fig. 2 is merely an example and is not limited.

The structure to be tested TS has a first connection terminal 112-1 and a second connection terminal 112-2. According to an exemplary embodiment, the array wafer 110 may further include a plurality of three-dimensional memory strings formed on the substrate, and the structure to be tested TS may be a three-dimensional memory array including one or more three-dimensional memory strings. The structure to be tested TS is represented in the form of a block diagram and a specific arrangement thereof is omitted for convenience of description in the present disclosure, but this schematic illustration is not intended to be limiting. In some embodiments, the three-dimensional memory may include gate layers (word lines) and insulating layers alternately stacked on a substrate, and further, a plurality of channel structures (not shown) extending to the substrate are formed through the alternately stacked gate layers and insulating layers, and the channel structures located in a core storage region of the three-dimensional memory may serve as three-dimensional memory strings. The structure to be tested TS may include a plurality of word lines connected to one or more three-dimensional memory strings, and one of the plurality of word lines may be selected as a word line to be tested. In this embodiment, the first connection terminal 112-1 may include one end of the word line to be tested, and the second connection terminal 112-2 may include the other end of the word line to be tested. However, the present disclosure is not limited thereto. In another exemplary embodiment, the structure to be tested TS may comprise more than one word line to be tested.

The array wafer 110 may also include a plurality of interconnects disposed on a side of the structure to be tested TS proximate to the bonding interface S0. For example, as shown in FIG. 2, the array wafer 110 may include a first interconnect 123-1, a second interconnect 123-2, and a third interconnect 123-3 and a fourth interconnect 123-4. The first interconnect 123-1 may electrically connect the first peripheral structure 121-1 with the first well region 115-1 located in the substrate of the array wafer 110. The second interconnection 123-2 may electrically connect the first peripheral structure 121-1 with the first connection terminal 112-1 of the structure to be tested TS. The third interconnect 123-3 may electrically connect the second peripheral structure 121-2 with the second well region 115-2 located in the substrate of the array wafer 110. The fourth interconnection 123-4 may electrically connect the second peripheral structure 121-2 with the second connection terminal 112-2 of the structure to be tested TS.

Further, each of the first to fourth interconnections 123-1 to 123-4 may include at least one set of array wafer connection blocks and array wafer conductor layers alternately stacked in a direction in which the structure to be tested TS approaches the peripheral wafer 120, respectively, that is, may be arranged in a manner of array wafer connection block 1-array wafer conductor layer 1-array wafer sub-connection block 2-array wafer conductor layer 2 … array wafer conductor layer n-array wafer connection block n. For example, in one embodiment, each interconnect may include a set of array wafer connection blocks and array wafer conductor layers, respectively, and specifically, the first interconnect 123-1 may include an array wafer connection block 131-1 and an array wafer conductor layer M1-1 stacked in sequence in a direction in which the structure to be tested TS approaches the peripheral wafer 120; the second interconnection 123-2 may include an array wafer connection block 131-2 and an array wafer conductor layer M1-2 sequentially stacked in a direction in which the structure to be tested TS approaches the peripheral wafer 120; the third interconnection 123-3 may include an array wafer connection block 131-3 and an array wafer conductor layer M1-3 sequentially stacked in a direction in which the structure to be tested TS approaches the peripheral wafer 120; the fourth interconnection 123-4 may include an array wafer connection block 131-4 and an array wafer conductor layer M1-4 sequentially stacked in a direction in which the structure to be tested TS approaches the peripheral wafer 120.

In another embodiment, each of the first to fourth interconnections 123-1 to 123-4 may include two sets of array wafer connection blocks and array wafer conductor layers, respectively, and specifically, as shown in fig. 2, the first interconnection 123-1 may include an array wafer connection block 131-1, an array wafer conductor layer M1-1, an array wafer connection block 133-1, and an array wafer conductor layer M2-1, which are sequentially stacked in a direction in which the structure to be tested TS approaches the peripheral wafer 120; the second interconnection 123-2 may include an array wafer connection block 131-2, an array wafer conductor layer M1-2, an array wafer connection block 133-2, and an array wafer conductor layer M2-2, which are sequentially stacked in a direction in which the structure to be tested TS is close to the peripheral wafer 120; the third interconnection 123-3 may include an array wafer connection block 131-3, an array wafer conductor layer M1-3, an array wafer connection block 133-3, and an array wafer conductor layer M2-3, which are sequentially stacked in a direction in which the structure to be tested TS is close to the peripheral wafer 120; the fourth interconnection 123-4 may include an array wafer connection block 131-4, an array wafer conductor layer M1-4, an array wafer connection block 133-4, and an array wafer conductor layer M2-4, which are sequentially stacked in a direction in which the structure to be tested TS approaches the peripheral wafer 120.

In an embodiment according to the present disclosure, the array wafer 110 may further include: a plurality of array wafer bonding contacts TVIA, the array wafer bonding contacts TVIA being located at a contact surface of the array wafer 110 close to the peripheral wafer 120; and a plurality of array wafer contact blocks (e.g., 135-1 to 135-4 in fig. 2) for electrically connecting the interconnections and the array wafer bonding contacts TVIA, respectively. More specifically, an array wafer contact block may electrically connect, for example, an array wafer conductor layer M included in an interconnect portion on a side close to the peripheral wafer 120 with an array wafer bonding contact portion TVIA. Referring to fig. 2, for example, the array wafer conductor layer M2-1 in the first interconnect 123-1 is electrically connected to the first array wafer bonding contact TVIA-1 through the array wafer contact block 135-1; the array wafer conductor layer M2-2 in the second interconnect 123-2 is electrically connected to the second array wafer bonding contact TVIA-2 through the array wafer contact block 135-2; the array wafer conductor layer M2-3 in the third interconnect 123-3 is electrically connected to the third array wafer bonding contact TVIA-3 through the array wafer contact block 135-3; the array wafer conductor layer M2-4 in the fourth interconnect 123-4 is electrically connected to the fourth array wafer bond contact TVIA-4 through the array wafer contact block 135-4. It should be understood that the illustration in fig. 2 is merely an example, and not a limitation, and in other embodiments, a plurality of metal contacts may be included on the array wafer conductor layer M1 or M2, for example, and a plurality of metal contacts on M2 may correspond to a plurality of array wafer contact blocks and may further correspond to a plurality of array wafer bonding contacts.

More specifically, the conductor layers in the array wafer 110 (e.g., the array wafer conductor layers M1-1 through M1-4, and the array wafer sub-conductor layers M2-1 through M2-4) may include conductor materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The connection blocks (e.g., array wafer connection blocks 131-1 to 131-4, and 133-1 to 133-4) in the array wafer 110 may be contact holes and/or contact trenches (e.g., formed by a wet etching process or a dry etching process) filled with a conductor (e.g., W). In some embodiments, filling the contact hole and/or the contact trench includes depositing a barrier layer, an adhesion layer, and/or a seed layer prior to depositing the conductor.

The material of the contact blocks (e.g., array wafer contact blocks 135-1 to 135-4) and the bonding contacts (e.g., array wafer bonding contacts TVIA-1 to TVIA-4) in the array wafer 110 may be copper, but the disclosure is not limited thereto. For example, in other embodiments, the contact bumps and bonding contacts in the array wafer 110 may be formed of a material such as aluminum (Al), tin (Sn). The contact block may be a contact hole and/or a contact trench (e.g., formed by a wet etch process or a dry etch process) filled with a conductor (e.g., W). The bonding contacts may be formed using the same process as the contact block, but may have a larger area relative to the contact block in a cross-section parallel to the bonding interface to form better contact when bonding. In some embodiments, filling the contact hole and/or the contact trench includes depositing a barrier layer, an adhesion layer, and/or a seed layer prior to depositing the conductor.

In one embodiment according to the present disclosure, the second interconnect 123-2 and the fourth interconnect 123-4 may have the same structural arrangement, for example, the second interconnect 123-2 and the fourth interconnect 123-4 may have the same number and regular arrangement of stacked structures, and the stacked structures may be formed by alternately stacking the array wafer connection blocks and the array wafer conductor layers. Specifically, as shown in fig. 2, the second interconnect 123-2 and the fourth interconnect 123-4 each have two sets of alternately stacked array wafer connection blocks (such as 131-2, 133-2, 131-4 and 133-4 shown in the figure) and array wafer conductor layers (such as M1-2, M2-2, M1-4 and M2-4 shown in the figure), and are arranged in a regular manner.

Further, in one embodiment according to the present disclosure, the second interconnect 123-2 and the fourth interconnect 123-4 are each electrically connected to one array wafer bonding contact through the same number and structure of array wafer contact blocks, respectively. For example, the second interconnect 123-2 is electrically connected to the second array of wafer bonding contacts TVIA-2 through one array of wafer contact blocks 135-2, and the fourth interconnect 123-4 is also electrically connected to the fourth array of wafer bonding contacts TVIA-4 through one array of wafer contact blocks 135-4, wherein the array of wafer contact blocks 135-2 and the array of wafer contact blocks 135-4 have the same structure.

In conjunction with the foregoing, in the case where the array wafer 110 and the peripheral wafer 120 are not bonded to each other, the first connection terminal 112-1 of the structure to be tested TS is electrically connected to the second array wafer bonding contact TVIA-2 through the second interconnection 123-2 and the array wafer contact block 135-2, and the second connection terminal 112-2 of the structure to be tested TS is electrically connected to the fourth array wafer bonding contact TVIA-4 through the fourth interconnection 123-4 and the array wafer contact block 135-4. The second interconnect 123-2 and the fourth interconnect 123-4 may have the same structure, and the array wafer contact block 135-2 and the array wafer contact block 135-4 may also have the same structure.

The above-described embodiments disclosed in the present application have one or more beneficial technical effects over the prior art. A comparative description will be made below in conjunction with fig. 1A and 1B, in which fig. 1A shows a schematic structural diagram of one example of a conventional three-dimensional memory 100; fig. 1B shows an electron microscope view of a bonding interface of the conventional three-dimensional memory 100. As can be seen from fig. 1A, before the array wafer 110 is bonded to the peripheral wafer 120, the first connection terminal 112-1 of the structure to be tested TS is connected to the first array wafer bonding contact TVIA-1 through the metal layer M1-1, the metal layer M2-1 and the array wafer contact block 135-1, and the first connection terminal 112-1 is also connected to the first well region 115-1 through the metal layer M1-1 and the first contact 116-1. The second connection terminal 112-2 is connected to the fourth array wafer bonding contact TVIA-4 via the fourth interconnect 123-4 and the array wafer contact block 135-4 before the array wafer 110 is bonded to the peripheral wafer 120, i.e., the second connection terminal 112-2 is not connected to the second well region 115-2 before bonding. Therefore, in this case, the circuit environments of the bonding contacts TVIA-1 and TVIA-4 connected to the left and right ends of the word line to be tested in the structure to be tested TS are different. For example, bonding contact TVIA-4 is connected only to the word line to be tested in structure to be tested TS, and bonding contact TVIA-1 is connected to well region 115-1 having a large number of active electrons in addition to being connected to the word line to be tested in structure to be tested TS. That is, the bonding contacts TVIA-1 and TVIA-4 create an unbalanced load with respect to the structure TS to be tested.

As previously described, such unbalanced loading may cause bonding anomalies during the bonding process. Specifically, in the bonding process, it is required to perform chemical mechanical polishing on the side of the bonding contact TVIA exposed on the wafer surface in the array wafer 110, then perform activation processing on the surface of the bonding contact TVIA by using charged ions, and then perform cleaning on the wafer by using deionized water, since the material of the bonding contact TVIA is usually copper, the bonding contact TVIA connected to both ends of the structure to be tested TS may generate an electrochemical reaction such as an electroplating reaction in the cleaning process. Further, as shown in fig. 1A, since the bonding contact TVIA-1 is connected to a P-well having a large number of active electrons, it may serve as a cathode in the plating reaction, and the bonding contact TVIA-4 is not connected to the P-well, it may serve as an anode in the plating reaction, which may cause dissolution of metal on the bonding contact TVIA-4, and may cause defects such as metal missing (missing) or metal void (void) to occur in the contact block 135-4 to which the bonding contact TVIA-4 is connected, as in the case where a portion (corresponding to the portion of the contact block 135-4 in fig. 1A) within a dotted frame shown in the electron micrograph of fig. 1B generates defects. This may cause package failure or cause bonding reliability problems, and wafers having the above defects are disposed of according to the visual inspection standards of semiconductor wafers, thereby causing serious economic loss.

In contrast, according to the above-mentioned embodiment disclosed in the present application, as can be seen in conjunction with fig. 2 and the foregoing, by providing the second interconnection 123-2 and the array wafer contact block 135-2 and the second array wafer bonding contact TVIA-2, the circuit components connected to the first connection terminal 112-1 and the second connection terminal 112-2 of the structure to be tested TS respectively have substantially the same configuration corresponding to each other before the bonding process, so that the first connection terminal 112-1 and the second connection terminal 112-2 of the structure to be tested TS have balanced and symmetrical loads with respect to the structure to be tested TS. Before the bonding process, since the array wafer 110 and the peripheral wafer 120 are not bonded to each other and are in a separated state, the array wafer bonding contact portion TVIA-2 of the first connection terminal 112-1 of the structure to be tested TS connected through the second interconnection 123-2 is not connected to the first peripheral structure 121-1 and is not connected to the first well region 115-1; likewise, the array wafer bonding contact portion TVIA-4 of the structure to be tested TS, to which the second connection terminal 112-2 is connected through the fourth interconnection 123-4, is not connected to the second peripheral structure 121-2 and thus is not connected to the second well region 115-2. That is, before the bonding process, the first connection terminal 112-1 and the second connection terminal 112-2 of the structure to be tested TS are not connected to the well region, and both have the same circuit environment. The design of balanced symmetry can greatly reduce the influence of electroplating reaction possibly occurring in the wafer bonding process on the wafer structure connection part, effectively avoid the generation of metal holes and greatly improve the bonding reliability.

The specific configuration of the first and second peripheral structures 121-1 and 121-2 in the peripheral wafer 120 will be further described with reference to fig. 2.

The first peripheral structure 121-1 may include a first peripheral wafer bonding contact BVIA-1 and a second peripheral wafer bonding contact BVIA-2, both of which may be located at a contact surface of the peripheral wafer 120 close to the array wafer 110, wherein the first peripheral wafer bonding contact BVIA-1 may be electrically connected to the first array wafer bonding contact TVIA-1 electrically connected to the first interconnect 123-1, and further electrically connected to the first well region 115-1 through the first interconnect 123-1; the second peripheral wafer bonding contact BVIA-2 may be electrically connected to the second array of wafer bonding contacts TVIA-2 electrically connected to the second interconnect 123-2, and further electrically connected to the first connection terminal 112-1 of the structure to be tested TS through the second interconnect 123-2.

Further, the first peripheral structure 121-1 may further include a first peripheral circuit 141-1 disposed on a side of the substrate (not shown) of the peripheral wafer 120 facing the bonding interface S0 and configured to provide a control signal for the first connection terminal 112-1 of the structure to be tested TS in a non-test state so as to control an operation of the structure to be tested TS. In a test state, the first peripheral circuit 141-1 may be in a floating state, at which time an external test signal for the structure to be tested TS is received from the outside via the first test pin, as will be described in detail below. And, the first peripheral structure 121-1 may further include a first peripheral wafer contact block 143-1 and a second peripheral wafer contact block 143-2, which may be located in a direction in which the first peripheral circuit 141-1 approaches the array wafer 110, and are used to electrically connect the first peripheral circuit 141-1 to the first peripheral wafer bonding contact BVIA-1 and the second peripheral wafer bonding contact BVIA-2, respectively.

Similar to the first peripheral structure 121-1, the second peripheral structure 121-2 may include a third peripheral wafer bonding contact BVIA-3 and a fourth peripheral wafer bonding contact BVIA-4, both of which may be located at a contact surface of the peripheral wafer 120 close to the array wafer 110, wherein the third peripheral wafer bonding contact BVIA-3 may be electrically connected to a third array wafer bonding contact TVIA-3 to which a third interconnect 123-3 is electrically connected, and further, to the second well region 115-2 through the third interconnect 123-3; fourth peripheral wafer bond contact BVIA-4 may be electrically connected to fourth array of wafer bond contacts TVIA-4 to which fourth interconnect 123-4 is electrically connected, and further electrically connected to second connection terminal 112-2 of structure under test TS through fourth interconnect 123-4.

Further, the second peripheral structure 121-2 may include a second peripheral circuit 141-2 disposed on a side of the substrate (not shown) of the peripheral wafer 120 facing the bonding interface S0 and may be configured to provide a control signal for the second connection terminal 112-2 of the structure to be tested TS in a non-test state so as to control an operation of the structure to be tested TS. It should be understood that in the non-test state, there may be cases where only one peripheral circuit is needed to provide control signals for the structure TS to be tested, e.g., in one embodiment, the second peripheral structure 121-2 may include the second peripheral circuit 141-2, while the first peripheral structure 121-1 may not include the peripheral circuit 141-1, including only, e.g., one metal conductor layer as a conductive path. In a test state, the second peripheral circuit 141-2 may be in a floating state, at which time an external test signal for the structure to be tested TS is received from the outside via the second test pin, as will be described in detail below. And, the second peripheral structure 121-2 may further include a third peripheral wafer contact block 143-3 and a fourth peripheral wafer contact block 143-4, which may be located in a direction in which the second peripheral circuit 141-2 approaches the array wafer 110, and are respectively used to electrically connect the second peripheral circuit 141-2 to the third peripheral wafer bonding contact BVIA-3 and the fourth peripheral wafer bonding contact BVIA-4.

In an embodiment according to the present disclosure, the material of the contact bumps (e.g., peripheral wafer contact bumps 143-1 to 143-4) and the bonding contacts (e.g., peripheral wafer bonding contacts BVIA-1 to BVIA-4) in peripheral wafer 120 may be copper, but the present disclosure is not limited thereto. For example, in other embodiments, the contact bumps and bonding contacts in the peripheral wafer 120 may be formed of materials such as Al, Sn. The contact blocks in peripheral wafer 120 may be contact holes and/or contact trenches (e.g., formed by a wet etch process or a dry etch process) filled with a conductor (e.g., W). The bonding contacts in the peripheral wafer 120 may be formed using the same process as the contact blocks, but may have a larger area relative to the contact blocks in a cross-section parallel to the bonding interface to form better contact when bonding. In some embodiments, filling the contact hole and/or the contact trench includes depositing a barrier layer, an adhesion layer, and/or a seed layer prior to depositing the conductor.

Referring again to fig. 2, in an embodiment of the present disclosure, the array wafer 110 may further include a first contact 116-1, the first contact 116-1 may be located on a side of the first well region 115-1 close to the peripheral wafer 120, and the first contact 116-1 may electrically connect the first well region 115-1 and the first interconnection 123-1. The first well region 115-1 may be a doped region disposed on a side of the substrate (not shown) proximate to the bonding interface S0. In an embodiment, the first well region 115-1 may be a P-type doped region, which may be a region formed by doping an N-type semiconductor as a substrate with any suitable P-type dopant, for example, boron (B), gallium (Ga), or aluminum (Al), i.e., a P-well. However, the present disclosure is not limited thereto. In another embodiment, the first well regions 115-1 may be regions formed in a P-type semiconductor as a substrate, i.e., N-wells, respectively, doped with any suitable N-type dopant, e.g., phosphorus (P), arsenic (Ar), or antimony (Sb).

In yet another embodiment according to the present disclosure, a second contact 116-2 may be further included in the array wafer 110, the second contact 116-2 may be located on a side of the second well region 115-2 near the peripheral wafer 120, and the second contact 116-2 may electrically connect the second well region 115-2 with the third interconnect 123-3. The second well region 115-2 may be formed by the same process as the first well region 115-1. That is, in the case where the first well region 115-1 is a P-well provided in an N-type substrate, the second well region 115-2 is also a P-well, and in the case where the first well region is an N-well provided in a P-type substrate, the second well region 115-2 is also an N-well.

As can be seen from the above, the first peripheral wafer bonding contact BVIA-1 may be electrically connected to the first interconnect 123-1 through the first array wafer bonding contact TVIA-1, specifically, the first array wafer bonding contact TVIA-1 in the array wafer 110 may be exposed from the side of the array wafer 110 facing the bonding interface S0 and may be electrically connected to the first peripheral wafer bonding contact BVIA-1 in the first peripheral structure 121-1 through the bonding process, and the array wafer connection block 131-1 in the first interconnect 123-1 is electrically connected to the first contact 116-1 and further electrically connected to the first test pin (not shown in the figure). Still further, in one embodiment, a first test pin (not shown) for receiving an external test signal applied to an end of the word line under test at the first connection end 112-1 may be disposed on a side surface of the substrate below the first well region 115-1 facing away from the bonding interface S0. The first test pin may be connected to the first contact 116-1 through a first contact structure (not shown) that extends through the first well region 115-1 and the substrate below it. Similarly, second peripheral wafer bond contact BVIA-2 may be electrically connected to second interconnect 123-2 through second array wafer bond contact TVIA-2, and array wafer bond contact TVIA-2 in array wafer 110 may also be exposed from a side of array wafer 110 facing bonding interface S0 and may be electrically connected to second peripheral wafer bond contact BVIA-2 in first peripheral structure 121-1 through a bonding process. In one embodiment, at an end of the second interconnect 123-2 near the structure to be tested TS, the second interconnect 123-2 may be electrically connected to the first connection terminal 112-1 of the structure to be tested TS through the array wafer connection block 131-2 included therein. Thereby forming an electrical connection path from the first test pin through the first well region 115-1, the first interconnect 123-1, the first peripheral structure 121-1 and the second interconnect 123-2 in sequence to the first connection terminal 112-1 of the structure to be tested TS. In this way, in a test state, an external test signal for one end (e.g., one end included in the first connection terminal 112-1) of a word line to be tested in the structure to be tested TS may be received from the outside via the first test pin. It should be noted that, in the test state, the signal applied to one end of the word line to be tested at the first connection terminal 112-1 of the structure to be tested TS is an external test signal received through the first test pin, and at this time, the first peripheral circuit 141-1 connected at the first connection terminal 112-1 may be in a floating state, i.e., the first peripheral circuit 141-1 may be regarded as functioning only as a conductive connection such as the first interconnect 123-1 and the second interconnect 123-2 in this case. In the present disclosure, the first test pin and the first contact structure are not shown in the drawings for the sake of simplifying the schematic structure and the related description.

On the other hand, the third peripheral wafer bonding contact BVIA-3 may be electrically connected to the third interconnect 123-3 through the array wafer bonding contact TVIA-3 in the array wafer 110, specifically, the array wafer bonding contact TVIA-3 may be exposed from the side of the array wafer 110 facing the bonding interface S0 and may be electrically connected to the third peripheral wafer bonding contact BVIA-3 in the second peripheral structure 121-2 through the bonding process, and the array wafer connection block 131-3 in the third interconnect 123-3 is electrically connected to the second contact 116-2 and further electrically connected to the second test pin (not shown). Still further, in some embodiments, a second test pin (not shown) for receiving an external test signal applied to the other end of the word line under test at the second connection terminal 112-2 may be disposed on a side surface of the substrate below the second well region 115-2 facing away from the bonding interface S0. The second test pin may be connected to the second contact 116-2 by a second contact structure (not shown) that extends through the second well region 115-2 and the substrate below it. Similarly, fourth peripheral wafer bond contact BVIA-4 may be electrically connected to fourth interconnect 123-4 through array wafer bond contact TVIA-4 in array wafer 110, and array wafer bond contact TVIA-4 in array wafer 110 may also be exposed from the side of array wafer 110 facing bonding interface S0 and may be electrically connected to fourth peripheral wafer bond contact BVIA-4 in second peripheral structure 121-2 through a bonding process. In one embodiment, at an end of the fourth interconnect 123-4 near the structure to be tested TS, the fourth interconnect 123-4 may be electrically connected to the second connection terminal 112-2 of the structure to be tested TS through the array wafer connection block 131-4 included therein. Thereby forming an electrical connection path from the second test pin to the second connection terminal 112-2 of the structure to be tested TS via the second well region 115-2, the third interconnect 123-3, the second peripheral structure 121-2 and the fourth interconnect 123-4 in that order. In this way, in the test state, an external test signal for the other end (e.g., one end included in the second connection terminal 112-2) of the word line to be tested in the structure to be tested TS may be received from the outside via the second test pin. Also, it should be noted that in the test state, the signal applied to one end of the word line to be tested at the second connection terminal 112-2 of the structure to be tested TS is an external test signal received through the second test pin, and at this time, the second peripheral circuit 141-2 connected at the second connection terminal 112-2 may be in a floating state, i.e., the second peripheral circuit 141-2 may be regarded as functioning only as a conductive connection (e.g., the third interconnect 123-3 and the fourth interconnect 123-4) in this case. In the present disclosure, the second test pin and the second contact structure are not shown in the drawings for the sake of simplifying the schematic structure and the related description.

It can be seen that after the bonding process, the first connection terminal 112-1 of the structure to be tested TS is connected to the first test pin through the second interconnection portion 123-2, the first peripheral structure 121-1, the first interconnection portion 123-1 and the first well region 115-1 in sequence, and symmetrically, the second connection terminal 112-2 of the structure to be tested TS is connected to the second test pin through the fourth interconnection portion 123-4, the second peripheral structure 121-2, the third interconnection portion 123-3 and the second well region 115-2 in sequence. The conductive paths formed by the second interconnect 123-2 in the array wafer, the first peripheral structure 121-1 in the peripheral wafer, and the first interconnect 123-1 in the array wafer can be regarded as a first group of jumper structures, and the conductive paths formed by the fourth interconnect 123-4 in the array wafer, the second peripheral structure 121-2 in the peripheral wafer, and the third interconnect 123-3 in the array wafer can be regarded as a second group of jumper structures. After the bonding process, two connection ends of the structure to be tested TS respectively form two groups of jumper structures symmetrical with respect to the structure to be tested TS through the interconnection structure in the array wafer and the peripheral structure in the peripheral wafer, so that the two connection ends of the structure to be tested TS are respectively connected to corresponding test pins through the symmetrical jumper structures formed at the two ends.

Before the bonding process, as described above, the first connection terminal 112-1 and the second connection terminal 112-2 of the structure to be tested TS have balanced and symmetrical loads with respect to the structure to be tested TS, and the first connection terminal 112-1 and the second connection terminal 112-2 of the structure to be tested TS are not connected to the well region, and both have the same circuit environment. The design of balanced symmetry can greatly reduce the influence of electroplating reaction possibly occurring in the wafer bonding process on the wafer structure connection part, is beneficial to improving the bonding reliability and ensures the performance quality of the three-dimensional memory.

In an embodiment, although not specifically shown, the word lines of the structure to be tested TS may be symmetrically arranged with respect to the structure to be tested, and thus, it will be understood by those skilled in the art that signals applied to the first and second connection terminals 112-1 and 112-2 (i.e., both ends of the word lines) of the structure to be tested TS may be the same signal. For example, in the test state, the external test signals supplied from the first test pin and the second test pin for applying to both ends of a word line to be tested among the word lines may be the same signal; in the non-test state, the control signals supplied from the first and second peripheral circuits 141-1 and 141-2 to be applied to both ends of the word line may be the same signal, and the first and second peripheral circuits 141-1 and 141-2 may have the same configuration.

In an embodiment, the first and second peripheral circuits 141-1 and 141-2 may comprise peripheral wafer devices that may generate any suitable digital, analog, and/or mixed signals for facilitating operation of the three-dimensional memory 100. For example, the peripheral wafer devices may include one or more of page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references, or any active or passive component of a circuit (e.g., a transistor, diode, resistor, or capacitor).

In an embodiment according to the present disclosure, the first and second peripheral circuits 141-1 and 141-2 may schematically represent driver circuits for generating input signals required for the structure to be tested TS, for example, the first peripheral circuit 141-1 may represent a first driver circuit connectable to one end of a word line of the structure to be tested TS, and the second peripheral circuit 141-2 may represent a second driver circuit connectable to the other end of the word line of the structure to be tested, but the present disclosure is not limited thereto. In an embodiment, as described above, since the first and second peripheral circuits 141-1 and 141-2 are connected to both ends of the word line, the first and second peripheral circuits 141-1 and 141-2 may have the same configuration.

In summary, in the three-dimensional memory according to the embodiment of the disclosure, the circuit environments of the loads (for example, the array wafer bonding contact portions TVIA) respectively connected to the two connection ends of the structure TS to be tested have a symmetrical design with respect to the structure TS to be tested, and the symmetrical design can greatly reduce the influence of the electroplating reaction possibly occurring in the wafer bonding process on the connection portion of the wafer structure, effectively avoid the generation of metal voids (for example, copper voids), and improve the bonding reliability.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.