阅读说明：本技术 半导体器件的制造方法 (Method for manufacturing semiconductor device ) 是由 周海洋 沈思杰 于 2021-08-20 设计创作，主要内容包括：本发明提供了一种半导体器件的制造方法,包括：提供衬底,所述衬底上依次形成有浮栅材料层和控制栅材料层,所述浮栅材料层和所述控制栅材料层上形成有暴露所述衬底的开口,所述开口两侧的所述控制栅材料层上形成有第一侧墙；在所述第一侧墙的侧壁上形成氧化层；确定待形成的控制栅的宽度为一设定值,根据所述第一侧墙的宽度、所述氧化层的厚度与所述设定值的关系,对所述第一侧墙和/或所述氧化层进行刻蚀,以调整所述第一侧墙和/或所述氧化层的宽度；以及,以所述第一侧墙,或所述第一侧墙和所述氧化层为掩模刻蚀所述控制栅材料层,形成控制栅。本发明提供的半导体器件的制造方法控制了形成的控制栅的宽度,提高了半导体器件的性能。(The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a floating gate material layer and a control gate material layer are sequentially formed on the substrate, openings for exposing the substrate are formed on the floating gate material layer and the control gate material layer, and first side walls are formed on the control gate material layer on two sides of the openings; forming an oxide layer on the side wall of the first side wall; determining the width of a control gate to be formed as a set value, and etching the first side wall and/or the oxide layer according to the relationship between the width of the first side wall, the thickness of the oxide layer and the set value so as to adjust the width of the first side wall and/or the oxide layer; and etching the control gate material layer by using the first side wall or the first side wall and the oxide layer as masks to form a control gate. The manufacturing method of the semiconductor device controls the width of the formed control gate and improves the performance of the semiconductor device.)

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein a floating gate material layer and a control gate material layer are sequentially formed on the substrate, openings for exposing the substrate are formed on the floating gate material layer and the control gate material layer, and first side walls are formed on the control gate material layer on two sides of the openings;

forming an oxide layer on the side wall of the first side wall;

determining the width of a control gate to be formed as a set value, and etching the first side wall and/or the oxide layer according to the relationship between the width of the first side wall, the thickness of the oxide layer and the set value so as to adjust the width of the first side wall and/or the oxide layer; and the number of the first and second groups,

and etching the control gate material layer by taking the first side wall or the first side wall and the oxide layer as masks to form a control gate.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the opening comprises:

forming a hard mask layer on the control gate material layer, and etching the hard mask layer to form a first opening exposing the control gate material layer;

forming first side walls on the control gate material layer on two sides of the first opening;

etching the control gate material layer by taking the first side wall and the hard mask layer as masks to form a second opening exposing the floating gate material layer;

forming second side walls on the floating gate material layer on two sides of the second opening;

etching the floating gate material layer with the second sidewall, the first sidewall and the hard mask layer as masks to form a third opening exposing the substrate,

and forming third side walls on the substrate at two sides of the third opening to finish etching of the opening.

3. The method for manufacturing the semiconductor device according to claim 2, wherein a width of the first sidewall is half a difference between a cross-sectional width of the first opening and a cross-sectional width of the second opening.

4. The method for manufacturing a semiconductor device according to claim 2, wherein after the forming of the opening and before the forming of the oxide layer, further comprises:

and forming an erasing grid in the opening.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the substrate includes a peripheral region and a storage region, and wherein the floating gate material layer and the control gate material layer are formed in the storage region and the peripheral region.

6. The method for manufacturing the semiconductor device according to claim 5, wherein the step of forming the oxide layer on the sidewalls of the first sidewalls comprises:

removing the hard mask layer, the control gate material layer and the floating gate material layer of the peripheral region to expose the substrate of the peripheral region;

forming a gate material layer on the substrate of the peripheral region, and extending to cover the hard mask layer and the erasing gate of the storage region;

removing the hard mask layer in the storage region and the gate material layer on the hard mask layer to expose the erase gate surface, the side wall of the first side wall and part of the control gate material layer of the storage region;

forming an oxide layer on the gate material layer, wherein the oxide layer extends to cover the surfaces of the control gate material layer and the erase gate in the storage region and the side wall of the first side wall; and the number of the first and second groups,

and forming a patterned photoresist layer on the oxide layer, and etching the gate material layer by taking the patterned photoresist layer as a mask so as to form a gate in the peripheral area.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the oxide layer has a thickness of

8. The method for manufacturing a semiconductor device according to claim 1 or 6, wherein the first sidewall spacer and/or the oxide layer are etched by a wet etching process.

9. The method for manufacturing a semiconductor device according to claim 8, wherein a process time of the wet etching process is a set time, and the set time is adjusted according to a relationship between a width of the first sidewall, a thickness of the oxide layer, and the set value.

10. The manufacturing method of a semiconductor device according to claim 1, wherein the manufacturing method of a semiconductor device is used for manufacturing a flash memory device.

Technical Field

The invention relates to the technical field of integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device.

Background

The flash memory device can store information under the condition of no power-on, has the advantages of high integration level, high access speed, easy erasing and the like, and is widely applied to various fields such as microcomputer, automatic control and the like.

The existing flash memory device generally comprises a substrate and a gate structure arranged on the surface of the substrate, wherein the gate structure comprises a floating gate and a control gate which are sequentially arranged on the substrate, and a side wall is arranged at the top of the control gate. If the size of the control gate is too small, the capacitance of the control gate is correspondingly reduced, and the induced voltage between the floating gate and the control gate is also reduced, thereby affecting the performance of the flash memory device. If the size of the control gate is too large, the gap between two adjacent gate structures is very narrow, and a void (void) is easily generated in the process of forming an interlayer dielectric layer on the substrate and the gate structures, so that the appearance and the performance of the flash memory device are influenced.

In order to avoid the influence of the too large or too small size of the control gate on the performance of the flash memory device, it is necessary to ensure that the actual size of the control gate is the same as the design size. However, the actual size of the control gate is related to the actual size of the sidewall, which is affected by multiple processes. For example, in the process of forming the side walls, the widths of the side walls formed on the surfaces of the semiconductor devices in different batches are different; for another example, in the subsequent wet etching process for the semiconductor device, the etchant may etch back the sidewall so as to change the width of the sidewall.

In view of this, there is a need for a method of controlling the size of a control gate in a flash memory device.

Disclosure of Invention

The invention aims to provide a manufacturing method of a semiconductor device, which is characterized in that according to the relation between the width of a first side wall, the thickness of an oxide layer and the width of a control gate to be formed, the first side wall and/or the oxide layer are correspondingly etched to adjust the width of the first side wall and/or the oxide layer used as an etching control gate mask, and further the width of the control gate to be formed subsequently is controlled.

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein a floating gate material layer and a control gate material layer are sequentially formed on the substrate, openings for exposing the substrate are formed on the floating gate material layer and the control gate material layer, and first side walls are formed on the control gate material layer on two sides of the openings;

forming an oxide layer on the side wall of the first side wall;

determining the width of a control gate to be formed as a set value, and etching the first side wall and/or the oxide layer according to the relationship between the width of the first side wall, the thickness of the oxide layer and the set value so as to adjust the width of the first side wall and/or the oxide layer; and the number of the first and second groups,

and etching the control gate material layer by taking the first side wall or the first side wall and the oxide layer as masks to form a control gate.

Optionally, the forming of the opening includes:

forming a hard mask layer on the control gate material layer, and etching the hard mask layer to form a first opening exposing the control gate material layer;

forming first side walls on the control gate material layer on two sides of the first opening;

etching the control gate material layer by taking the first side wall and the hard mask layer as masks to form a second opening exposing the floating gate material layer;

forming second side walls on the floating gate material layer on two sides of the second opening;

etching the floating gate material layer with the second sidewall, the first sidewall and the hard mask layer as masks to form a third opening exposing the substrate,

and forming third side walls on the substrate at two sides of the third opening to finish etching of the opening.

Optionally, the width of the first sidewall is half of a difference between the width of the cross section of the first opening and the width of the cross section of the second opening.

Optionally, after forming the opening, before forming the oxide layer, the method further includes:

and forming an erasing grid in the opening.

Optionally, the substrate includes a peripheral region and a storage region, and the floating gate material layer and the control gate material layer are formed in the storage region and the peripheral region.

Optionally, the process of forming the oxide layer on the sidewall of the first sidewall spacer includes:

removing the hard mask layer, the control gate material layer and the floating gate material layer of the peripheral region to expose the substrate of the peripheral region;

forming a gate material layer on the substrate of the peripheral region, and extending to cover the hard mask layer and the erasing gate of the storage region;

removing the hard mask layer in the storage region and the gate material layer on the hard mask layer to expose the erase gate surface, the side wall of the first side wall and part of the control gate material layer of the storage region;

forming an oxide layer on the gate material layer, wherein the oxide layer extends to cover the surfaces of the control gate material layer and the erase gate in the storage region and the side wall of the first side wall; and the number of the first and second groups,

and forming a patterned photoresist layer on the oxide layer, and etching the gate material layer by taking the patterned photoresist layer as a mask so as to form a gate in the peripheral area.

Optionally, the thickness of the oxide layer is

Optionally, a wet etching process is used to etch the first sidewall and/or the oxide layer.

Optionally, the process time of the wet etching process is a set time, and the set time is adjusted according to the relationship between the width of the first sidewall, the thickness of the oxide layer, and the set value.

Optionally, the manufacturing method of the semiconductor device is used for manufacturing a flash memory device.

In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, wherein a floating gate material layer and a control gate material layer are sequentially formed on the substrate, openings for exposing the substrate are formed on the floating gate material layer and the control gate material layer, and first side walls are formed on the control gate material layer on two sides of the openings; forming an oxide layer on the side wall of the first side wall; determining the width of a control gate to be formed as a set value, and etching the first side wall and/or the oxide layer according to the relationship between the width of the first side wall, the thickness of the oxide layer and the set value so as to adjust the width of the first side wall and/or the oxide layer; and etching the control gate material layer by using the first side wall or the first side wall and the oxide layer as masks to form a control gate. According to the invention, according to the relation between the width of the first side wall, the thickness of the oxide layer and the width of a control gate to be formed, the first side wall and/or the oxide layer are correspondingly etched to adjust the width of the first side wall and/or the oxide layer used as an etching control gate mask, so that the width of a subsequently formed control gate is controlled, and the performance of a semiconductor device is improved.

Drawings

Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 2-12 are schematic structural diagrams corresponding to respective steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

wherein the reference numbers are as follows:

100-a substrate; 110-a first dielectric layer; 120-a layer of floating gate material; 121-floating gate;

130-a second dielectric layer; 140-a control gate material layer; 141-a control gate; 150-a hard mask layer;

160-opening; 161-first side wall; 162-a second side wall; 163-third side wall;

170-erase gate; 180-a layer of gate material; 181-an oxide layer; 182-a photoresist layer; 183-grid;

x1-peripheral region; x2-storage area.

Detailed Description

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to fig. 1, the method for manufacturing a semiconductor device according to the present embodiment includes:

step S01: providing a substrate, wherein a floating gate material layer and a control gate material layer are sequentially formed on the substrate, openings for exposing the substrate are formed on the floating gate material layer and the control gate material layer, and first side walls are formed on the control gate material layer on two sides of the openings;

step S02: forming an oxide layer on the side wall of the first side wall;

step S03: determining the width of a control gate to be formed as a set value, and etching the first side wall and/or the oxide layer according to the relationship between the width of the first side wall, the thickness of the oxide layer and the set value so as to adjust the width of the first side wall and/or the oxide layer;

step S04: and etching the control gate material layer by taking the first side wall or the first side wall and the oxide layer as masks to form a control gate.

Fig. 2 to fig. 12 are schematic structural diagrams corresponding to respective steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention. The method for fabricating the semiconductor structure according to the present embodiment will be described in detail with reference to fig. 2 to 12.

First, referring to fig. 2-5, step S01 is executed to provide a substrate 100, a floating gate material layer 120 and a control gate material layer 140 are sequentially formed on the substrate 100, an opening 160 exposing the substrate 100 is formed on the floating gate material layer 120 and the control gate material layer 140, and a first sidewall 161 is formed on the control gate material layer 140 on two sides of the opening 160. In this embodiment, the substrate 100 includes a storage region X1 and a peripheral region X2, and the floating gate material layer 120 and the control gate material layer 140 are formed in the storage region X1 and the peripheral region X2. Optionally, a first dielectric layer 110 is further formed between the substrate 100 and the floating gate material layer 120, and a second dielectric layer 120 is further formed between the floating gate material layer 120 and the control gate material layer 140.

In this embodiment, the substrate 100 is a silicon substrate, and in other embodiments of the present invention, the material selected for the substrate 100 may be at least one of the following materials: the substrate 100 may be a multilayer structure of these semiconductor materials, or a silicon-on-insulator (SOI), a silicon-on-insulator (SSOI), a silicon-on-insulator-germanium (S-SiGeOI), a silicon-on-insulator-germanium (SiGeOI), a germanium-on-insulator (GeO), or the like, and the present invention is not limited thereto. Optionally, the first dielectric layer 110 is a silicon oxide layer, and the second dielectric layer 130 is an ONO stacked structure (i.e., a stacked structure formed by sequentially stacking silicon oxide, silicon nitride, and silicon oxide).

Specifically, the process of forming the opening 160 includes: first, referring to fig. 2, a substrate 100 is provided, a floating gate material layer 120 and a control gate material layer 140 are sequentially formed on the substrate 100, a hard mask layer 150 is formed on the control gate material layer 140, and the hard mask layer 150 is etched to form a first opening (i.e., opening 160 in fig. 2) exposing the control gate material layer 140; referring to fig. 3, forming a first sidewall 161 on the control gate material layer 140 on both sides of the first opening 160, etching the control gate material layer 140 by using the hard mask layer 150 and the first sidewall 161 as masks, and forming a second opening (i.e., the opening 160 in fig. 3) exposing the floating gate material layer 120; referring to fig. 4, second sidewalls 162 are formed on the floating gate material layer 120 at two sides of the second opening 160, the floating gate material layer 120 is etched by using the hard mask layer 150, the first sidewalls 161 and the second sidewalls 162 as masks, a third opening (i.e., the opening 160 in fig. 4) exposing the substrate 100 is formed, and third sidewalls 163 are formed on the substrate 100 at two sides of the third opening 160, so as to complete the etching of the opening 160. At this time, the width of the first sidewall 161 is half of the difference between the sectional width of the first opening (i.e., the width indicated by CD1 in fig. 2) and the sectional width of the second opening (i.e., the width indicated by CD2 in fig. 3). In other embodiments of the present invention, the width of the first sidewall 161 may be obtained by other methods, which is not limited by the present invention.

In addition, referring to fig. 5, after forming the opening 160 and before forming the oxide layer 180, forming an erase gate 170 in the opening 160, wherein a top of the erase gate 170 is flush with a top of the opening 160. It should be noted that the erase gate 170 is formed in the storage region X2, in other embodiments of the present invention, other process flows may be adopted to form the erase gate 170, which is not limited in the present invention.

Next, referring to fig. 6-10, step S02 is performed to form an oxide layer 181 on the sidewalls of the first sidewalls 161. Specifically, referring to fig. 6, the hard mask layer 150, the control gate material layer 140 and the floating gate material layer 120 in the peripheral region X1 are removed to expose the substrate 100 in the peripheral region X1; referring to fig. 7, a gate material layer 180 is formed on the substrate 100 in the peripheral region X1 and extends to cover the hard mask layer 150 and the erase gate 170 of the storage region X2; referring to fig. 8, the hard mask layer 150 in the storage region X2 and the gate material layer 180 on the hard mask layer 150 are removed to expose the surface of the erase gate 170, the sidewalls of the first sidewalls 161 and a portion of the control gate material layer 140 of the storage region X2; referring to fig. 9 and 10, an oxide layer 181 is formed on the gate material layer 180, wherein the oxide layer 181 extends to cover the surfaces of the control gate material layer 140 and the erase gate 170 in the storage region X1 and the sidewalls of the first sidewalls 161; forming a patterned photoresist layer 182 on the oxide layer 181, and etching the gate material layer 180 by using the patterned photoresist layer 182 as a mask to form a gate 183 in the peripheral region X1; the patterned photoresist layer 182 is then removed. Optionally, the thickness of the oxide layer 181 isA gate oxide layer (not shown) is also formed between the gate 182 and the substrate 100.

Next, referring to fig. 11, step S03 is executed to determine the width of the control gate 141 to be formed to be a set value, and the first sidewall 161 and/or the oxide layer 181 are etched according to the relationship between the width of the first sidewall 161, the thickness of the oxide layer 181 and the set value, so as to adjust the width of the first sidewall 161 and/or the oxide layer 181. Optionally, the set value is the width of the control gate 141 formed in the subsequent process in the design layout.

In this embodiment, a wet etching process is used to etch the first sidewall 161 and/or the oxide layer 181, and the process time of the wet etching process is a set time, and the set time is adjusted according to the relationship between the width of the first sidewall 161, the thickness of the oxide layer 181, and the set value. Specifically, if the width of the first sidewall 161 is greater than or equal to the predetermined value, the predetermined time includes a process time for removing the oxide layer 181 and a process time for adjusting the width of the first sidewall 161 to the predetermined value. If the width of the first sidewall 161 is smaller than the predetermined value and the sum of the width of the first sidewall 161 and the thickness of the oxide layer 181 is greater than the predetermined value, the predetermined time is a process time for etching a portion of the oxide layer 181, so that the sum of the remaining thickness of the oxide layer 181 and the width of the first sidewall 161 is the predetermined value, thereby adjusting the width of the finally formed control gate 141. However, since the thickness of the oxide layer 181 is generally set to beTherefore, the adjustment capability of the width of the control gate 141 by retaining part or all of the oxide layer 181 is limited.

Table 1. the relationship table between the width of the first sidewall and the wet etching process time obtained according to the existing data statistics:

optionally, parameters (including the width of the first sidewall, the thickness of the oxide layer, and the humidity) in the manufacturing process of the semiconductor devices of different batches can be collectedProcess time of the process etching, design width and actual width of the control gate, etc.) and establish a database to provide a data basis for feedback adjustment of the control gate size during subsequent manufacturing of other semiconductor devices. For example, referring to table 1, when the measured width of the first sidewall isAnd then, wet etching is carried out for 6min, so that the width of the first side wall is adjusted to the design width of the control gate in the semiconductor device.

Subsequently, referring to fig. 12, step S04 is performed to etch the control gate material layer 140 by using the first sidewall 161 or the first sidewall 161 and the oxide layer 181 as a mask, so as to form a control gate 141. Optionally, after forming the control gate 141, the method further includes: the floating gate material layer 120 is etched by using the first sidewall 161 or the first sidewall 161 and the oxide layer 181 as masks to form a floating gate 121.

In this embodiment, the manufacturing method of the semiconductor device is used for manufacturing a flash memory device, and in other embodiments of the present invention, the manufacturing method of the semiconductor device may also be used for manufacturing other semiconductor devices having the same or similar structures, which is not limited by the present invention.

In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate, wherein a floating gate material layer and a control gate material layer are sequentially formed on the substrate, openings for exposing the substrate are formed on the floating gate material layer and the control gate material layer, and first side walls are formed on the control gate material layer on two sides of the openings; forming an oxide layer on the side wall of the first side wall; determining the width of a control gate to be formed as a set value, and etching the first side wall and/or the oxide layer according to the relationship between the width of the first side wall, the thickness of the oxide layer and the set value so as to adjust the width of the first side wall and/or the oxide layer; and etching the control gate material layer by using the first side wall or the first side wall and the oxide layer as masks to form a control gate. According to the invention, according to the relation between the width of the first side wall, the thickness of the oxide layer and the width of a control gate to be formed, the first side wall and/or the oxide layer are correspondingly etched to adjust the width of the first side wall and/or the oxide layer used as an etching control gate mask, so that the width of a subsequently formed control gate is controlled, and the performance of a semiconductor device is improved.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.