阅读说明：本技术 用于控制命令输入的电子器件 (Electronic device for controlling command input ) 是由 金敬默 金雄来 崔谨镐 于 2020-10-13 设计创作，主要内容包括：本申请公开一种用于控制命令输入的电子器件。电子器件包括命令发生电路,该命令发生电路被配置为根据内部芯片选择信号与内部命令地址的逻辑电平组合来产生在全部存储体刷新操作期间被使能的刷新命令和驱动控制信号。该电子器件还包括缓冲器控制电路,该缓冲器控制电路被配置为从刷新命令和驱动控制信号产生用于将第一组缓冲器使能的第一缓冲器使能信号和用于将第二组缓冲器使能的第二缓冲器使能信号。(An electronic device for controlling command input is disclosed. The electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal that are enabled during an all bank refresh operation according to a logic level combination of an internal chip select signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate a first buffer enable signal to enable the first set of buffers and a second buffer enable signal to enable the second set of buffers from the refresh command and the drive control signal.)

1. An electronic device, comprising:

a command generation circuit configured to generate a refresh command and a driving control signal according to a logic level combination of an internal chip selection signal and an internal command address, the refresh command and the driving control signal being enabled during an all bank refresh operation; and

a buffer control circuit configured to generate a first buffer enable signal for enabling a first set of buffers and a second buffer enable signal for enabling a second set of buffers from the refresh command and the driving control signal.

2. The electronic device of claim 1, wherein during the all bank refresh operation, the first set of buffers is disabled and the second set of buffers is enabled.

3. The electronic device of claim 1, wherein the internal command addresses comprise a first set of internal command addresses and a second set of internal command addresses, an

Wherein the electronic device further comprises a buffer circuit configured to generate the internal chip select signal and the first and second sets of internal command addresses from a chip select signal, a first set of command addresses, and a second set of command addresses through the first and second sets of buffers enabled by the first and second buffer enable signals.

4. The electronic device of claim 3, wherein the buffer circuit comprises:

a chip select signal buffer circuit configured to generate the internal chip select signal by buffering the chip select signal in synchronization with an internal clock;

a first command buffer circuit comprising the first set of buffers, the first command buffer circuit configured to be enabled by the first buffer enable signal and to generate the first set of internal command addresses from the first set of command addresses; and

a second command buffer circuit comprising the second set of buffers, the second command buffer circuit configured to be enabled by the second buffer enable signal and to generate the second set of internal command addresses from the second set of command addresses.

5. The electronic device of claim 4, wherein the first command buffer circuit comprises:

a first buffer configured to be enabled by the first buffer enable signal and to generate a first input command address by buffering the first set of command addresses;

a first delay circuit configured to generate a first delayed command address by delaying the first input command address; and

a first transfer circuit configured to generate the first set of internal command addresses from the first delayed command address in synchronization with the internal clock.

6. The electronic device of claim 5, wherein the first buffer is set to the first set of buffers.

7. The electronic device of claim 4, wherein the second command buffer circuit comprises:

a second buffer configured to be enabled by the second buffer enable signal and to generate a second input command address by buffering the second set of command addresses;

a second delay circuit configured to generate a second delayed command address by delaying the second input command address; and

a second transmission circuit configured to generate the second set of internal command addresses from the second delayed command addresses in synchronization with the internal clock.

8. The electronic device of claim 7, wherein the second buffer is set to the second set of buffers.

9. The electronic device of claim 1, wherein the command generation circuit comprises:

a command input circuit configured to generate an input command from the internal command address according to the driving control signal;

a command decoder configured to generate the refresh command and an internal command according to a logic level combination of the internal chip select signal and the input command in synchronization with an internal clock; and

a drive control signal generation circuit configured to generate the drive control signal, the drive control signal being enabled for a predetermined period by the refresh command and all bank information signals input via the internal command address.

10. The electronic device of claim 1, wherein the buffer control circuit comprises:

a pre-enable signal generation circuit configured to generate a pre-enable signal that is enabled between a time point when the refresh command is input and a time point when the internal chip select signal is input; and

a buffer enable signal generation circuit configured to generate the first buffer enable signal by inverting and buffering the pre-enable signal, and generate the second buffer enable signal by inverting and buffering the pre-enable signal during a period in which the driving control signal is enabled.

11. An electronic device, comprising:

a command generation circuit configured to generate a refresh command and a driving control signal according to a logic level combination of an internal chip selection signal, a first group of internal command addresses, and a second group of internal command addresses, the refresh command and the driving control signal being enabled during an all bank refresh operation, and configured to generate an internal command by detecting the logic level combination of the internal chip selection signal and the second group of internal command addresses during the all bank refresh operation; and

a buffer control circuit configured to generate a first buffer enable signal for enabling a first set of buffers and a second buffer enable signal for enabling a second set of buffers from the refresh command and the driving control signal.

12. The electronic device of claim 11, wherein the internal command is generated from the internal chip select signals and the second set of internal command addresses input via the second set of buffers.

13. The electronic device of claim 11, wherein during the all bank refresh operation, the first set of buffers is disabled and the second set of buffers is enabled.

14. The electronic device of claim 11, wherein the first set of buffers is enabled to generate the first set of internal command addresses when the first buffer enable signal is enabled, and disabled to prevent generation of the first set of internal command addresses when the first buffer enable signal is disabled, an

The second group of buffers is enabled to generate the second group of internal command addresses when the second buffer enable signal is enabled, and disabled to prevent generation of the second group of internal command addresses when the second buffer enable signal is disabled.

15. The electronic device of claim 11, wherein the command generation circuit comprises:

a command input circuit configured to generate input commands from the first and second sets of internal command addresses according to the driving control signal;

a command decoder configured to generate the refresh command and the internal command according to a logic level combination of the internal chip select signal and the input command in synchronization with an internal clock; and

a drive control signal generation circuit configured to generate the drive control signal, the drive control signal being enabled for a predetermined period by the refresh command and all of the bank information signals input via the first and second groups of internal command addresses.

16. The electronic device of claim 15, wherein the command input circuit prevents input of the first set of internal command addresses when the drive control signal is enabled.

17. The electronic device of claim 15, wherein the command decoder comprises:

a pre-decoder configured to generate a pre-refresh command and a pre-internal command by decoding the input command; and

a synchronization circuit configured to generate the refresh command and the internal command from the pre-refresh command and the pre-internal command when the internal chip selection signal is input in synchronization with the internal clock.

18. The electronic device of claim 17, wherein the synchronization circuit comprises:

a first synchronization circuit configured to generate the refresh command from the pre-refresh command when the internal chip selection signal is input in synchronization with the internal clock; and

a second synchronization circuit configured to generate the internal command from the pre-internal command when the internal chip selection signal is input in synchronization with the internal clock.

19. The electronic device of claim 15, wherein the drive control signal generation circuit comprises:

an all-bank refresh signal generation circuit configured to generate an all-bank refresh signal from the all-bank information signal during a period in which the refresh command is input; and

a latch circuit configured to generate the drive control signal, the drive control signal being enabled by the all bank refresh signal and disabled after a predetermined period.

20. The electronic device of claim 11, wherein the buffer control circuit comprises:

a pre-enable signal generation circuit configured to generate a pre-enable signal that is enabled between a time point when the refresh command is input and a time point when the internal chip select signal is input; and

a buffer enable signal generation circuit configured to generate the first buffer enable signal by inverting and buffering the pre-enable signal, and configured to generate the second buffer enable signal by inverting and buffering the pre-enable signal during a period in which the driving control signal is enabled.

Technical Field

Various embodiments are generally directed to an electronic device for controlling buffer enablement during refresh operations.

Background

In general, a semiconductor device including a DDR SDRAM (double data rate synchronous DRAM) performs a write operation of storing data, a read operation of outputting data, and a refresh operation of sensing and amplifying data of a memory cell according to a command input from an external chipset. The semiconductor device needs to perform an activation operation in order to perform a write operation, a read operation, and a refresh operation. The semiconductor device generates an internal command for performing an activation operation according to a command and an address input through the command address pin, and sorts the sequentially input commands using the chip address selection signal.

Various refresh operation methods have been proposed for high-speed operation of semiconductor devices. Examples of the proposed refresh operation include an all bank refresh operation of refreshing all of a plurality of banks included in a core circuit of a semiconductor device and the same bank refresh operation (same-bank refresh operation) of performing a refresh operation only on some of the plurality of banks included in the core circuit and performing write/read operations on other banks.

Disclosure of Invention

Various embodiments are directed to an electronic device capable of reducing current consumption by disabling a buffer that receives some command addresses during a refresh operation.

In one embodiment, an electronic device may include a command generation circuit configured to generate refresh commands and drive control signals that are enabled during an all bank refresh operation according to a logic level combination of an internal chip select signal and an internal command address. The electronic device may further include a buffer control circuit configured to generate a first buffer enable signal to enable the first set of buffers and a second buffer enable signal to enable the second set of buffers from the refresh command and the drive control signal.

In one embodiment, an electronic device may include a command generation circuit configured to generate a refresh command and a drive control signal according to a logic level combination of an internal chip select signal, a first set of internal command addresses, and a second set of internal command addresses, the refresh command and the drive control signal enabled during an all bank refresh operation, and configured to generate the internal command by detecting the logic level combination of the internal chip select signal and the second set of internal command addresses during the all bank refresh operation. The electronic device may further include a buffer control circuit configured to generate a first buffer enable signal to enable the first set of buffers and a second buffer enable signal to enable the second set of buffers from the refresh command and the drive control signal.

According to the present embodiment, the electronic device can disable the buffer that has received some command addresses during the entire bank refresh operation of the refresh operation, thereby reducing current consumption.

Further, the electronic device may detect a logic level of a command address received via a buffer that receives some command addresses during a refresh operation and perform an internal operation. Accordingly, the internal operation can be efficiently performed.

Drawings

Fig. 1 is a block diagram showing a configuration of an electronic device according to an embodiment.

Fig. 2 is a diagram for describing the operation of the internal clock generation circuit included in the electronic device shown in fig. 1.

Fig. 3 is a table showing logic levels of internal chip select signals and internal command addresses for performing a refresh operation and an internal operation of the electronic device shown in fig. 1.

Fig. 4 is a block diagram showing a configuration of a buffer circuit included in the electronic device shown in fig. 1.

Fig. 5 is a diagram showing a configuration of a chip selection signal buffer circuit included in the buffer circuit shown in fig. 4.

Fig. 6 is a diagram showing a configuration of a first command buffer circuit included in the buffer circuit shown in fig. 4.

Fig. 7 is a circuit diagram showing a configuration of a second buffer included in the first command buffer circuit shown in fig. 6.

Fig. 8, 9 and 10 are diagrams for describing an operation of the second buffer shown in fig. 7.

Fig. 11 is a diagram showing a configuration of a second command buffer circuit included in the buffer circuit shown in fig. 4.

Fig. 12 is a circuit diagram showing a configuration of a third buffer included in the second command buffer circuit shown in fig. 11.

Fig. 13 is a block diagram showing a configuration of a command generation circuit included in the electronic device shown in fig. 1.

Fig. 14 is a circuit diagram showing a configuration of a command input circuit included in the command generating circuit shown in fig. 13.

Fig. 15 is a block diagram showing a configuration of a command decoder included in the command generating circuit shown in fig. 13.

Fig. 16 is a circuit diagram showing a configuration of a synchronization circuit included in the command decoder shown in fig. 15.

Fig. 17 is a circuit diagram showing the configuration of a drive control signal generation circuit included in the command generation circuit shown in fig. 13.

Fig. 18 is a circuit diagram showing a configuration of a buffer control circuit included in the electronic device shown in fig. 1.

Fig. 19 is a diagram illustrating a configuration of an electronic system to which the electronic devices illustrated in fig. 1 to 18 are applied according to an embodiment.

Detailed Description

The term "predetermined" means that when a parameter is used in a process or algorithm, the value of the parameter is predetermined. According to embodiments, the value of the parameter may be set at the beginning of the process or algorithm or at the same time as the process or algorithm is executed.

Terms such as "first" and "second" used to distinguish between various components are not limited by the components. For example, a first component can be referred to as a second component and vice versa.

When one component is referred to as being "coupled" or "connected" to another component, it may mean that the components are directly coupled or connected to each other or are coupled or connected to each other through another component interposed therebetween. On the other hand, when one component is referred to as being "directly coupled" or "directly connected" to another component, this may mean that the components are directly coupled or connected to each other without another component interposed therebetween.

"logic high level" and "logic low level" are used to describe the logic levels of a signal. A signal having a "logic high level" is distinguished from a signal having a "logic low level". For example, when the signal having the first voltage corresponds to a "logic high level", the signal having the second voltage may correspond to a "logic low level". According to an embodiment, the "logic high level" may be set to a voltage higher than the "logic low level". Depending on the embodiment, the logic levels of the signals may be set to different logic levels or opposite logic levels. For example, a signal having a logic high level may be set to have a logic low level according to an embodiment, and a signal having a logic low level may be set to have a logic high level according to an embodiment.

Hereinafter, the present disclosure will be described in more detail by examples. The examples are merely illustrative of the present disclosure, and the scope of the present disclosure is not limited by the examples.

As shown in fig. 1, an electronic device 1 according to an embodiment may include an internal clock generation circuit 110, a buffer circuit 120, a command generation circuit 130, a buffer control circuit 140, and a core circuit 150.

The internal clock generation circuit 110 may receive the clock CLK and generate the internal clock ICLK. The internal clock generation circuit 110 may generate the internal clock ICLK by adjusting the phase of the clock CLK. The internal clock generation circuit 110 may generate the internal clock ICLK by dividing the frequency of the clock CLK. The internal clock generation circuit 110 may generate the internal clock ICLK having a frequency corresponding to 1/2 of the frequency of the clock CLK. The clock CLK may be set as a signal that is periodically switched to control the operation of the electronic device 1 according to the present embodiment. The operation of the internal clock generation circuit 110 to generate the internal clock ICLK by dividing the frequency of the clock CLK will be described in detail with reference to fig. 2 which will be described below.

The buffer circuit 120 may generate the internal chip selection signal ICS and the first to eleventh internal command addresses ICA <1:11> from the chip selection signal CS and the first to eleventh command addresses CA <1:11 >. The buffer circuit 120 may generate the internal chip selection signal ICS by buffering the chip selection signal CS. The buffer circuit 120 may include first and second sets of buffers enabled by first and second buffer enable signals CA _ EN1 and CA _ EN 2. The buffer circuit 120 may generate a first set of internal command addresses ICA <1,3,4,6:11> through a first set of buffers that are enabled. The buffer circuit 120 may generate the second set of internal command addresses ICA <2,5> through the second set of buffers that are enabled. The first and second sets of buffers will be described in detail with reference to fig. 4,6 and 11. According to an embodiment, the first and second groups of internal command addresses ICA <1,3,4,6:11> and ICA <2,5> may be set to a combination of bits among the first to eleventh internal command addresses ICA <1:11 >.

The command generating circuit 130 may generate the refresh command REF and the driving control signal REF _ PD according to a logic level combination of the internal chip selection signal ICS and the first and second sets of internal command addresses ICA <1:11> during the refresh operation. The command generating circuit 130 may generate the first internal command WT and the second internal command RD by detecting a logic level combination of the internal chip select signal ICS and the second set of internal command addresses ICA <2,5> during the refresh operation.

The buffer control circuit 140 may generate a first buffer enable signal CA _ EN1 for enabling the first group of buffers and a second buffer enable signal CA _ EN2 for enabling the second group of buffers from the refresh command REF and the driving control signal REF _ PD.

The core circuit 150 may include first to eighth banks BK1 to BK 8. The core circuit 150 may perform an all bank refresh operation and the same bank refresh operation according to the refresh command REF. The core circuit 150 may refresh the first to eighth banks BK1 to BK8 during the all bank refresh operation according to the refresh command REF. The core circuit 150 may refresh any one of the first bank BK1 through the eighth bank BK8 during the same bank refresh operation according to the refresh command REF. The core circuit 150 may perform a first internal operation according to the first internal command WT. The core circuit 150 may perform the second internal operation according to the second internal command RD. The first internal operation may be set to a write operation of storing data by compensating for a resistance value of an input/output line to/from which data is input/output. The second internal operation may be set to a read operation of outputting data by compensating for a resistance value of an input/output line to/from which data is input/output.

Referring to fig. 2, the operation of the internal clock generation circuit 110 will be described below.

The internal clock generation circuit 110 may generate the internal clock ICLK by dividing the frequency of the clock CLK. One period P2 of the internal clock ICLK may be set to a period twice as long as one period P1 of the clock CLK. The frequency of the internal clock ICLK may be set to a frequency corresponding to 1/2 of the frequency of the clock CLK.

Referring to fig. 3, the logic level combinations of the internal chip selection signal ICS for performing the refresh operation and the first and second internal operations according to the present embodiment and the first to eleventh internal command addresses ICA <1:11> will be described below.

First, the logic level combinations of the internal chip selection signal ICS and the first to eleventh internal command addresses ICA <1:11> for performing the all BANK refresh operation REFRESH ALL BANK during the refresh operation will be described below.

In order to perform the all BANK refresh operation REFRESH ALL BANK during the refresh operation, the internal chip select signal ICS may be set to a logic low level L, the first internal command address ICA <1> may be set to a logic high level H, the second internal command address ICA <2> may be set to a logic high level H, the third internal command address ICA <3> may be set to a logic low level L, the fourth internal command address ICA <4> may be set to a logic low level L, the fifth internal command address ICA <5> may be set to a logic high level H, and the eleventh internal command address ICA <11> may be set to a logic low level L. The sixth to tenth internal command addresses ICA <6:10> may be set to various pieces of information (such as addresses) for setting the operation of the electronic device 1. The eleventh internal command address ICA <11> may be set to the all bank information signal for setting the all bank refresh operation during the refresh operation.

Next, the logic level combinations of the internal chip selection signal ICS and the first to eleventh internal command addresses ICA <1:11> for performing the same BANK refresh operation REFRESH SAME BANK during the refresh operation will be described below.

In order to perform the same BANK refresh operation REFRESH SAME BANK during a refresh operation, the internal chip select signal ICS may be set to a logic low level L, the first internal command address ICA <1> may be set to a logic high level H, the second internal command address ICA <2> may be set to a logic high level H, the third internal command address ICA <3> may be set to a logic low level L, the fourth internal command address ICA <4> may be set to a logic low level L, the fifth internal command address ICA <5> may be set to a logic high level H, and the eleventh internal command address ICA <11> may be set to a logic high level H. The sixth to tenth internal command addresses ICA <6:10> may be set to various pieces of information (such as addresses) for setting the operation of the electronic device 1.

The all-bank information signal input via the eleventh internal command address ICA <11> to perform the all-bank refresh operation during the refresh operation may be set to a logic low level. All of the bank information signals input via the eleventh internal command address ICA <11> to perform the same bank refresh operation during the refresh operation may be set to a logic high level.

Next, the logic level combination of the internal chip selection signal ICS for performing the first internal operation WRITE and the second group internal command address ICA <2,5> during the refresh operation will be described below.

In order to perform the first internal operation WRITE during the refresh operation, the internal chip selection signal ICS may be set to a logic low level L, the second internal command address ICA <2> may be set to a logic low level L, and the fifth internal command address ICA <5> may be set to a logic low level L.

Next, the logic level combination of the internal chip selection signal ICS for performing the first internal operation WRITE during the normal operation and the first and second sets of internal command addresses ICA <1:11> will be described below.

In order to perform the first internal operation WRITE during the normal operation, the internal chip selection signal ICS may be set to a logic low level L, the first internal command address ICA <1> may be set to a logic high level H, the second internal command address ICA <2> may be set to a logic low level L, the third internal command address ICA <3> may be set to a logic high level H, the fourth internal command address ICA <4> may be set to a logic high level H, and the fifth internal command address ICA <5> may be set to a logic low level L. The sixth to eleventh internal command addresses ICA <6:11> may be set to various pieces of information (such as addresses) for setting the write operation of the electronic device 1.

Next, the logic level combination of the internal chip selection signal ICS for performing the second internal operation READ and the second group internal command address ICA <2,5> will be described below.

In order to perform the second internal operation READ during the refresh operation, the internal chip selection signal ICS may be set to a logic low level L, the second internal command address ICA <2> may be set to a logic low level L, and the fifth internal command address ICA <5> may be set to a logic high level H.

Next, the logic level combination of the internal chip selection signal ICS for performing the second internal operation READ during the normal operation and the first and second sets of internal command addresses ICA <1:11> will be described below.

In order to perform the second internal operation READ during the normal operation, the internal chip select signal ICS may be set to a logic low level L, the first internal command address ICA <1> may be set to a logic high level H, the second internal command address ICA <2> may be set to a logic low level L, the third internal command address ICA <3> may be set to a logic high level H, the fourth internal command address ICA <4> may be set to a logic high level H, and the fifth internal command address ICA <5> may be set to a logic high level H. The sixth to eleventh internal command addresses ICA <6:11> may be set to various pieces of information (such as addresses) for setting the read operation of the electronic device 1.

Referring to fig. 4, the buffer circuit 120 according to the present embodiment may include a chip selection signal buffer circuit 120_1 and first to eleventh command buffer circuits 121_1 to 121_ 11.

The chip selection signal buffer circuit 120_1 may generate the internal chip selection signal ICS by buffering the chip selection signal CS in synchronization with a rising edge of the internal clock ICLK.

When the first buffer enable signal CA _ EN1 is enabled, the first command buffer circuit 121_1 may generate the first internal command address ICA <1> by buffering the first command address CA <1> in synchronization with the rising edge of the internal clock ICLK. When the first buffer enable signal CA _ EN1 is disabled, the first command buffer circuit 121_1 may prevent the generation of the first internal command address ICA <1 >.

When the second buffer enable signal CA _ EN2 is enabled, the second command buffer circuit 121_2 may generate the second internal command address ICA <2> by buffering the second command address CA <2> in synchronization with the rising edge of the internal clock ICLK. When the second buffer enable signal CA _ EN2 is disabled, the second command buffer circuit 121_2 may prevent the generation of the second internal command address ICA <2 >.

Since the third and fourth command buffer circuits 121_3 and 121_4 and the sixth to eleventh command buffer circuits 121_6 to 121_11 perform the same operation as the first command buffer circuit 121_1 except that their input and output signals are different from those of the first command buffer circuit 121_1, a detailed description thereof is omitted herein. Since the fifth command buffer circuit 121_5 performs the same operation as the second command buffer circuit 121_2 except that its input and output signals are different from those of the second command buffer circuit 121_2, a detailed description thereof will be omitted herein.

Referring to fig. 5, the chip selection signal buffer circuit 120_1 may include a first buffer 210_1, a first delay circuit 210_2, and a first transfer circuit 210_ 3.

The first buffer 210_1 may generate the input chip selection signal IN _ CS by buffering the chip selection signal CS.

The first delay circuit 210_2 may generate the delayed chip select signal CSD by delaying the input chip select signal IN _ CS.

The first transfer circuit 210_3 may receive the delayed chip selection signal CSD and generate the internal chip selection signal ICS in synchronization with a rising edge of the internal clock ICLK.

Referring to fig. 6, the first command buffer circuit 121_1 may include a second buffer 220_1, a second delay circuit 220_2, and a second transfer circuit 220_ 3.

When the second buffer 220_1 is enabled by the first buffer enable signal CA _ EN1, the second buffer 220_1 may generate the first input command address IN _ CA <1> by buffering the first command address CA <1 >. When the second buffer 220_1 is disabled by the first buffer enable signal CA _ EN1, the second buffer 220_1 may prevent the generation of the first input command address IN _ CA <1 >.

The second delay circuit 220_2 may generate the first delayed command address CAD <1> by delaying the first input command address IN _ CA <1 >.

The second transmission circuit 220_3 may receive the first delayed command address CAD <1> and generate the first internal command address ICA <1> in synchronization with the rising edge of the internal clock ICLK.

Referring to fig. 7, the second buffer 220_1 may be implemented as a PMOS transistor P11 coupled between a power supply voltage VDD and a first node nd11, PMOS transistors P12 and P13 coupled between the power supply voltage VDD and a second node nd12, an NMOS transistor N11 coupled between a first node nd11 and a third node nd13, an NMOS transistor N12 coupled between the second node nd12 and a third node nd13, an NMOS transistor N13 coupled between the third node nd13 and a ground voltage VSS, and an inverter IV 11.

When the first buffer enable signal CA _ EN1 is enabled to a logic high level, the second buffer 220_1 may generate the first input command address IN _ CA <1>, which is driven according to a logic level of the first command address CA <1 >.

When the first buffer enable signal CA _ EN1 is disabled to a logic low level, the second buffer 220_1 may prevent generation of the first input command address IN _ CA <1 >.

Referring to fig. 8, an operation of the second buffer 220_1 when the first buffer enable signal CA _ EN1 is enabled to a logic high level and the first command address CA <1> is input at a logic high level will be described below.

When the first buffer enable signal CA _ EN1 is enabled to a logic high level and the first command address CA <1> is input at the logic high level, the NMOS transistors N11 and N13 of the second buffer 220_1 are turned on to drive the first node nd11 at the level of the ground voltage VSS.

When the first node nd11 is driven at the level of the ground voltage VSS, the PMOS transistor P12 of the second buffer 220_1 may be turned on to drive the second node nd12 at the level of the power supply voltage VDD. When the second node nd12 is driven at the level of the power supply voltage VDD, the second buffer 220_1 generates the first input command address IN _ CA <1> at a logic high level.

Referring to fig. 9, an operation of the second buffer 220_1 when the first buffer enable signal CA _ EN1 is enabled to a logic high level and the first command address CA <1> is input at a logic low level will be described below.

When the first buffer enable signal CA _ EN1 is enabled to a logic high level and the first command address CA <1> is input at a logic low level, the NMOS transistors N12 and N13 of the second buffer 220_1 are turned on to drive the second node nd12 at the level of the ground voltage VSS. When the second node nd12 is driven at the level of the ground voltage VSS, the second buffer 220_1 generates the first input command address IN _ CA <1> at a logic low level.

Referring to fig. 10, an operation of the second buffer 220_1 when the first buffer enable signal CA _ EN1 is disabled to a logic low level will be described below.

When the first buffer enable signal CA _ EN1 is disabled to a logic low level, the PMOS transistor P13 of the second buffer 220_1 is turned on, thereby driving the second node nd12 at the level of the power supply voltage VDD. When the second node nd12 is driven at the level of the power supply voltage VDD, the second buffer 220_1 generates the first input command address IN _ CA <1> at a logic high level.

At this time, when the first buffer enable signal CA _ EN1 is disabled to a logic low level, the second buffer 220_1 may prevent the generation of the first input command address IN _ CA <1> by generating the first input command address IN _ CA <1> clamped to a logic high level regardless of the logic level of the first command address CA <1 >.

Referring to fig. 11, the second command buffer circuit 121_2 may include a third buffer 230_1, a third delay circuit 230_2, and a third transfer circuit 230_ 3.

When the third buffer 230_1 is enabled by the second buffer enable signal CA _ EN2, the third buffer 230_1 may generate the second input command address IN _ CA <2> by buffering the second command address CA <2 >. When the third buffer 230_1 is disabled by the second buffer enable signal CA _ EN2, the third buffer 230_1 may prevent the generation of the second input command address IN _ CA <2 >.

The third delay circuit 230_2 may generate the second delayed command address CAD <2> by delaying the second input command address IN _ CA <2 >.

The third transmission circuit 230_3 may receive the second delayed command address CAD <2> and generate the second internal command address ICA <2> in synchronization with the rising edge of the internal clock ICLK.

Referring to fig. 12, the third buffer 230_1 may be implemented as a PMOS transistor P21 coupled between the power voltage VDD and the fourth node nd21, PMOS transistors P22 and P23 coupled between the power voltage VDD and the fifth node nd22, an NMOS transistor N21 coupled between the fourth node nd21 and the sixth node nd23, an NMOS transistor N22 coupled between the fifth node nd22 and the sixth node nd23, an NMOS transistor N23 coupled between the sixth node nd23 and the ground voltage VSS, and an inverter IV 21.

When the second buffer enable signal CA _ EN2 is enabled to a logic high level, the third buffer 230_1 may generate a second input command address IN _ CA <2>, which is driven according to a logic level of the second command address CA <2 >.

When the second buffer enable signal CA _ EN2 is disabled to a logic low level, the third buffer 230_1 may prevent generation of the second input command address IN _ CA <2 >.

Since the third buffer 230_1 is implemented as the same circuit as the second buffer 220_1 described with reference to fig. 7 to 10 and performs the same operation as the second buffer 220_1 except that its input and output signals are different from those of the second buffer 220_1, a detailed description of its operation will be omitted herein.

Referring to fig. 13, the command generating circuit 130 may include a command input circuit 131, a command decoder 132, and a driving control signal generating circuit 133.

The command input circuit 131 may generate first to eleventh input commands ICAD <1:11> from the first to eleventh internal command addresses ICA <1:11> according to the driving control signal REF _ PD. The command input circuit 131 may block the input of some of the first to eleventh internal command addresses ICA <1:11> according to the driving control signal REF _ PD.

The command decoder 132 may generate the refresh command REF, the first internal command WT, and the second internal command RD by decoding the internal chip select signal ICS and the first to eleventh input commands ICAD <1:11> in synchronization with the internal clock ICLK. The command decoder 132 may generate the refresh command REF, the first internal command WT, and the second internal command RD that are selectively enabled according to the logic level combination of the internal chip selection signal ICS and the first to eleventh input commands ICAD <1:11> in synchronization with the internal clock ICLK.

The logic level combination of the internal chip selection signal ICS for generating the refresh command REF and the first to eleventh input commands ICAD <1:11> may be set to the same logic level combination as the logic level combination of the internal chip selection signal ICS and the first to eleventh internal command addresses ICA <1:11> that are input during the entire bank refresh operation and the same bank refresh operation that have been described with reference to fig. 3. The logic level combination of the internal chip select signals ICS for generating the first internal command WT and the first to eleventh input commands ICAD <1:11> may be set to the same logic level combination as the logic level combination of the internal chip select signals ICS input during the first internal operation described with reference to fig. 3 and the first to eleventh internal command addresses ICA <1:11 >. The logic level combination of the internal chip select signals ICS for generating the second internal command RD and the first to eleventh input commands ICAD <1:11> may be set to the same logic level combination as the logic level combination of the internal chip select signals ICS input during the second internal operation described with reference to fig. 3 and the first to eleventh internal command addresses ICA <1:11 >.

The drive control signal generation circuit 133 may generate a drive control signal REF _ PD that is enabled for a predetermined period during all bank refresh operations of the refresh operation. The drive control signal generation circuit 133 may generate a drive control signal REF _ PD that is enabled for a predetermined period of time by the entire bank information signal and the refresh command REF input through the eleventh internal command address ICA <11 >.

Referring to fig. 14, the command input circuit 131 may include first to eleventh command input circuits 131_1 to 131_ 11.

The first command input circuit 131_1 may generate the first input command ICAD <1> from the first internal command address ICA <1> according to a logic level of the driving control signal REF _ PD. When the driving control signal REF _ PD is input at a logic low level, the first command input circuit 131_1 may generate the first input command ICAD <1> by buffering the first internal command address ICA <1 >. When the driving control signal REF _ PD is input at a logic high level, the first command input circuit 131_1 may block the input of the first internal command address ICA <1 >.

The second command input circuit 131_2 may generate a second input command ICAD <2> from the second internal command address ICA <2> using the power supply voltage VDD. The second command input circuit 131_2 may generate the second input command ICAD <2> by buffering the second internal command address ICA <2 >.

Since the third and fourth command input circuits 131_3 and 131_4 and the sixth to eleventh command input circuits 131_6 to 131_11 are implemented as the same circuit as the first command input circuit 131_1 and perform the same operation as the first command input circuit 131_1 except that their input and output signals are different from those of the first command input circuit 131_1, a detailed description thereof will be omitted herein. Since the fifth command input circuit 131_5 is implemented as the same circuit as the second command input circuit 131_2 and performs the same operation as the second command input circuit 131_2 except that its input and output signals are different from those of the second command input circuit 131_2, a detailed description thereof will be omitted herein.

Referring to fig. 15, the command decoder 132 may include a pre-decoder 132_1 and a synchronization circuit 132_ 2.

The PRE-decoder 132_1 may generate the PRE-refresh command PRE _ REF, the first PRE-internal command PRE _ WT, and the second PRE-internal command PRE _ RD by decoding the first to eleventh input commands ICAD <1:11 >. The PRE-decoder 132_1 may generate a PRE-refresh command PRE _ REF, a first PRE-internal command PRE _ WT, and a second PRE-internal command PRE _ RD that are selectively enabled according to a logic level combination of the first to eleventh input commands ICAD <1:11 >.

The synchronizing circuit 132_2 may generate the refresh command REF, the first internal command WT, and the second internal command RD from the internal chip selection signal ICS, the PRE-refresh command PRE _ REF, the first PRE-internal command PRE _ WT, and the second PRE-internal command PRE _ RD in synchronization with the internal clock ICLK. The synchronizing circuit 132_2 may generate the refresh command REF, the first internal command WT, and the second internal command RD from the PRE-refresh command PRE _ REF, the first PRE-internal command PRE _ WT, and the second PRE-internal command PRE _ RD during a period in which the internal chip selection signal ICS is at a logic low level in synchronization with the internal clock ICLK.

Referring to fig. 16, the synchronization circuit 132_2 may include a first synchronization circuit 132_11, a second synchronization circuit 132_12, and a third synchronization circuit 132_ 13.

When the internal chip selection signal ICS is input at a logic low level, the first synchronization circuit 132_11 may generate the refresh command REF from the PRE-refresh command PRE _ REF in synchronization with a rising edge of the internal clock ICLK. When the internal chip selection signal ICS is input at a logic low level, the first synchronization circuit 132_11 may buffer the PRE-refresh command PRE _ REF in synchronization with a rising edge of the internal clock ICLK and output the buffered signal as the refresh command REF.

When the internal chip select signal ICS is input at a logic low level, the second synchronization circuit 132_12 may generate the first internal command WT from the first PRE-internal command PRE _ WT in synchronization with a rising edge of the internal clock ICLK. When the internal chip selection signal ICS is input at a logic low level, the second synchronization circuit 132_12 may buffer the first PRE-internal command PRE _ WT in synchronization with a rising edge of the internal clock ICLK and output the buffered signal as the first internal command WT.

When the internal chip selection signal ICS is input at a logic low level, the third synchronization circuit 132_13 may generate the second internal command RD from the second PRE-internal command PRE _ RD in synchronization with the rising edge of the internal clock ICLK. When the internal chip selection signal ICS is input at a logic low level, the third synchronization circuit 132_13 may buffer the second PRE-internal command PRE _ RD in synchronization with a rising edge of the internal clock ICLK and output the buffered signal as the second internal command RD.

Referring to fig. 17, the driving control signal generation circuit 133 may include an all bank refresh signal generation circuit 133_1 and a latch circuit 133_ 2.

The ALL-bank refresh signal generation circuit 133_1 may generate an ALL-bank refresh signal REF _ ALL from an ALL-bank information signal input from the eleventh internal command address ICA <11> during a period in which the refresh command REF is input. The ALL-bank refresh signal generation circuit 133_1 may generate an ALL-bank refresh signal REF _ ALL that is enabled when the eleventh internal command address ICA <11> is at a logic low level during a period in which the refresh command REF is input. The ALL-bank refresh signal generation circuit 133_1 may generate an ALL-bank refresh signal REF _ ALL that is disabled when the eleventh internal command address ICA <11> is at a logic high level during a period in which the refresh command REF is input. When the ALL bank refresh operation is performed during the refresh operation, the ALL bank refresh signal REF _ ALL may be enabled. When the same bank refresh operation is performed during a refresh operation, the ALL bank refresh signal REF _ ALL may be disabled.

The latch circuit 133_2 may generate a drive control signal REF _ PD that is enabled by the ALL bank refresh signal REF _ ALL and disabled after a predetermined period. The latch circuit 133_2 may generate a driving control signal REF _ PD that is enabled to a logic high level when the ALL bank refresh signal REF _ ALL is enabled to a logic high level. The latch circuit 133_2 may generate the drive control signal REF _ PD that is disabled to a logic low level after a predetermined period of time has elapsed from a point in time when the drive control signal REF _ PD is enabled to a logic high level.

Referring to fig. 18, the buffer control circuit 140 may include a pre-enable signal generation circuit 141 and a buffer enable signal generation circuit 142.

The PRE-enable signal generation circuit 141 may generate a PRE-enable signal PRE _ CEN that is enabled between a point of time when the refresh command REF is input and a point of time when the internal chip selection signal ICS is input. The PRE-enable signal generation circuit 141 may generate a PRE-enable signal PRE _ CEN that is enabled to a logic high level at a point of time when the refresh command REF is input at a logic high level. The PRE-enable signal generation circuit 141 may generate a PRE-enable signal PRE _ CEN that is disabled to a logic low level at a point in time when the internal chip selection signal ICS is input at a logic high level.

The buffer enable signal generation circuit 142 may generate the first buffer enable signal CA _ EN1 by inverting and buffering the PRE-enable signal PRE _ CEN. The buffer enable signal generation circuit 142 may generate the second buffer enable signal CA _ EN2 by inverting and buffering the PRE-enable signal PRE _ CEN during a period in which the driving control signal REF _ PD is enabled. The buffer enable signal generation circuit 142 may generate the second buffer enable signal CA _ EN2 by inverting and buffering the PRE-enable signal PRE _ CEN during a period in which the driving control signal REF _ PD is enabled to a logic high level.

Referring to fig. 1 to 18, an operation of performing a first internal operation when an all bank refresh operation is performed during a refresh operation of an electronic device for control command input according to the present embodiment will be described below.

The internal clock generation circuit 110 generates the internal clock ICLK by dividing the frequency of the clock CLK.

The buffer circuit 120 generates the internal chip selection signal ICS and the first to eleventh internal command addresses ICA <1:11> from the chip selection signal CS and the first to eleventh command addresses CA <1:11 >. At this time, the internal chip select signal ICS is generated to a logic low level, the first internal command address ICA <1> is generated to a logic high level, the second internal command address ICA <2> is generated to a logic high level, the third internal command address ICA <3> is generated to a logic low level, the fourth internal command address ICA <4> is generated to a logic low level, and the fifth internal command address ICA <5> is generated to a logic high level. The eleventh internal command address ICA <11> is generated to a logic low level.

The command generating circuit 130 generates the refresh command REF enabled to a logic high level in synchronization with the internal clock ICLK according to the logic level combination of the internal chip select signal ICS and the first and second sets of internal command addresses ICA <1:11 >. The command generating circuit 130 generates a driving control signal REF _ PD that is enabled to a logic high level by a logic high refresh command REF and a logic low eleventh internal command address ICA <11 >.

The buffer control circuit 140 generates a first buffer enable signal CA _ EN1 disabled to a logic low level and a second buffer enable signal CA _ EN2 enabled to a logic high level from the refresh command REF and the driving control signal REF _ PD.

The core circuit 150 performs an all bank refresh operation on the first to eighth banks BK1 to BK8 according to the refresh command REF.

The buffer circuit 120 disables the first group of buffers according to the first buffer enable signal CA _ EN1 of logic low. The buffer circuit 120 enables the second group of buffers according to the second buffer enable signal CA _ EN2 of logic high. The buffer circuit 120 generates the second internal command address ICA <2> and the fifth internal command address ICA <5> from the second command address CA <2> and the fifth command address CA <5> through the second group of buffers. That is, the buffer circuit 120 generates the second group internal command address ICA <2,5 >.

The command generating circuit 130 generates the first internal command WT that is enabled to a logic high level according to a logic level combination of the internal chip select signal ICS and the second set of internal command addresses ICA <2,5> in synchronization with the internal clock ICLK.

The core circuit 150 performs a write operation of storing data by compensating a resistance value of an input/output line through which data is input/output according to the first internal command WT.

The electronic device 1 according to the present embodiment can disable the buffer that has received some command addresses during the entire bank refresh operation of the refresh operation, thereby reducing current consumption. Further, the electronic device 1 according to the present embodiment can detect the logic level of a command address received via a buffer that receives some command addresses during a refresh operation, and perform an internal operation. Accordingly, the internal operation can be efficiently performed.

Fig. 19 is a block diagram showing a configuration of an electronic system 1000 according to an embodiment. As shown in fig. 19, the electronic system 1000 may include a host 1100 and a semiconductor system 1200.

The host 1100 and the semiconductor system 1200 may transmit/receive signals to/from each other using an interface protocol. Examples of the interface protocol used between the host 1100 and the semiconductor system 1200 may include MMC (multimedia card), ESDI (enhanced small disk interface), IDE (integrated drive electronics), PCI-E (peripheral component interconnect-express), ATA (advanced technology attachment), SATA (serial ATA), PATA (parallel ATA), SAS (serial attached SCSI), USB (universal serial bus), and the like.

The semiconductor system 1200 may include a controller 1300 and a semiconductor device 1400(K: 1). The controller 1300 may control the semiconductor device 1400(K:1) to perform a refresh operation, a first internal operation, and a second internal operation. Each semiconductor device 1400(K:1) may disable buffers that receive some command addresses during all bank refresh operations of the refresh operation, thereby reducing current consumption. Further, each semiconductor device 1400(K:1) may detect a logic level of a command address received via a buffer that receives some command addresses during a refresh operation, and may perform a first internal operation and a second internal operation. Accordingly, the internal operation can be efficiently performed.

Each semiconductor device 1400(K:1) may be implemented as the electronic device 1 shown in fig. 1. According to an embodiment, the semiconductor device 20 may be implemented as a DRAM (dynamic random access memory), a PRAM (phase change random access memory), a RRAM (resistive random access memory), an MRAM (magnetic random access memory), and an FRAM (ferroelectric random access memory).

While various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are by way of example only. Accordingly, the electronic devices described herein should not be limited based on the described embodiments.