阅读说明：本技术 多控制器通信方法、装置、计算机设备和存储介质 (Multi-controller communication method, multi-controller communication device, computer equipment and storage medium ) 是由 陈江 王超 韩舒 于 2021-10-28 设计创作，主要内容包括：本申请涉及一种多控制器通信方法、装置、计算机设备和存储介质。所述方法包括：主控制器发送同步时钟信号,并开始对时钟的下降沿和上升沿计数；从控制器接收到所述同步时钟信号后开始对时钟的下降沿和上升沿计数；主控制器、从控制器根据预设的规则,在下降沿或者上升沿进行数据的发送或接收。采用本方法能够实现多控制器的通信方法,解决主从控制器通信问题。(The application relates to a multi-controller communication method, a multi-controller communication device, computer equipment and a storage medium. The method comprises the following steps: the main controller sends a synchronous clock signal and starts to count the falling edge and the rising edge of the clock; after receiving the synchronous clock signal from the slave controller, starting to count the falling edge and the rising edge of the clock; and the master controller and the slave controller transmit or receive data at a falling edge or a rising edge according to a preset rule. By adopting the method, the communication method of the multiple controllers can be realized, and the problem of communication between the master controller and the slave controller is solved.)

1. A multi-controller communication method, the multi-controller including 1 master controller and at least 1 slave controller, the method comprising:

the main controller sends a synchronous clock signal and starts to count the falling edge and the rising edge of the clock;

after receiving the synchronous clock signal from the slave controller, starting to count the falling edge and the rising edge of the clock;

and the master controller and the slave controller transmit or receive data at a falling edge or a rising edge according to a preset rule.

2. The multi-controller communication method according to claim 1, wherein the multi-controllers are interconnected by a communication bus.

3. The method as claimed in claim 2, wherein the communication bus comprises a CLK clock line and a DATA line, both in bidirectional communication.

4. The multi-controller communication method of claim 1, wherein the master controller transmitting the synchronized clock signal comprises:

the master controller sends a clock signal and sends a synchronization signal on the falling edge of the clock signal, wherein the synchronization signal comprises a frame header and a master controller identifier.

5. The multi-controller communication method according to claim 3, wherein the master controller and the slave controller perform data transmission or reception on a falling edge or a rising edge according to a preset rule, and the method comprises the following steps:

on the falling edge of the clock signal, the master controller or the slave controller transmits DATA needing synchronization to the DATA DATA line;

on the rising edge of the clock signal, the master or slave receives the DATA to be synchronized from the DATA line.

6. The multi-controller communication method according to claim 5,

on the falling edge of the clock signal, the master controller or the slave controller transmits DATA to be synchronized to the DATA line, including:

the method comprises the following steps that a main controller transmits DATA needing synchronization to a DATA DATA line from a 1 st clock signal falling edge to an Nth clock signal falling edge, wherein N is a positive integer larger than 1;

the first slave controller transmits DATA needing synchronization to a DATA line from the falling edge of the (N + 1) th clock signal line to the falling edge of the (2N) th clock signal line;

the second slave controller transmits DATA needing synchronization to the DATA DATA line from the 2N +1 clock signal line falling edge to the 3N clock signal falling edge;

repeating the steps until all M slave controllers transmit DATA to be synchronized to a DATA DATA line, wherein M is a positive integer greater than or equal to 1;

on the rising edge of the clock signal, the master controller or the slave controller receives the DATA needing synchronization from the DATA DATA line, and the method comprises the following steps:

and from the rising edge of the 1 st clock signal to the rising edge of the MN clock signals, the master controller or the slave controller receives the DATA needing synchronization from the DATA DATA line.

7. The multi-controller communication method according to claim 5, wherein the master controller or the slave controller puts the DATA line into a high impedance state after the DATA transmission is completed.

8. A multi-controller communication apparatus for a multi-controller communication method according to any one of claims 1 to 7, the apparatus comprising: m +1 controllers, backplate, communication bus, wherein: m +1 controllers are inserted on the backboard, different slot positions on the backboard have different identification signals, the controller can identify the currently inserted slot position through the slot position identification signals so as to determine the identification of the controller, and the M +1 controllers are connected through a communication bus.

9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method of any of claims 1 to 7 are implemented when the computer program is executed by the processor.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 7.

Technical Field

The present application relates to the field of communication control technologies, and in particular, to a multi-controller communication method, apparatus, computer device, and storage medium.

Background

A storage device set often includes a plurality of storage controllers, for example, a storage device including four storage controllers, as shown in fig. 1, in which a controller, B controller, C controller, and D controller are included.

The plurality of storage controllers have a master-slave relationship before, and when the plurality of storage controllers work normally, the plurality of storage controllers need to communicate when working cooperatively. For example, between the host controller and the execution units, control commands need to be communicated to the execution units in real time, and status information needs to be fed back to the host controller quickly. The mutual communication between controllers is usually realized by adopting a bus mode, such as 232, 485, CAN, Ethernet, and the like, and the interfaces thereof generally utilize hardware resources of a CPU in the device. Therefore, the CPU needs to spend a large amount of running time to manage, and the implementation process of the whole communication protocol is complicated, so that the real-time performance of the communication data and the utilization rate of the bus bandwidth are difficult to control.

Disclosure of Invention

In view of the above, it is necessary to provide a multi-controller communication method, apparatus, computer device and storage medium.

In one aspect, a multi-controller communication method is provided, the multi-controller including 1 master controller and at least 1 slave controller, the method including:

the main controller sends a synchronous clock signal and starts to count the falling edge and the rising edge of the clock;

after receiving the synchronous clock signal from the slave controller, starting to count the falling edge and the rising edge of the clock;

and the master controller and the slave controller transmit or receive data at a falling edge or a rising edge according to a preset rule.

In one embodiment, the multiple controllers are interconnected by a communication bus.

In one embodiment, the communication bus includes a CLK clock line and a DATA line, both in bidirectional communication.

In one embodiment, the master controller sending the synchronized clock signal comprises:

the master controller sends a clock signal and sends a synchronization signal on the falling edge of the clock signal, wherein the synchronization signal comprises a frame header and a master controller identifier.

In one embodiment, the master controller and the slave controller transmit or receive data at a falling edge or a rising edge according to a preset rule, including:

on the falling edge of the clock signal, the master controller or the slave controller transmits DATA needing synchronization to the DATA DATA line;

on the rising edge of the clock signal, the master or slave receives the DATA to be synchronized from the DATA line.

In one embodiment, the master controller or the slave controller transmits DATA to be synchronized to the DATA line on the falling edge of the clock signal, including:

the method comprises the following steps that a main controller transmits DATA needing synchronization to a DATA DATA line from a 1 st clock signal falling edge to an Nth clock signal falling edge, wherein N is a positive integer larger than 1;

the first slave controller transmits DATA needing synchronization to a DATA line from the falling edge of the (N + 1) th clock signal line to the falling edge of the (2N) th clock signal line;

the second slave controller transmits DATA needing synchronization to the DATA DATA line from the 2N +1 clock signal line falling edge to the 3N clock signal falling edge;

repeating the steps until all M slave controllers transmit DATA to be synchronized to a DATA DATA line, wherein M is a positive integer greater than or equal to 1;

on the rising edge of the clock signal, the master controller or the slave controller receives the DATA needing synchronization from the DATA DATA line, and the method comprises the following steps:

and from the rising edge of the 1 st clock signal to the rising edge of the MN clock signals, the master controller or the slave controller receives the DATA needing synchronization from the DATA DATA line.

In one embodiment, the master or slave puts the DATA line to a high impedance state after the DATA transmission is complete.

In another aspect, there is provided a multi-controller communication apparatus, the apparatus comprising: m +1 controllers, backplate, communication bus, wherein: m +1 controllers are inserted on the backboard, different slot positions on the backboard have different identification signals, the controller can identify the currently inserted slot position through the slot position identification signals so as to determine the identification of the controller, and the M +1 controllers are connected through a communication bus.

In another aspect, a computer device is provided, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor implements the following steps when executing the computer program:

the main controller sends a synchronous clock signal and starts to count the falling edge and the rising edge of the clock;

after receiving the synchronous clock signal from the slave controller, starting to count the falling edge and the rising edge of the clock;

and the master controller and the slave controller transmit or receive data at a falling edge or a rising edge according to a preset rule.

In yet another aspect, a computer-readable storage medium is provided, having stored thereon a computer program which, when executed by a processor, performs the steps of:

the main controller sends a synchronous clock signal and starts to count the falling edge and the rising edge of the clock;

after receiving the synchronous clock signal from the slave controller, starting to count the falling edge and the rising edge of the clock;

and the master controller and the slave controller transmit or receive data at a falling edge or a rising edge according to a preset rule.

According to the multi-controller communication method, the multi-controller communication device, the computer equipment and the storage medium, the main controller sends the synchronous clock signal and starts to count the falling edge and the rising edge of the clock; after receiving the synchronous clock signal from the slave controller, starting to count the falling edge and the rising edge of the clock; the master controller and the slave controllers transmit or receive data at the falling edge or the rising edge according to a preset rule, so that the communication method of the multiple controllers is realized, and the problem of communication between the master controller and the slave controllers is solved.

Drawings

FIG. 1 is a schematic diagram of a memory device;

FIG. 2 is a schematic diagram of a multi-controller communication device in one embodiment;

FIG. 3 is a flow diagram illustrating a multi-controller communication method according to one embodiment;

FIG. 4 is a diagram illustrating an internal structure of a computer device according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In one embodiment, there is provided a multi-controller communication device, the device comprising: m +1 controllers, backplate, communication bus, wherein: m +1 controllers are inserted on the backboard, different slot positions on the backboard have different identification signals, the controller can identify the currently inserted slot position through the slot position identification signals so as to determine the identification of the controller, and the M +1 controllers are connected through a communication bus.

Specifically, as shown in fig. 2, taking 4 controllers of the storage system as an example, the storage controllers are sequentially defined as four ABCD controllers, the four memories are inserted into the same backplane, different slot positions on the backplane have corresponding different identification numbers, and the identification number corresponding to the slot position is used as the ID number of the controller inserted into the slot position; 4 storage controllers correspond to 4 ID numbers; only one of the 4 memory controllers acts as a master controller, and the remaining 3 act as slave controllers.

In one embodiment, as shown in fig. 2, a multi-controller communication method is provided and exemplified in succession to the multi-controller shown in fig. 2, the multi-controller including 1 master controller and 3 slave controllers, the multi-controller communication method including the steps of:

s1, the master controller sends a synchronous clock signal and starts to count the falling edge and the rising edge of the clock;

s2, counting the falling edge and rising edge of the clock after the synchronous clock signal is received from the controller;

and S3, the master controller and the slave controller transmit or receive data at the falling edge or the rising edge according to a preset rule.

In one embodiment, multiple controllers are interconnected by a communication bus.

In one embodiment, the communication bus includes a CLK clock line and a DATA line, both in bidirectional communication.

Specifically, the four ABCD controllers are interconnected via a communication bus on the backplane, the communication bus including two signal lines, namely a Clock Line (CLK) and a DATA line (DATA); the clock line and the data line are both bidirectional signals, and pull-up processing is carried out on the backboard; the CLK signal of the master controller is used as the output signal of the controller, and the CLK signals of the other slave controllers are used as the input signals.

In one embodiment, the master controller transmitting the synchronized clock signal in step S1 includes:

and S11, the master controller sends a clock signal and sends a synchronization signal on the falling edge of the clock signal, wherein the synchronization signal comprises a frame header and a master controller identification.

Specifically, the master control a sends a clock signal, sends a "frame header + master control ID number" on the falling edge of the clock signal, and if the ID numbers of the controller ABCD are set to 0x1, 0x2, 0x3, and 0x4, respectively; the frame header is defined as 0xAABB, and other controllers start counting the clock falling edges and falling edges after receiving the "frame header + master ID number".

In one embodiment, step S3 includes:

s31, at the falling edge of the clock signal, the master controller or the slave controller transmits the DATA to be synchronized to the DATA DATA line;

at the rising edge of the clock signal, the master or slave receives the DATA to be synchronized from the DATA line S32.

In one embodiment, step S31 includes:

s311, the main controller transmits DATA to be synchronized to a DATA DATA line from the 1 st clock signal falling edge to the Nth clock signal falling edge, wherein N is a positive integer greater than 1;

s312, when the falling edge of the (N + 1) th clock signal line reaches the falling edge of the 2N clock signal line, the first slave controller transmits DATA needing synchronization to the DATA DATA line;

s313, the second slave controller transmits the DATA to be synchronized to the DATA DATA line from the 2N +1 th clock signal line falling edge to the 3N clock signal falling edge;

and S314, repeating the steps until all M slave controllers transmit DATA needing to be synchronized to the DATA DATA line, wherein M is a positive integer greater than or equal to 1.

In one embodiment, step S32 includes:

s321, from the rising edge of the 1 st clock signal to the rising edge of the MN clock signals, the master controller or the slave controller receives the DATA to be synchronized from the DATA line.

Specifically, continuing with the above example, where M =3 and N =10, then:

on the first clock falling edge to the tenth clock falling edge; the controller A puts the DATA to be synchronized on the DATA line;

falling edge to twentieth clock falling edge at the eleventh clock; the controller B puts the DATA to be synchronized on the DATA line;

from the twenty-first clock falling edge to the thirty-second clock falling edge; the controller C puts the DATA to be synchronized on the DATA line;

falling edge at thirty-first clock to forty-fourth clock; the controller D puts the DATA to be synchronized on the DATA line;

at the same time, each controller receives the data of controller ABCD on the first to forty-th clock rising edges.

On each falling edge, the controller puts a DATA amount of 1bit on the DATA line. The format of the data transmitted over the communication bus is as follows:

data of frame header + main control ID number +10bit A control data +10bit B control data +10bit C control data +10bit D control data

In one embodiment, the master or slave puts the DATA DATA line to a high impedance state after the DATA transmission is complete.

In the communication method of the multiple controllers, the communication of the master controller and the slave controller is realized through the special ID number identification and the specific data format.

It should be understood that, although the steps in the flowchart of fig. 3 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 3 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 4. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a multi-controller communication method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.

Those skilled in the art will appreciate that the architecture shown in fig. 4 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is provided, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the following steps when executing the computer program:

the main controller sends a synchronous clock signal and starts to count the falling edge and the rising edge of the clock;

after receiving the synchronous clock signal from the slave controller, starting to count the falling edge and the rising edge of the clock;

and the master controller and the slave controller transmit or receive data at a falling edge or a rising edge according to a preset rule.

In one embodiment, the processor, when executing the computer program, further performs the steps of:

the master controller sends a clock signal and sends a synchronization signal on the falling edge of the clock signal, wherein the synchronization signal comprises a frame header and a master controller identifier.

In one embodiment, the processor, when executing the computer program, further performs the steps of:

on the falling edge of the clock signal, the master controller or the slave controller transmits DATA needing synchronization to the DATA DATA line;

on the rising edge of the clock signal, the master or slave receives the DATA to be synchronized from the DATA line.

In one embodiment, the processor, when executing the computer program, further performs the steps of:

the method comprises the following steps that a main controller transmits DATA needing synchronization to a DATA DATA line from a 1 st clock signal falling edge to an Nth clock signal falling edge, wherein N is a positive integer larger than 1;

the first slave controller transmits DATA needing synchronization to a DATA line from the falling edge of the (N + 1) th clock signal line to the falling edge of the (2N) th clock signal line;

the second slave controller transmits DATA needing synchronization to the DATA DATA line from the 2N +1 clock signal line falling edge to the 3N clock signal falling edge;

repeating the steps until all M slave controllers transmit DATA to be synchronized to a DATA DATA line, wherein M is a positive integer greater than or equal to 1;

on the rising edge of the clock signal, the master controller or the slave controller receives the DATA needing synchronization from the DATA DATA line, and the method comprises the following steps:

and from the rising edge of the 1 st clock signal to the rising edge of the MN clock signals, the master controller or the slave controller receives the DATA needing synchronization from the DATA DATA line.

In one embodiment, the processor, when executing the computer program, further performs the steps of:

and after the DATA transmission is completed, the master controller or the slave controller puts the DATA DATA line into a high-impedance state.

In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:

the main controller sends a synchronous clock signal and starts to count the falling edge and the rising edge of the clock;

after receiving the synchronous clock signal from the slave controller, starting to count the falling edge and the rising edge of the clock;

and the master controller and the slave controller transmit or receive data at a falling edge or a rising edge according to a preset rule.

In one embodiment, the computer program when executed by the processor further performs the steps of:

the master controller sends a clock signal and sends a synchronization signal on the falling edge of the clock signal, wherein the synchronization signal comprises a frame header and a master controller identifier.

In one embodiment, the computer program when executed by the processor further performs the steps of:

on the falling edge of the clock signal, the master controller or the slave controller transmits DATA needing synchronization to the DATA DATA line;

on the rising edge of the clock signal, the master or slave receives the DATA to be synchronized from the DATA line.

In one embodiment, the computer program when executed by the processor further performs the steps of:

the method comprises the following steps that a main controller transmits DATA needing synchronization to a DATA DATA line from a 1 st clock signal falling edge to an Nth clock signal falling edge, wherein N is a positive integer larger than 1;

the first slave controller transmits DATA needing synchronization to a DATA line from the falling edge of the (N + 1) th clock signal line to the falling edge of the (2N) th clock signal line;

the second slave controller transmits DATA needing synchronization to the DATA DATA line from the 2N +1 clock signal line falling edge to the 3N clock signal falling edge;

repeating the steps until all M slave controllers transmit DATA to be synchronized to a DATA DATA line, wherein M is a positive integer greater than or equal to 1;

on the rising edge of the clock signal, the master controller or the slave controller receives the DATA needing synchronization from the DATA DATA line, and the method comprises the following steps:

and from the rising edge of the 1 st clock signal to the rising edge of the MN clock signals, the master controller or the slave controller receives the DATA needing synchronization from the DATA DATA line.

In one embodiment, the computer program when executed by the processor further performs the steps of:

and after the DATA transmission is completed, the master controller or the slave controller puts the DATA DATA line into a high-impedance state.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.