阅读说明：本技术 半导体结构、三维存储器及其制备方法 (Semiconductor structure, three-dimensional memory and preparation method thereof ) 是由 杨永刚 于 2021-08-26 设计创作，主要内容包括：本申请提供了一种三维存储器的制备方法,包括：在衬底上形成包括沟道结构的堆叠结构；在堆叠结构远离衬底的一侧形成第一绝缘层；对第一绝缘层进行刻蚀,形成第一凹槽；基于第一凹槽对第一绝缘层进行刻蚀,以将第一凹槽扩大为第二凹槽；基于第二凹槽对第一绝缘层进行刻蚀,以形成沿垂直衬底的方向贯通第一绝缘层的第一接触通孔,其中在靠近所述衬底一侧,所述第一接触通孔的宽度小于所述第二凹槽的宽度；以及对第一接触通孔进行填充,以形成沟道触点。本申请的三维存储器及其制备方法在一定程度上保证了沟道触点与沟道结构和连接触点套刻对准时有足够的工艺窗口,节省了试跑的时间,提高了产品的良率和生产效率。(The application provides a preparation method of a three-dimensional memory, which comprises the following steps: forming a stacked structure including a channel structure on a substrate; forming a first insulating layer on one side of the stacked structure far away from the substrate; etching the first insulating layer to form a first groove; etching the first insulating layer based on the first groove to expand the first groove into a second groove; etching the first insulating layer based on the second groove to form a first contact through hole penetrating through the first insulating layer along a direction vertical to the substrate, wherein the width of the first contact through hole is smaller than that of the second groove on one side close to the substrate; and filling the first contact via to form a trench contact. The three-dimensional memory and the preparation method thereof ensure that enough process windows exist when the alignment of the channel contact, the channel structure and the connecting contact is aligned to a certain extent, save the time of trial run, and improve the yield and the production efficiency of products.)

1. A method for preparing a three-dimensional memory is characterized by comprising the following steps:

forming a stacked structure including a channel structure on a substrate;

forming a first insulating layer on one side of the stacked structure far away from the substrate;

etching the first insulating layer to form a first groove;

etching the first insulating layer based on the first groove to expand the first groove into a second groove;

etching the first insulating layer based on the second groove to form a first contact through hole penetrating through the first insulating layer along a direction vertical to the substrate, wherein the width of the first contact through hole is smaller than that of the second groove on one side close to the substrate; and

filling the first contact via to form a trench contact.

2. The method of claim 1, further comprising:

forming a second insulating layer including a connection contact on a side of the first insulating layer remote from the substrate, the connection contact and the channel contact being in contact with each other.

3. The method of claim 2, wherein the width of the channel contact is greater than the width of the connection contact where the connection contact and the channel contact each other.

4. The method of claim 1, wherein the channel structure comprises a channel plug, and wherein the channel contact and the channel plug are in contact with each other.

5. The method of claim 4, wherein a width of the channel contact is less than a width of the channel plug where the channel contact and the channel plug contact each other.

6. The method of claim 1, wherein etching the first insulating layer based on the first recess is an isotropic etch.

7. The method of claim 6, wherein the isotropic etching comprises at least one of wet etching and gas etching.

8. The method of claim 1, further comprising, prior to forming the first recess:

forming a mask layer with a first opening on one side of the first insulating layer, which is far away from the substrate; and

and etching the first insulating layer based on the first opening to form a first groove.

9. The method of claim 2, wherein the material of the channel contact and the connection contact is a conductive material.

10. A semiconductor structure, comprising:

a substrate;

the stacked structure is positioned on the substrate and comprises dielectric layers and gate layers which are stacked alternately;

a channel structure extending through the stack structure; and

the first insulating layer is positioned on one side, far away from the substrate, of the stacked structure and comprises a channel contact, wherein the width of the top of the channel contact is larger than that of the bottom of the channel contact, the top is the side far away from the substrate, and the bottom is the side close to the substrate.

11. The structure of claim 10, further comprising:

a second insulating layer on a side of the first insulating layer remote from the substrate, including a connection contact, wherein the connection contact and the channel contact are in contact with each other.

12. The method of claim 11, wherein the width of the channel contact is greater than the width of the connection contact where the connection contact and the channel contact each other.

13. The structure of claim 10, wherein the channel structure includes a channel plug, the channel contact and the channel plug being in contact with each other.

14. The method of claim 13, wherein a width of the channel contact is less than a width of the channel plug where the channel contact and the channel plug contact each other.

15. The structure of claim 11, wherein the material of the channel contact and the connection contact is a conductive material.

16. A three-dimensional memory comprising the semiconductor structure of any one of claims 10 to 15.

Technical Field

The present application relates to the field of semiconductor design and manufacturing, and more particularly, to a semiconductor structure, a structure of a three-dimensional memory (3D NAND), and a method for fabricating the same.

Background

Memory is an important device used in modern information technology for storing data information. With the continuous increase of the demands of various electronic devices on integration level and data storage density, it is more and more difficult for a common two-dimensional memory device to meet the demands, and under such a situation, a three-dimensional memory is produced.

The three-dimensional memory generally adopts at least one stacking structure, and the unit cost of a storage unit is reduced while the plurality of stacking structures can realize extremely high data storage density. However, as the number of stacked layers increases, Overlay (OVL) alignment between layers becomes more difficult to control, and particularly at the position of a contact interconnection layer, since a conductive connection needs to be formed through an interconnection process, once alignment deviation occurs, the problem of unstable electrical connection, which affects the stability of device operation, and even opens is easily caused. Therefore, a stable interconnection process is realized, and the problem of improving the stability of the memory is rapidly solved.

Disclosure of Invention

The present application provides a semiconductor structure, a three-dimensional memory and a method of fabricating the same that can at least partially solve the above-mentioned problems in the prior art.

According to an aspect of the present application, there is provided a method of manufacturing a three-dimensional memory, which may include: forming a stacked structure including a channel structure on a substrate; forming a first insulating layer on one side of the stacked structure far away from the substrate; etching the first insulating layer to form a first groove; etching the first insulating layer based on the first groove to expand the first groove into a second groove; etching the first insulating layer based on the second groove to form a first contact through hole penetrating through the first insulating layer along a direction vertical to the substrate, wherein the width of the first contact through hole is smaller than that of the second groove on one side close to the substrate; and filling the first contact through hole to form a channel contact.

In one embodiment of the present application, the method may further include: forming a second insulating layer including a connection contact on a side of the first insulating layer remote from the substrate, the connection contact and the channel contact being in contact with each other.

In one embodiment of the present application, the width of the channel contact may be greater than the width of the connection contact where the connection contact and the channel contact each other.

In one embodiment of the present application, the channel structure may include a channel plug, and the channel contact and the channel plug contact each other.

In one embodiment of the present application, a width of the channel contact may be smaller than a width of the channel plug where the channel contact and the channel plug contact each other.

In one embodiment of the present application, the etching of the first insulating layer based on the first groove is isotropic etching.

In one embodiment of the present application, the isotropic etching may include at least one of wet etching and gas etching.

In one embodiment of the present application, before forming the first groove, the method may further include: forming a mask layer with a first opening on one side of the first insulating layer, which is far away from the substrate; and etching the first insulating layer based on the first opening to form a first groove.

In one embodiment of the present application, the material of the channel contact and the connection contact may be a conductive material.

Another aspect of the present application provides a semiconductor structure, which may include: a substrate; the stacked structure is positioned on the substrate and comprises dielectric layers and gate layers which are stacked alternately; a channel structure extending through the stack structure; and the first insulating layer is positioned on one side of the stacked structure far away from the substrate and comprises a channel contact, wherein the channel contact is in contact with the channel structure.

In one embodiment of the present application, the structure may further include: the second insulating layer is positioned on one side, far away from the substrate, of the first insulating layer and comprises a connecting contact, wherein the width of the top of the connecting contact is larger than that of the bottom of the connecting contact, the top is one side far away from the substrate, and the bottom is one side close to the substrate.

In one embodiment of the present application, the width of the channel contact may be greater than the width of the connection contact where the connection contact and the channel contact each other.

In one embodiment of the present application, the channel structure may include a channel plug, and the channel contact and the channel plug contact each other.

In one embodiment of the present application, a width of the channel contact may be smaller than a width of the channel plug where the channel contact and the channel plug contact each other.

In one embodiment of the present application, the material of the channel contact and the connection contact may be a conductive material.

In yet another aspect, a three-dimensional memory is provided that can include any of the semiconductor structures described above.

According to the semiconductor structure, the three-dimensional memory and the preparation method thereof, in the process of forming the first contact through hole, the isotropic etching process is added, so that the finally formed channel contact is in a shape with small width at the bottom and large width at the top, and a sufficient process window is ensured to be formed when the channel contact is aligned with the channel structure and the connecting contact in alignment to a certain extent. The width of the bottom of the channel contact is small, so that the channel contact is in contact with a channel structure; the width of the top of the channel contact is large, so that the channel contact is favorably contacted with the connecting contact, the alignment difficulty of the channel contact, the channel structure and the connecting contact is reduced to a certain extent, the time of pilot run (pi-run) is saved, and the yield and the production efficiency of products are improved.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:

fig. 1 is a flowchart of a method for manufacturing a three-dimensional memory 1000 according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a three-dimensional memory according to an embodiment of the present disclosure after forming a channel structure;

FIG. 3 is a cross-sectional view of a semiconductor structure after forming a first recess according to one embodiment of the present application;

FIG. 4 is a cross-sectional view of a semiconductor structure after forming a second recess according to one embodiment of the present application;

FIG. 5A is a cross-sectional view of a semiconductor structure after forming a first contact via according to one embodiment of the present application;

FIG. 5B is a cross-sectional view of the semiconductor structure after forming a channel contact in accordance with one embodiment of the present application; and

figure 6 is a cross-sectional schematic view of a semiconductor structure after forming a connection contact according to one embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

In the drawings, the size, dimension, and shape of elements have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art. In addition, in the present application, the order in which the processes of the respective steps are described does not necessarily indicate an order in which the processes occur in actual operation, unless explicitly defined otherwise or can be inferred from the context.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 is a flowchart of a method for manufacturing a three-dimensional memory 1000 according to an embodiment of the present disclosure. As shown in fig. 1, the present application provides a method 1000 for manufacturing a three-dimensional memory, comprising:

step S110: forming a stacked structure including a channel structure on a substrate;

step S120: forming a first insulating layer on one side of the stacked structure far away from the substrate;

step S130: etching the first insulating layer to form a first groove;

step S140: etching the first insulating layer based on the first groove to expand the first groove into a second groove;

step S150: etching the first insulating layer based on the second groove to form a first contact through hole penetrating through the first insulating layer along a direction vertical to the substrate, wherein the width of the first contact through hole is smaller than that of the second groove on one side close to the substrate; and

step S160: the first contact via is filled to form a trench contact.

The specific processes of the steps of the above-described manufacturing method 1000 will be described in detail with reference to fig. 2 to 6.

Fig. 2 is a schematic diagram of a three-dimensional memory according to an embodiment of the present disclosure after a channel structure is formed. As shown in fig. 2, a stacked structure 120 is formed on a substrate 110, wherein the stacked structure 120 includes dielectric layers 121 and sacrificial layers 122 that are alternately stacked. The substrate 110 may be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like. The material of the substrate 110 may also be a compound semiconductor. For example, the substrate 110 may be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a silicon carbide (SiC) substrate, or the like. It is noted that the substrate 110 of the present application may also be fabricated using at least one of other semiconductor materials known in the art.

The stacked structure 120 may include a plurality of dielectric layers 121 and sacrificial layers 122 alternately stacked in a direction perpendicular to the substrate 110. The method for forming the stacked structure 120 may include a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof, which is not limited in this application. In the stacked structure 120, the thicknesses of the plurality of sacrificial layers 122 may be the same or different, the thicknesses of the plurality of dielectric layers 121 may be the same or different, and the thicknesses of the dielectric layers 121 and the sacrificial layers 122 may be set according to specific process requirements. Sacrificial layer 122 may be removed and replaced with a conductive material during subsequent processing to form a gate layer, i.e., a word line. Alternatively, the material of the dielectric layer 121 may include silicon oxide, and the material of the sacrificial layer 122 may include silicon nitride. The greater the number of layers of the dielectric layer 121 and the sacrificial layer 122 in the stacked structure 120, the higher the integration.

The stacked structure 120 is etched to form a channel hole 130 (not shown) penetrating the stacked structure 120 and extending to the substrate 110, and a functional layer and a channel layer are sequentially formed on an inner wall of the channel hole 130, and an insulating material is filled in the channel hole 130 to form a channel structure 140. The trench hole 130 may be formed in the stack structure 120 using, for example, a dry or wet etching process. The trench hole 130 may extend vertically in a direction of the substrate 110, thereby exposing a portion of the substrate 110. The functional layer 141 and the channel layer 142 may be sequentially formed on sidewalls of the channel hole using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Among them, the charge blocking layer, the charge trapping layer, and the tunneling layer may be referred to as a functional layer 141. The charge blocking layer is used for blocking the outflow of stored charges of the charge trapping layer, and the charge trapping layer can penetrate through the tunneling layer through the tunneling effect under the action of voltage so as to realize the writing and the erasing of memory data. For example, the material of the charge blocking layer may be silicon oxide, the material of the charge trapping layer may be nitride, and the material of the tunneling layer may be oxide. In some embodiments, the channel structure may further include a channel plug 144, wherein the channel plug 144 is located on top of the channel structure, forming an electrical connection with the channel layer 142.

FIG. 3 is a cross-sectional view of a semiconductor structure after forming a first recess according to an embodiment of the present application. In some embodiments, after forming the channel structure 140, a gate line slit (not shown) may be formed in the stacked structure 120 by, for example, a dry or wet etching process, and then the sacrificial layer 122 may be replaced with the gate layer 123 through the gate line slit. As shown in fig. 3, a first insulating layer 150 may be formed on a side of the stacked structure away from the substrate by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and a mask layer (not shown) having a first opening is formed on a side of the first insulating layer 150 away from the substrate; and etching the first insulating layer 150 in a direction perpendicular to the substrate 110 based on the first opening to form a first groove 151. The first insulating layer may be etched by dry etching to form a first groove 151, and a depth of the first groove 151 is smaller than a thickness of the first insulating layer 150. The first insulating layer may include one or a combination of a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer, and a zirconium oxide layer.

FIG. 4 is a cross-sectional view of a semiconductor structure after forming a second recess according to an embodiment of the present application. As shown in fig. 4, the first insulating layer 150 is isotropically etched based on the first groove 151 to expand the first groove 151 into the second groove 152. Wherein the isotropic etching may include at least one of wet etching and gas etching, and the second groove 152 may be formed to a desired depth and width by controlling an etching rate according to the requirements of the semiconductor structure.

Fig. 5A is a cross-sectional view of a semiconductor structure after forming a first contact via according to an embodiment of the present application. As shown in fig. 5A, the etching of the first insulating layer is continued on the basis of the second groove 152 to form a first contact via 153 penetrating the first insulating layer 150 in a direction perpendicular to the substrate. Wherein the first contact via 153 is located above the channel structure 140, and the width of the first contact via 153 is smaller than the width of the second groove 152 at a side close to the substrate 110. Figure 5B is a cross-sectional view of the semiconductor structure after forming a channel contact according to one embodiment of the present application. As shown in fig. 5B, the first contact via (C1CH)153 is filled with a conductive material, which may include metal tungsten and copper, to form a channel contact 154. Since the trench contact 154 is aligned with the trench plug 144 in the related art, the width of the bottom (the side close to the substrate) of the trench contact 154 is relatively small. The channel contact 154 of the present application has a bottom width (the side closer to the substrate) that is less than the width of the top (the side further from the substrate). The small width at the bottom of the channel contact 154 facilitates alignment between the channel contact 154 and the channel plug 144 where the channel contact 154 and the channel plug 144 contact each other, enabling electrical connection of the channel contact 154 to the channel plug 144, wherein the bottom width of the channel contact 154 is less than the top width of the channel plug 144.

Figure 6 is a cross-sectional schematic view of a semiconductor structure after forming a connection contact according to one embodiment of the present application. As shown in fig. 6, a second insulating layer 160 may be formed on a side of the first insulating layer 150 away from the substrate by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, wherein the material of the second insulating layer 160 may be the same as or different from that of the first insulating layer 150, and the thickness of the second insulating layer 160 may be the same as or different from that of the first insulating layer 150. A via etch is performed on the second insulating layer over the second recess 152 and the via is filled, forming a connection contact 161 that contacts the channel contact 154. The channel contact 154 of the present application has a bottom width (the side closer to the substrate) that is less than the width of the top (the side further from the substrate). The large width at the top of the channel contact 154 facilitates alignment between the channel contact 154 and the connection contact 161 where the channel contact 154 and the connection contact 161 contact each other, allowing for electrical connection of the channel contact 154 to the connection contact 161, wherein the width at the bottom of the connection contact 161 is less than the width at the top of the channel contact 154.

In some embodiments, a metal layer is further included on the side of the second insulating layer 160 away from the substrate, and the metal layer may be electrically connected to the connection contact 161.

In the implementation mode, the channel contact with the small width at the bottom and the large width at the top is formed by adding the isotropic etching process, so that a sufficient process window is ensured to a certain extent when the channel contact is aligned with the channel structure and the connecting contact in the alignment process. The width of the bottom of the channel contact is small, so that the channel contact is in contact with a channel structure; the width of the top of the channel contact is large, which is beneficial to the contact between the channel contact and the connecting contact. Although the isotropic etching process is added, the alignment difficulty of the channel contact, the channel structure and the connecting contact is reduced to a certain extent, the time of pilot run (pi-run) is saved, and the yield and the production efficiency of products are improved.

In another aspect of the present application, a semiconductor structure is provided, which may include: a substrate; the stacked structure is positioned on the substrate and comprises dielectric layers and gate layers which are stacked alternately; a channel structure penetrating the stacked structure; and a first insulating layer located on a side of the stacked structure remote from the substrate and including a channel contact, wherein the channel contact is in contact with the channel structure.

In one embodiment of the present application, the semiconductor structure may further include a second insulating layer on a side of the first insulating layer remote from the substrate, including a connection contact, wherein the connection contact and the channel contact are in contact with each other. Where the connection contact and the channel contact each other, the width of the channel contact is greater than the width of the connection contact.

In one embodiment of the present application, the channel structure includes a channel plug, and the channel contact and the channel plug are in contact with each other. Where the channel contact and the channel plug contact each other, the width of the channel contact is smaller than the width of the channel plug.

In one embodiment of the present application, the material of the channel contact and the connection contact is a conductive material, such as metal tungsten and copper.

The application also provides a three-dimensional memory, and the three-dimensional memory can comprise any one of the semiconductor structures.

Since the contents and structures referred to in the above description of the method 1000 may be fully or partially applicable to the three-dimensional memory described herein, the contents related or similar thereto will not be described in detail.

The objects, technical solutions and advantageous effects of the present invention are further described in detail with reference to the above-described embodiments. It should be understood that the above description is only a specific embodiment of the present invention, and is not intended to limit the present invention. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.