阅读说明：本技术 一种高边电平移位和驱动电路 (High-side level shift and drive circuit ) 是由 杨丰 苟超 李鹏 梁盛铭 刘文韬 王菡 廖鹏飞 蒲林 霍改青 刘婷 曾欣 王强 于 2021-08-25 设计创作，主要内容包括：本发明属于集成电路领域,特别涉及一种高边电平移位和驱动电路；包括逻辑电路、低电平产生电路和高电平产生电路；本发明在逻辑电路产生驱动电压为高电平时,控制高电平产生电路不工作,让低电平产生电路产生低电平电压；在逻辑电路产生的驱动电压为低电平时,控制低电平产生电路不工作,让高电平产生电路产生高电平电压。本发明电路结构简单,设计复杂度低；本发明高边驱动信号的低电平电压可根据低电平产生电路中第二支路中的电流源及其PMOS管的宽长比进行任意调节,能够输出任意连续的低电平电压值；本发明不需使用三极管,能够减小电路驱动能力对工艺中三极管的要求,避免了工艺制造中三极管的性能差异对电路的驱动能力的影响。(The invention belongs to the field of integrated circuits, and particularly relates to a high-side level shift and drive circuit; the circuit comprises a logic circuit, a low level generating circuit and a high level generating circuit; when the logic circuit generates the driving voltage which is high level, the high level generating circuit is controlled not to work, and the low level generating circuit generates the low level voltage; when the driving voltage generated by the logic circuit is at a low level, the low level generating circuit is controlled not to work, and the high level generating circuit is enabled to generate a high level voltage. The circuit of the invention has simple structure and low design complexity; the low level voltage of the high-side driving signal can be adjusted at will according to the width-to-length ratio of the current source in the second branch circuit and the PMOS tube thereof in the low level generating circuit, and any continuous low level voltage value can be output; the invention does not need to use a triode, can reduce the requirement of the driving capability of the circuit on the triode in the process, and avoids the influence of the performance difference of the triode in the process manufacturing on the driving capability of the circuit.)

1. A high side level shift and drive circuit comprises a logic circuit, a low level generation circuit and a high level generation circuit; it is characterized in that the preparation method is characterized in that,

the input end of the logic circuit is connected with a DRIVER signal and a feedback signal of the low level generating circuit; the output end of the logic circuit is connected with the NMOS tube of the first branch of the low level generating circuit, the NMOS tube of the second branch, the grid electrode of the first power NMOS tube and the grid electrode of the NMOS tube of the high level generating circuit, and the power supply of the logic circuit is V_CCAnd the ground is GND;

the low level generating circuit comprises a first branch circuit, a second branch circuit, a first power NMOS tube, a second power NMOS tube and a feedback NMOS tube; each branch circuit comprises a current source, an NMOS (N-channel metal oxide semiconductor) tube, a resistor and a PMOS (P-channel metal oxide semiconductor) tube group; in each branch, one end of the current source is connected with GND, the other end of the current source is connected with the source electrode of an NMOS (N-channel metal oxide semiconductor) tube, the drain electrode of the NMOS tube is connected with one end of a resistor, the other end of the resistor is connected with the drain electrodes of the PMOS tube groups, and the source electrode of the PMOS tube group is connected with V_IN(ii) a The other end of the resistor of the first branch is also connected with a grid electrode of a feedback NMOS tube, a drain electrode of the feedback NMOS tube is connected with the input end of the logic circuit, and a source electrode of the feedback NMOS tube is connected with a source electrode of a second power NMOS tube; one end of the resistor of the second branch circuit is also connected with a feedback NMOS tube, a source electrode of the second power NMOS tube and a drain electrode of the first power NMOS tube, and outputs a DRIVER _ H signal to the high-level generating circuit; the source electrode of the first power NMOS tube is connected with GND; the other end of the resistor of the second branch is also connected with a second power NMOS tubeThe drain of the second power NMOS tube is connected with V_IN；

The high level generating circuit comprises a current source, an NMOS tube and two PMOS tubes, wherein one end of the current source is connected with GND, the other end of the current source is connected with the source electrode of the NMOS tube, and the drain electrode of the NMOS tube is connected with the drain electrode and the grid electrode of one PMOS tube and the grid electrode of the other PMOS tube; the source electrode of one PMOS tube and the source electrode of the other PMOS tube are connected with V_INAnd the grid electrode of the other PMOS tube is connected with the drain electrode.

2. The high-side level shift and drive circuit as claimed in claim 1, wherein the PMOS transistor group comprises at least two PMOS transistors connected in series, wherein the drain of each PMOS transistor is connected to the gate of the PMOS transistor; the series connection mode is that the source electrode of the current PMOS tube is connected with the grid electrode and the drain electrode of the next PMOS tube.

3. The high-side level shift and drive circuit as claimed in claim 2, wherein the number of PMOS transistors connected in series in the group of PMOS transistors in the first branch is M, and the number of PMOS transistors connected in series in the group of PMOS transistors in the second branch is N, and M ≠ N.

4. The high-side level shift and drive circuit as claimed in claim 2, wherein the number of PMOS transistors connected in series in the group of PMOS transistors in the first branch is M, and the number of PMOS transistors connected in series in the group of PMOS transistors in the second branch is N, where M is N.

5. The high-side level shift and drive circuit of claim 1, wherein when the DRIVER signal is high,

the grid voltage of an NMOS tube in the high level generating circuit is low level, the NMOS tube and the two PMOS tubes are not conducted, and the high level generating circuit does not work;

the grid voltage of the first power NMOS tube is at a high level, the first power NMOS tube is conducted, and the output of a DRIVER _ H signal at a low level is controlled;

the above-mentionedThe grid voltage of the NMOS tubes of the first branch and the second branch is high level, V_INSwitch on through first branch road and second branch road respectively to GND, first branch road with the NMOS pipe of second branch road switches on to control feedback NMOS pipe switches on when controlling second power NMOS pipe and switch on, make first power NMOS pipe turn-off, the control outputs the DRIVER _ H signal of low level.

6. The high-side level shift and drive circuit as claimed in claim 5, wherein the first power NMOS transistor and the second power NMOS transistor are both high power NMOS transistors, and the feedback NMOS transistor is a low power NMOS transistor.

7. The high-side level shift and drive circuit as claimed in claim 5, wherein the magnitude of the low level of DRIVER _ H is adjusted by the width-to-length ratio of the current source in the second branch and its PMOS transistor group.

8. The high-side level shift and drive circuit as claimed in claim 5 or 7, wherein the gate voltage output by the first branch to the feedback NMOS transistor does not exceed the sum of the threshold voltage of the feedback NMOS transistor and the voltage value of the low-level DRIVER _ H signal.

9. The high-side level shift and drive circuit of claim 1, wherein when the DRIVER signal is low,

grid voltages of a first branch circuit, an NMOS (N-channel metal oxide semiconductor) tube of a second branch circuit and a first power NMOS tube in the low level generation circuit are low levels, and all devices in the low level generation circuit are not conducted;

the grid voltage of an NMOS tube in the high-level generating circuit is high level, V_INAnd the other PMOS tube, the NMOS tube and the current source in the high-level generating circuit are conducted, one PMOS tube is conducted through a current mirror image, and the DRIVER _ H signal of high level is controlled to be output.

Technical Field

The invention belongs to the field of integrated circuits, and particularly relates to a high-side level shift and drive circuit applied to a high-voltage monolithic DC/DC converter chip.

Background

With the development of electronic system design towards integration direction, the switching converter chip has been widely applied in the fields of communication, electronic computers, consumer electronics, and the like. The monolithic DC/DC converter chip has the characteristics of high integration level, high cost performance, simplest peripheral circuit, capability of forming a high-efficiency power supply and the like, so that the monolithic DC/DC converter chip is widely applied.

A common output stage structure of a high-voltage monolithic DC/DC converter chip is shown in fig. 1, a PMOS transistor M2 and an NMOS transistor M1 are integrated inside the high-voltage DC/DC converter chip, the chip generates a DRIVER signal through an error amplifier and a PWM controller, the high level of the DRIVER signal is generally a low voltage (3.3V-5V), the low level is GND (0V), the DRIVER signal generates a DRIVER _ H signal to control the switching of M2 through a level shift and drive circuit, the DRIVER _ L signal generates a switching of M1, and the DRIVER _ H and the DRIVER _ L are a pair of complementary signals. General V_INVoltage greater than 12V, V in higher voltage applications_INThe voltage is more than 100V, when DRIVER _ H is low level, the M2 tube is opened (when DRIVER _ L is low level, M1 tube is closed), and V is not considered to the conduction voltage drop of M2 tube_OUTVoltage, etcV_IN(ii) a When DRIVER _ L is at high level, M1 tube is on (when DRIVER _ H is at high level, M2 tube is off), and V does not consider the conduction voltage drop of M1 tube_OUTVoltage, etc. GND.

The upper tube M2 of the high-voltage monolithic DC/DC converter chip output stage of FIG. 1 adopts a PMOS tube, and compared with a structure that the upper tube adopts an NMOS tube and needs a charge pump for driving, the output stage of FIG. 1 has a simple structure. However, since the gate-source withstand voltage of M2 is generally lower than the source-drain withstand voltage in an integrated circuit chip, the low level voltage enabling DRIVER _ H as described above is not GND but a relative V_INThe lower voltage turns M2 on. While low level voltage needs to be guaranteed V_INThe difference between the low level of the DRIVER _ H and the low level of the DRIVER _ H does not exceed the grid source withstand voltage of the M2 tube, but the grid source withstand voltage of the M2 is usually between 5V and 30V, so the low level voltage of the DRIVER _ H needs to be more than V according to different processes_INThe lower voltage is 5V to 30V.

Fig. 2 is a prior art high side level shift and drive circuit, the DRIVER signal passes through the circuit to generate the DRIVER _ H signal, and fig. 3 is a key control signal waveform of the prior art high side level shift and drive circuit. When DRIVER is high, V_{G_M3}The NMOS transistor M3, the PMOS transistor M4 and the PMOS transistor M5 are not conducted when the voltage is low, and the high-voltage generating circuit does not work; v_{G_M1}At high level, the NMOS transistor M1 is turned on, V_INThe transistor is connected to GND through a voltage regulator tube Z1, a resistor R1, an NMOS tube M1 and a current source I _ ref1, and the base voltage of a triode Q1 is V_IN-V_Z1(ii) a Then V_{G_M2}When the voltage is high level, the NMOS transistor M2 is turned on, and M2 is a power transistor with a large area and can provide a large current V_INThe transistor Q2 is connected with the NMOS transistor M2, and the voltage of DRIVER _ H is V_IN-V_Z1-V_BE,Q2Q2 is a large area transistor that provides a large drive current; when Q2 is turned on, Q1 is turned on, Q1 is a small triode, and Q1 signal is fed back to the logic circuit module to make V_{G_M2}At low level, M2 is turned off, no current is consumed due to the gate of the MOS transistor at the later stage driven by DRIVER _ H signal, and DRIVER _ H is maintained at V_IN-V_Z1-V_BE,Q2Left and right, this voltage is a low level voltage of DRIVER _ H. When DRIVER is at low level, V_{G_M1}And V_{G_M2}All devices in the low level generating circuit are not conducted when the voltage is low; at this time V_{G_M3}At a high level, V_INM4 is conducted through conduction of M5, M3 and I _ ref2 and conduction of M4 through current mirror image, current is not consumed due to the grid electrode of the later stage MOS tube driven by the DRIVER _ H signal, and the DRIVER _ H maintains V_INLeft and right, this level is a high level voltage of DRIVER _ H.

The low level voltage value of DRIVER _ H generated by the structure is relatively fixed and is V_IN-V_Z1-V_BE,Q2In the integrated circuit process V_Z1Generally greater than 5V, V_BE,Q2Is 0.7V, V_IN-V_Z1-V_BE,Q2The value of (A) is more than 5.7V, when the grid source voltage resistance of the rear stage switch tube is low (such as 5V), the signal is applied to the rear stage switch tube, and the rear stage switch tube can be damaged. At the same time, due to V provided in one process_Z1The selectable voltage value is not more than 2, and the structure generates low level voltage and V of DRIVER _ H_INThe difference number is fixed, and the application requirements of different voltages of the later stage cannot be met. And the performance difference of the triode Q2 is large in different processes, so that the driving capability of the circuit is influenced, and the requirement of the structure of the circuit on the performance of the triode in the process is high.

Disclosure of Invention

In order to overcome the defects that the low level voltage generated by the high-side level shift and drive circuit is relatively fixed and the process requirement of using a triode is high, the invention provides a novel high-side level shift and drive circuit which has the characteristics of simple structure, free adjustment of the low level voltage and no use of the triode.

In order to achieve the purpose, the invention provides the following technical scheme:

a high-side level shift and drive circuit comprises a logic circuit, a low level generation circuit and a high level generation circuit.

The input end of the logic circuit is connected with a DRIVER signal and a feedback signal of the low level generating circuit; the output end of the logic circuit is connected with the NMOS tube of the first branch of the low level generating circuit, the NMOS tube of the second branch, the grid of the first power NMOS tube and the output end of the high level generating circuitThe grid of the NMOS tube, and the power supply of the logic circuit is V_CCAnd the ground is GND;

the low level generating circuit comprises a first branch circuit, a second branch circuit, a first power NMOS tube, a second power NMOS tube and a feedback NMOS tube; each branch circuit comprises a current source, an NMOS (N-channel metal oxide semiconductor) tube, a resistor and a PMOS (P-channel metal oxide semiconductor) tube group; in each branch, one end of the current source is connected with GND, the other end of the current source is connected with the source electrode of an NMOS (N-channel metal oxide semiconductor) tube, the drain electrode of the NMOS tube is connected with one end of a resistor, the other end of the resistor is connected with the drain electrodes of the PMOS tube groups, and the source electrode of the PMOS tube group is connected with V_IN(ii) a The other end of the resistor of the first branch is also connected with a grid electrode of a feedback NMOS tube, a drain electrode of the feedback NMOS tube is connected with the input end of the logic circuit, and a source electrode of the feedback NMOS tube is connected with a source electrode of a second power NMOS tube; one end of the resistor of the second branch circuit is also connected with a feedback NMOS tube, a source electrode of the second power NMOS tube and a drain electrode of the first power NMOS tube, and outputs a DRIVER _ H signal to the high-level generating circuit; the source electrode of the first power NMOS tube is connected with GND; the other end of the resistor of the second branch is also connected with a grid electrode of a second power NMOS tube, and a drain electrode of the second power NMOS tube is connected with a voltage V_IN；

The high level generating circuit comprises a current source, an NMOS tube and two PMOS tubes, wherein one end of the current source is connected with GND, the other end of the current source is connected with the source electrode of the NMOS tube, and the drain electrode of the NMOS tube is connected with the drain electrode and the grid electrode of one PMOS tube and the grid electrode of the other PMOS tube; the source electrode of one PMOS tube and the source electrode of the other PMOS tube are connected with V_INAnd the grid electrode of the other PMOS tube is connected with the drain electrode.

The invention has the beneficial effects that:

(1) the circuit has simple structure and low design complexity, and can obtain high and low level voltage only by matching and designing a plurality of NMOS (N-channel metal oxide semiconductor) tubes and PMOS (P-channel metal oxide semiconductor) tubes;

(2) the low level voltage of the high-side driving signal DRIVER can be adjusted at will according to the current source in the second branch circuit and the width-length ratio of the PMOS tube thereof, and any continuous low level voltage value can be output;

(3) the invention does not need to use a triode, reduces the requirement of the driving capability of the circuit on the triode in the process, and avoids the influence of the performance difference of the triode in the process manufacturing on the driving capability of the circuit.

Drawings

In order to make the object, technical scheme and beneficial effect of the invention more clear, the invention provides the following drawings for explanation:

FIG. 1 is a diagram of a conventional high voltage monolithic DC/DC converter chip output stage;

FIG. 2 is a diagram of a conventional high-side level shift and drive circuit;

FIG. 3 illustrates the waveforms of the key control signals of a conventional high-side level shift and drive circuit;

FIG. 4 is a schematic block diagram of a circuit of one embodiment of the present invention;

FIG. 5 is a key control signal waveform of one embodiment of the present invention;

fig. 6 is a schematic block circuit diagram of a preferred embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 4, an embodiment of the present invention provides a high-side level shift and drive circuit, which includes a logic circuit, a low level generation circuit, and a high level generation circuit.

The input end of the logic circuit is connected with a DRIVER signal and a feedback signal output by a drain of a feedback NMOS tube M9 of the low-level generation circuit;

the output end of the logic circuit mainly outputs 3 paths of signals, the 3 paths of signals are controlled by the logic circuit to output the same or different signals, and the 3 paths of signals are respectively output in the following modes:

the output signal 1 is respectively connected with the grid of an NMOS tube M1 of a first branch and the grid of an NMOS tube M2 of a second branch of the low level generating circuit;

the output signal 2 is connected with the grid electrode of a first power NMOS transistor M3;

the output signal 3 is connected to the gate of the NMOS transistor M4 of the high level generation circuit.

The power supply of the logic circuit is V_CCThe ground is GND and is connected with a power supply V_CCAnd ground GND form a loop.

The low level generating circuit comprises a first branch circuit, a second branch circuit, a first power NMOS transistor M3, a second power NMOS transistor M10 and a feedback NMOS transistor M9;

each branch circuit comprises a current source, an NMOS (N-channel metal oxide semiconductor) tube, a resistor and a PMOS (P-channel metal oxide semiconductor) tube group; in each branch, one end of the current source is connected with GND, the other end of the current source is connected with the source electrode of an NMOS (N-channel metal oxide semiconductor) tube, the drain electrode of the NMOS tube is connected with one end of a resistor, the other end of the resistor is connected with the drain electrodes of the PMOS tube groups, and the source electrode of the PMOS tube group is connected with V_IN(ii) a The other end of the resistor R1 of the first branch is also connected with the grid of a feedback NMOS tube M9, the drain of the feedback NMOS tube M9 is connected with the input end of the logic circuit, and the source of the feedback NMOS tube M9 is connected with the source of a second power NMOS tube M10; one end of the resistor R2 of the second branch is also connected with a feedback NMOS tube M9, a source electrode of a second power NMOS tube M10 and a drain electrode of a first power NMOS tube M3, and outputs a DRIVER _ H signal of a high-level generating circuit; the source of the first power NMOS transistor M3 is connected with GND; the other end of the resistor R2 of the second branch is also connected with the grid of a second power NMOS transistor M10, and the drain of the second power NMOS transistor M10 is connected with V_IN；

Wherein, for two branches, the first branch comprises a current source I _ ref1, an NMOS transistor M1, a resistor R1 and a PMOS transistor group (a PMOS transistor M5 and a PMOS transistor M6); the second branch comprises a current source I _ ref2, an NMOS transistor M2, a resistor R2 and a PMOS transistor group (a PMOS transistor M7 and a PMOS transistor M8); the source of the NMOS transistor M1 of the first branch is connected with one end of a current source I _ ref1, the drain of the NMOS transistor M1 is connected with one end of a resistor R1, the other end of the current source I _ ref1 is connected with GND, the other end of the resistor R1 is connected with the drain of a PMOS transistor M6, the gate of the PMOS transistor M6 and the gate of a feedback NMOS transistor M9, and the source of the PMOS transistor M6 is connected with the drain of the PMOS transistor M5 and the drain of the PMOS transistor M5The grid of M5, the source of PMOS transistor M5, the source of PMOS transistor M7 of the second branch and the source of second power NMOS transistor M10 are connected with V_INThe source of the second branch NMOS transistor M2 is connected to one end of a current source I _ ref2, the drain of the NMOS transistor M2 is connected to one end of a resistor R2, the drain of the first power NMOS transistor M3 is connected to the source of a feedback NMOS transistor M9, the source of the second power NMOS transistor M10 and the drain of a PMOS transistor M11 of the high level generating circuit, the other end of the current source I _ ref2 is connected to GND, the other end of the resistor R2 is connected to the drain of the PMOS transistor M8, the gate of the PMOS transistor M8 and the gate of the second power NMOS transistor M10, the source of the PMOS transistor M8 is connected to the drain of the PMOS transistor M7 and the gate of the PMOS transistor M7, and the source of the first power NMOS transistor M3 is connected to GND.

The high level generating circuit comprises a current source I _ ref3, an NMOS tube M4, two PMOS tubes, namely a PMOS tube M11 and a PMOS tube M12, one end of the current source I _ ref3 is connected with GND, the other end of the current source I _ ref3 is connected with the source electrode of the NMOS tube, and the drain electrode of the NMOS tube M4 is connected with the drain electrode and the grid electrode of one PMOS tube M12 and the grid electrode of the other PMOS tube M11; the source electrode of one PMOS transistor M12 and the source electrode of the other PMOS transistor M11 are connected with V_INAnd the gate of the other PMOS transistor M11 is connected to the drain.

The operation principle of an embodiment of the present invention is as follows, as shown in fig. 5, and fig. 5 shows waveforms of key control signals of an embodiment of the present invention.

When the DRIVER signal at the input of the logic circuit is high:

the input signal 3 is a low level voltage, so that the gate voltage V of the NMOS transistor M4 of the high level generation circuit_{G_M4}The NMOS transistor M4, the PMOS transistor M11, and the PMOS transistor M12 in the high level generating circuit are turned off at low level, and the high level generating circuit does not work at this time.

The input signal 1 is a high level voltage, and the gate voltages of the NMOS transistors of the first branch and the second branch are high levels, that is, the gate voltage V of the NMOS transistor M1 in the first branch_{G_M1}And the gate voltage V of the NMOS transistor M2 in the second branch_{G_M2}Is at a high level;

when the NMOS transistor M1 is turned on, V_INThe current is conducted to GND through a PMOS tube M5, a PMOS tube M6, a resistor R1, an NMOS tube M1 and a current source I _ ref1 in the first branch circuit, and the feedback NMOS is connectedGate voltage V of tube M9_{G_M9}Comprises the following steps:

wherein, V_INFor the supply voltage, I _ ref1 is the current of the current source I _ ref1 of the first branch, μ_pIs the mobility of holes, C_OXIs the gate oxide capacitance of unit area of PMOS tube, (W/L)_M5Is the width-to-length ratio, V, of the PMOS transistor M5_T,M5Is the threshold voltage of PMOS tube M5, (W/L)_M6Is the width-to-length ratio, V, of the PMOS transistor M6 device_T,M6Is the threshold voltage of the PMOS transistor M6.

When the NMOS transistor M2 is turned on, V_INThe power is conducted to GND through a PMOS tube M7, a PMOS tube M8, a resistor R2, an NMOS tube M2 and a current source I _ ref2 in a second branch, and the grid voltage V of a second power NMOS tube M10_{G_M10}Comprises the following steps:

wherein, V_INFor the supply voltage, I _ ref2 is the current, μ, of the current source I _ ref2 of the second branch_pIs the mobility of holes, C_OXIs the gate oxide capacitance of unit area of PMOS tube, (W/L)_M7Is the width-to-length ratio, V, of the PMOS transistor M7_T,M7Is the threshold voltage of PMOS tube M7, (W/L)_M8Is the width-to-length ratio, V, of the PMOS transistor M8 device_T,M8Is the threshold voltage of the PMOS transistor M8.

The input signal 2 is a high level voltage, and then the gate voltage V of the first power NMOS transistor is enabled_{G_M3}The high level makes the NMOS transistor M3 conduct, and the NMOS transistor M3 is a large power transistor, which can provide large current, V_INWhen the second power NMOS transistor M10 and the first power NMOS transistor M3 are turned on, the voltage of the low level DRIVER _ H output by the control circuit at this time is:

DRIVER_H＝V_{G_M10}-V_GS,M10 (3)

wherein, V_GS,M10Is the difference of the gate-source voltage of the second power NMOS transistor M10.

The second power NMOS transistor is also a high-power NMOS transistor, and M10 is an NMOS transistor with a large area and can also provide large driving current; when the second power NMOS transistor M10 is turned on, the feedback NMOS transistor M9 is turned on, the feedback NMOS transistor M9 is a small NMOS transistor, and the drain of the feedback NMOS transistor M9 is fed back to the logic circuit module, so that the gate voltage V of the first power NMOS transistor is enabled to be lower than the gate voltage V of the first power NMOS transistor_{G_M3}At low level, M3 is turned off, no current is consumed due to the gate of the MOS transistor at the later stage driven by DRIVER _ H signal, the second power NMOS transistor M10 is kept in weak conduction state, and the difference V between the gate and source voltages is_GS,M10Is equal to V_T,M10，V_T,M10Substituting formula (2) into formula (3) for the threshold voltage of the second power NMOS transistor M10, the voltage of DRIVER _ H is:

at this time, DRIVER _ H is a low level voltage.

In addition, in the embodiment of the invention, a voltage V is generated by the PMOS transistor M5, the PMOS transistor M6, the resistor R1, the NMOS transistor M1 and the current source I _ ref1 in the first branch circuit separately_{G_M9}Voltage, the conduction of the second power NMOS transistor M10 is detected by the feedback NMOS transistor M9, and the proper voltage V can be output by setting the proper first branch_{G_M9}When DRIVER _ H is low, the feedback NMOS transistor M9 is not turned on. For example, assuming that the low level DRIVER _ H is 15V, V corresponds to the source of the feedback NMOS transistor M9_{S_M9}When 15V, the feedback NMOS transistor M9 is turned on under the condition V_{G_M9}-V_{S_M9}＞V_T,M9(ii) a Then to ensure that the feedback NMOS transistor M9 does not conduct, assume V_T,M9When the voltage is 0.7V, the gate voltage V of the feedback NMOS transistor M9 needs to be set_{G_M9}Not more than 15.7V.

When the DRIVER signal at the input of the logic circuit is low:

the input signals 1 and 2 are both low level signals, i.e. the gate voltage V of the NMOS transistor M1 in the first branch_{G_M1}The second branchGrid voltage V of middle NMOS transistor M2_{G_M2}Grid voltage V of first power NMOS tube_{G_M3}Are all low level signals; all devices in the low level generating circuit are not conducted at the moment;

the input signal 3 is a high level signal, and the NMOS transistor V in the high level generating circuit_{G_M4}At a high level, V_INThrough PMOS pipe M12, NMOS pipe M4 and current source I _ ref3 among the high level generating circuit switch on, make PMOS pipe M11 switch on through the current mirror image, because the grid of the later stage MOS pipe of DRIVER _ H signal drive, do not consume the electric current, DRIVER _ H maintains V_INLeft and right, this level is a high level voltage of DRIVER _ H. From equation (4), it can be seen that the low level voltage of DRIVER _ H can be obtained by adjusting the width-to-length ratio (W/L) of the current source I _ ref2 and the PMOS transistor M7_M7And width-to-length ratio (W/L) of PMOS tube M8_M8Compared with the existing structure using the Zener diode, the embodiment of the invention can obtain any continuous low-level voltage value, and the circuit structure is changed from the triode to the NMOS tube, thereby avoiding the influence of the performance difference of the triode in the process manufacturing on the driving capability of the circuit.

The preferred embodiment of the present invention provides another high-side level shift and driving circuit, as shown in fig. 6, which is different from the previous embodiment in that M PMOS transistors are connected in series between a PMOS transistor M5 and a PMOS transistor M6 of a low level generation circuit, N PMOS transistors are connected in series between a PMOS transistor M7 and a PMOS transistor M8, wherein a drain of each PMOS transistor is connected to a gate of the PMOS transistor; the series connection mode is that the source electrode of the current PMOS tube is connected with the grid electrode and the drain electrode of the next PMOS tube; the grid and the drain of the first PMOS tube can be used as the grid terminal and the drain terminal of the whole PMOS tube grouping structure, the source of the last PMOS tube can be used as the source terminal of the whole PMOS tube grouping structure, the grid terminals and the drain terminals of all the PMOS tube grouping structures are commonly connected with the resistors in the corresponding branches, and the source terminal of the PMOS tube grouping structure is correspondingly connected with the V_IN(ii) a And M ≠ N.

In some embodiments, when M is equal to N, the first branch and the second branch belong to an approximately symmetrical structure, so the design size of the PMOS transistor group in the first branch can be made closer to the design size of the PMOS transistor group in the second branch.

In other embodiments, M ≠ N may also be used, and at this time, the first branch and the second branch belong to more arbitrary structures, which can meet more personalized application requirements.

The DRIVER _ H voltage at this time can be expressed as:

wherein, V_INFor the supply voltage, I _ ref2 is the current, μ, of the current source I _ ref2 of the second branch_pIs the mobility of holes, C_OXThe gate oxide capacitance per unit area of the PMOS tube, Mn represents the nth PMOS tube in the second branch circuit; (W/L)_MnIs the width-to-length ratio of Mn in the PMOS tube, V_T,MnThe threshold voltage of the PMOS transistor Mn is shown, and N represents the number of PMOS transistors connected in series in the second branch circuit. This embodiment can make the low level voltage variation range of DRIVER _ H wider through connecting a plurality of PMOS pipes in series to satisfy more applications.

In the description of the present invention, it is to be understood that the terms "coaxial", "bottom", "one end", "top", "middle", "other end", "upper", "one side", "top", "inner", "outer", "front", "center", "both ends", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "disposed," "connected," "fixed," "rotated," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; the terms may be directly connected or indirectly connected through an intermediate, and may be communication between two elements or interaction relationship between two elements, unless otherwise specifically limited, and the specific meaning of the terms in the present invention will be understood by those skilled in the art according to specific situations.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.