阅读说明：本技术 一种带宽降速修复方法、装置及电子设备 (Bandwidth deceleration repairing method and device and electronic equipment ) 是由 孔维宾 吴常顺 周加洋 于 2021-10-08 设计创作，主要内容包括：本发明公开了一种带宽降速修复方法、装置及电子设备,应用于BIOS模块,BIOS模块与包含有寄存器的CPLD模块一侧连接,用于与CPLD模块进行通信,CPLD模块另一侧与配置有目标带宽的PCIE模块连接,用于获取PCIE模块的链路带宽；方法包括：当设备启动时,从CPLD模块中获取PCIE模块的链路带宽；将链路带宽与目标带宽进行比对,确定PCIE模块是否出现带宽降速；当PCIE模块出现带宽降速,向CPLD模块发送寄存器连接状态控制指令,寄存器根据接收到的指令先响应禁用连接操作再响应启用连接操作。(The invention discloses a bandwidth deceleration repairing method, a bandwidth deceleration repairing device and electronic equipment, which are applied to a BIOS module, wherein the BIOS module is connected with one side of a CPLD module containing a register and is used for communicating with the CPLD module, and the other side of the CPLD module is connected with a PCIE module configured with a target bandwidth and is used for acquiring the link bandwidth of the PCIE module; the method comprises the following steps: when the equipment is started, acquiring the link bandwidth of the PCIE module from the CPLD module; comparing the link bandwidth with a target bandwidth, and determining whether the PCIE module has bandwidth deceleration; when the bandwidth of the PCIE module is reduced, a register connection state control instruction is sent to the CPLD module, and the register responds to the connection disabling operation first and then responds to the connection enabling operation according to the received instruction.)

1. The bandwidth deceleration repairing method is characterized by being applied to a BIOS module, wherein the BIOS module is connected with one side of a CPLD module containing a register and is used for communicating with the CPLD module, and the other side of the CPLD module is connected with a PCIE module configured with a target bandwidth and is used for acquiring the link bandwidth of the PCIE module; the method comprises the following steps:

when the equipment is started, acquiring the link bandwidth of the PCIE module from the CPLD module;

comparing the link bandwidth with a target bandwidth to determine whether the PCIE module has bandwidth deceleration;

and when the bandwidth of the PCIE module is reduced, a register connection state control instruction is sent to the CPLD module, so that the register responds to the connection disabling operation and responds to the connection enabling operation according to the received instruction.

2. The method according to claim 1, wherein when the PCIE module experiences bandwidth degradation, sending a register connection state control instruction to the CPLD module includes:

when the bandwidth of the PCIE module is reduced, detecting the bandwidth configuration information of the PCIE module;

and when the PCIE module is configured with a bandwidth configuration display card, executing the operation of sending a register connection state control instruction to the CPLD module.

3. The method according to claim 1, wherein when the PCIE module experiences bandwidth degradation, a register connection state control instruction is sent to the CPLD module, so that the register responds to the connection disabling operation and then responds to the connection enabling operation according to the received instruction, and then the method further comprises:

detecting a bandwidth speed reduction repair result of the PCIE module;

when the PCIE module still generates bandwidth speed reduction, the step of sending a register connection state control instruction to the CPLD module is repeated, so that the register responds to the steps of disabling connection operation and then enabling connection operation according to the received instruction until the target times are reached.

4. The method of claim 1, wherein sending a register connection state control instruction to the CPLD module, such that the register responds to disable connection operations and then responds to enable connection operations according to the received instruction, comprises:

sending a register connection forbidding control instruction to the CPLD module, so that the register responds to connection forbidding operation according to the received instruction;

and responding to the timing operation, and sending a register starting connection control instruction to the CPLD module when the target duration is reached, so that the register responds to starting connection operation according to the received instruction.

5. The method of claim 1, wherein the register-linked-state control instruction comprises: a register disable connection control instruction, a register enable connection control instruction, and a register disable and enable connection operation interval duration instruction;

sending a register connection state control instruction to the CPLD module, so that the register responds to the disable connection operation first and then responds to the enable connection operation according to the received instruction, further comprising:

sending a register connection forbidding control instruction to the CPLD module, so that the register responds to connection forbidding operation according to the received instruction;

and sending the register enabling connection control instruction and the interval duration instruction of the register disabling and enabling connection operation to the CPLD module, so that the register responds to enabling connection delay operation according to the received instruction.

6. The method of claim 3, further comprising:

and sending the repair times of the PCIE module bandwidth speed reduction and the repair result corresponding to each repair operation to a register of the CPLD module for storage.

7. The method according to any one of claims 1-6, further comprising:

and sending the bandwidth speed reduction information of the PCIE module to the CPLD module, so that the CPLD module stores the speed reduction information in a register.

8. The bandwidth deceleration repairing device is used for a BIOS module, wherein the BIOS module is connected with one side of a CPLD module containing a register and is used for communicating with the CPLD module, and the other side of the CPLD module is connected with a PCIE module configured with a target bandwidth and is used for acquiring a link bandwidth of the PCIE module; the device comprises:

the link bandwidth acquisition module is used for acquiring the link bandwidth of the PCIE module from the CPLD module when the equipment is started;

a speed reduction determining module, configured to compare the link bandwidth with a target bandwidth, and determine whether a bandwidth reduction occurs in the PCIE module;

and the instruction sending module is used for sending a register connection state control instruction to the CPLD module when the bandwidth speed reduction occurs in the PCIE module, so that the register responds to the connection disabling operation first and then responds to the connection enabling operation according to the received instruction.

9. An electronic device, comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the steps of the bandwidth throttling repair method according to any of claims 1 to 7.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the bandwidth slowdown restoration method according to any one of claims 1 to 7.

Technical Field

The invention relates to the technical field of equipment bandwidth processing, in particular to a bandwidth deceleration repairing method and device and electronic equipment.

Background

PCIE (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. In the development process of PCIE, the interface version has been developed from PCIE1.0 to PCIE5.0, and the supported bandwidth is also gradually evolved from X1 and X2 to X16 and X32. For a CPU supporting PCIE3.0, a PCIE device in the CPU generally needs to configure a corresponding standard bandwidth, such as a standard bandwidth of configuration X16. However, the PCIE device that finds the bandwidth configuration completed during the device power-on or reboot has a problem of bandwidth reduction, such as bandwidth reduction from X16 to X1.

In the related art, for a PCIE device with a reduced bandwidth speed, the bandwidth reduction repair is generally performed by pulling the CPU to reset twice, but the second reset needs to be performed only after the PCIE device is stabilized for a duration of one second after the first reset is completed, generally, the required stabilization duration between two reset operations is 16 seconds, the consumed time is long, and the device has a certain requirement on the startup duration, so a new bandwidth reduction repair method is urgently needed to be provided to improve the timeliness of the bandwidth reduction repair.

Disclosure of Invention

Therefore, the technical problem to be solved by the present invention is to overcome the defect that the conventional bandwidth speed reduction repair method consumes a long time, so as to provide a bandwidth speed reduction repair method, device and electronic device.

According to a first aspect, the embodiment of the present invention discloses a bandwidth speed reduction repair method, which is applied to a BIOS module, where the BIOS module is connected to one side of a CPLD module including a register, and is configured to communicate with the CPLD module, and the other side of the CPLD module is connected to a PCIE module configured with a target bandwidth, and is configured to obtain a link bandwidth of the PCIE module; the method comprises the following steps: when the equipment is started, acquiring the link bandwidth of the PCIE module from the CPLD module; comparing the link bandwidth with a target bandwidth to determine whether the PCIE module has bandwidth deceleration; and when the bandwidth of the PCIE module is reduced, a register connection state control instruction is sent to the CPLD module, so that the register responds to the connection disabling operation and responds to the connection enabling operation according to the received instruction.

Optionally, when the bandwidth of the PCIE module decreases, sending a register connection state control instruction to the CPLD module includes: when the bandwidth of the PCIE module is reduced, detecting the bandwidth configuration information of the PCIE module; and when the PCIE module is configured with a bandwidth configuration display card, executing the operation of sending a register connection state control instruction to the CPLD module.

Optionally, when the PCIE module experiences bandwidth slowdown, a register connection state control instruction is sent to the CPLD module, so that the register responds to the connection disabling operation first and then responds to the connection enabling operation according to the received instruction, and then the method further includes: detecting a bandwidth speed reduction repair result of the PCIE module; when the PCIE module still generates bandwidth speed reduction, the step of sending a register connection state control instruction to the CPLD module is repeated, so that the register responds to the steps of disabling connection operation and then enabling connection operation according to the received instruction until the target times are reached.

Optionally, sending a register connection state control instruction to the CPLD module, so that the register responds to the disable connection operation first and then responds to the enable connection operation according to the received instruction, including: sending a register connection forbidding control instruction to the CPLD module, so that the register responds to connection forbidding operation according to the received instruction; and responding to the timing operation, and sending a register starting connection control instruction to the CPLD module when the target duration is reached, so that the register responds to starting connection operation according to the received instruction.

Optionally, the register connection state control instruction includes: a register disable connection control instruction, a register enable connection control instruction, and a register disable and enable connection operation interval duration instruction; sending a register connection state control instruction to the CPLD module, so that the register responds to the disable connection operation first and then responds to the enable connection operation according to the received instruction, further comprising: sending a register connection forbidding control instruction to the CPLD module, so that the register responds to connection forbidding operation according to the received instruction; and sending the register enabling connection control instruction and the interval duration instruction of the register disabling and enabling connection operation to the CPLD module, so that the register responds to enabling connection delay operation according to the received instruction.

Optionally, the method further comprises: and sending the repair times of the PCIE module bandwidth speed reduction and the repair result corresponding to each repair operation to a register of the CPLD module for storage.

Optionally, the method further comprises: and sending the bandwidth speed reduction information of the PCIE module to the CPLD module, so that the CPLD module stores the speed reduction information in a register.

According to a second aspect, the embodiment of the present invention further discloses a bandwidth deceleration repairing device, which is used for a BIOS module, where the BIOS module is connected to one side of a CPLD module including a register, and is configured to communicate with the CPLD module, and the other side of the CPLD module is connected to a PCIE module configured with a target bandwidth, and is configured to obtain a link bandwidth of the PCIE module; the device comprises: the link bandwidth acquisition module is used for acquiring the link bandwidth of the PCIE module from the CPLD module when the equipment is started; a speed reduction determining module, configured to compare the link bandwidth with a target bandwidth, and determine whether a bandwidth reduction occurs in the PCIE module; and the instruction sending module is used for sending a register connection state control instruction to the CPLD module when the bandwidth speed reduction occurs in the PCIE module, so that the register responds to the connection disabling operation first and then responds to the connection enabling operation according to the received instruction.

According to a third aspect, an embodiment of the present invention further discloses an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the steps of the bandwidth reduction repair method according to the first aspect or any one of the optional embodiments of the first aspect.

According to a fourth aspect, the embodiments of the present invention also disclose a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the bandwidth reduction repair method according to the first aspect or any one of the optional embodiments of the first aspect.

The technical scheme of the invention has the following advantages:

the invention provides a bandwidth deceleration repairing method/device, which is applied to a BIOS module, wherein the BIOS module is connected with one side of a CPLD module containing a register and is used for communicating with the CPLD module, the other side of the CPLD module is connected with a PCIE module configured with a target bandwidth and is used for acquiring the link bandwidth of the PCIE module, when equipment is started, the link bandwidth of the PCIE module is acquired from the CPLD module, the link bandwidth is compared with the target bandwidth to determine whether the bandwidth deceleration occurs in the PCIE module, and when the bandwidth deceleration occurs in the PCIE module, a register connection state control command is sent to the CPLD module, so that the register responds to the connection disabling operation and then responds to the connection enabling operation according to the received command. When the BIOS module detects that the PCIE module has the bandwidth deceleration condition at the equipment starting stage, a register connection state control instruction is sent to the CPLD module, the control register responds to the forbidden connection operation firstly and then responds to the starting connection operation secondly according to the received instruction, so that the PCIE module link is initialized again and the training operation is carried out again to realize the link bandwidth repair, the register is forbidden and the starting connection only needs millisecond-level time consumption in the whole bandwidth deceleration repair process, the timeliness of the bandwidth deceleration repair is improved, and the requirement on the equipment starting time length is met.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a flowchart of a specific example of a bandwidth slowdown repair method in an embodiment of the present invention;

fig. 2 is a schematic structural diagram corresponding to a specific example of a bandwidth speed reduction repair method in the embodiment of the present invention;

FIG. 3 is a flowchart illustrating a specific example of a bandwidth throttling recovery method according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating a specific example of a bandwidth throttling recovery method according to an embodiment of the present invention;

FIG. 5 is a flowchart illustrating a specific example of a bandwidth throttling recovery method according to an embodiment of the present invention;

FIG. 6 is a schematic block diagram of a specific example of a bandwidth throttling recovery apparatus according to an embodiment of the present invention;

fig. 7 is a diagram of a specific example of an electronic device in an embodiment of the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "first", "second", and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and can, for example, be electrical connections; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

The BIOS (Basic Input Output System) is a set of programs that are fixed on a ROM chip on a main board in a computer, and stores the most important Basic Input Output programs of the computer, a self-test program after power-on, and a System self-start program. The CPLD (Complex Programmable Logic Device) is a digital integrated circuit with high density, high speed and low power consumption, which is formed by using programming technologies such as CMOS EPROM, EEPROM, flash memory and SRAM.

The embodiment of the invention discloses a bandwidth deceleration repairing method which is applied to a BIOS module, wherein as shown in figure 2, the BIOS module is connected with one side of a CPLD module containing a register through a CPU and is used for communicating with the CPLD module, and the other side of the CPLD module is connected with a PCIE module configured with a target bandwidth and is used for acquiring the link bandwidth of the PCIE module. The target bandwidth of the PCIE module may be configured in a manner that a video card (e.g., PEX8733 card) with a corresponding bandwidth is inserted into the device chassis to complete bandwidth configuration. The BIOS module can realize information interaction between the BIOS module and the CPLD module through an Inter-Integrated Circuit (IIC); meanwhile, the PEX8733 card sends the relevant information of the card, such as the on-site information, reset information, power control information, current link bandwidth information, etc. of the card to the CPLD module. As shown in fig. 1, the method comprises the steps of:

step 101, when the device is started, obtaining the link bandwidth of the PCIE module from the CPLD module.

Illustratively, the device start-up process may include a device power-on process or a device restart process, and when the device power-on process or the device restart process is detected, the link bandwidth of the PCIE module is acquired from the CPLD module through the BIOS module. Specifically, the CPLD module may obtain the current link bandwidth from the PCIE module according to a certain interval duration or obtain the current link bandwidth of the PCIE module when the CPLD module receives a link bandwidth obtaining request sent by the BIOS module, and then send the obtained link bandwidth to the BIOS module through the IIC.

Step 102, comparing the link bandwidth with the target bandwidth, and determining whether the PCIE module has a bandwidth slowdown. When the bandwidth of the PCIE module decreases, step 103 is executed.

For example, the target bandwidth may be a bandwidth initially configured for the PCIE module, and if the PEX8733 card is configured to support a bandwidth of X16, the target bandwidth is X16. Comparing the acquired link bandwidth with a target bandwidth, and when the comparison result is inconsistent, indicating that the bandwidth reduction situation occurs in the PCIE module, and requiring the bandwidth reduction recovery operation; and when the acquired link bandwidth is consistent with the target bandwidth, stopping responding to the bandwidth deceleration repairing operation.

And 103, sending a register connection state control instruction to the CPLD module, so that the register responds to the connection forbidding operation and then responds to the connection enabling operation according to the received instruction.

Illustratively, the state transition between the disabled connection and the enabled connection of the register can be realized by changing the address offset of the register, for example, when the address offset of the register can be specified to be "0", the register responds to "Enable LINK" operation, and when the address offset of the register is "1", the register responds to "Disable LINK" operation, so that the register connection state control instruction sent to the CPLD module can be an instruction for changing the address offset of the register, and by sending the instruction for changing the address offset of the register, the control register responds to the disabled connection operation first and then responds to the enabled connection operation. The specific representation form of the register address offset is not limited in the embodiment of the present application, and a person skilled in the art can determine according to actual needs as long as the disabling and enabling connection operations of the register are controlled by changing the address offset. The register connection state control instruction can also be a protocol instruction for expressing the connection forbidding and enabling sent to the CPLD module in advance by using a predetermined communication protocol, the CPLD module carries out analysis operation according to the predetermined communication protocol after receiving the protocol instruction, and the register is controlled to respond to the corresponding connection operation according to the analysis result.

According to the bandwidth speed reduction repair method provided by the embodiment of the invention, the register connection state control instruction is sent to the CPLD module, and the control register responds to the connection disabling operation and responds to the connection enabling operation according to the received instruction, so that the PCIE module link is initialized again and trained to realize link bandwidth repair. In the whole process, the register is forbidden and enabled to be connected with the register only within millisecond time while the bandwidth deceleration repair is realized, the timeliness of the bandwidth deceleration repair is improved, and the requirement on the startup time of equipment is met. When in the linux system, the setpci command can be used to complete the bandwidth down repair operation.

As an optional implementation manner of the present invention, in step 103, when bandwidth reduction occurs in the PCIE module, sending a register connection state control instruction to the CPLD module, includes: detecting bandwidth configuration information of the PCIE module; and when the PCIE module is configured with the bandwidth configuration display card, the operation of sending a register connection state control instruction to the CPLD module is executed.

Illustratively, when detecting that the bandwidth of the PCIE module decreases, first, bandwidth configuration information is detected for the PCIE module, and when the PCIE module is configured with a bandwidth configuration display card (e.g., a PEX8733 card), a subsequent register connection state control instruction sending operation is executed; when the PCIE module is not configured with a bandwidth configuration graphics card and only has a bandwidth speed reduction condition, the operation of sending the register connection state control instruction to the CPLD module is stopped, so as to avoid that the startup progress of the device is affected by executing an invalid bandwidth recovery operation under the condition that no card is inserted into the device chassis.

As an alternative embodiment of the present invention, as shown in fig. 3, after step 103, the method further includes:

and step 104, detecting the bandwidth deceleration repair result of the PCIE module. For example, the detection manner of the bandwidth deceleration repair result may be to obtain the link bandwidth of the PCIE module from the CPLD module again, compare the link bandwidth with the target bandwidth, and further determine whether the bandwidth deceleration condition still occurs in the PCIE module. For details, reference is made to the corresponding steps in the above embodiments, which are not described herein again.

And 105, when the bandwidth speed reduction still occurs in the PCIE module, repeatedly sending a register connection state control instruction to the CPLD module, so that the register responds to the step of disabling the connection operation first and then responding to the step of enabling the connection operation according to the received instruction until the target frequency is reached. For example, the target times are not limited in the embodiments of the present application, and can be determined by those skilled in the art according to actual needs. In the embodiment of the application, the target frequency is 3 times, and the frequency of bandwidth speed reduction repair is set to 3 times, so that the influence of excessive repeated repair on the starting progress is avoided while the reliable recovery of the bandwidth speed reduction is ensured.

As an optional embodiment of the present invention, as shown in fig. 4, sending a register connection state control instruction to the CPLD module in step 103, so that the register responds to the disable connection operation first and then responds to the enable connection operation according to the received instruction, includes:

step 1031a, sending a register connection forbidding control instruction to the CPLD module, so that the register responds to connection forbidding operation according to the received instruction; for a specific manner of controlling the register to disable the connection by sending the instruction, refer to step 103 in the above embodiment, and details are not described herein.

And 1032a, responding to the timing operation, and sending a register starting connection control instruction to the CPLD module when the target duration is reached, so that the register responds to starting connection operation according to the received instruction. For a specific way of controlling the register to enable connection by sending an instruction, refer to step 103 in the above embodiment, and are not described herein again.

Illustratively, in the process that the register first responds to the disabled connection and then responds to the enabled connection, in order to ensure that the PCIE module can reliably complete the operations of initialization and retraining, and improve the success rate of bandwidth slowdown recovery, the register response enabled connection operation is controlled at a certain interval after the register responds to the disabled connection operation. The target time length may be 40-60ms, and preferably 50ms in the embodiment of the present application, and the setting of the target time length is not limited, and can be determined by a person skilled in the art according to actual needs.

As an optional embodiment of the present invention, the register link state control instruction includes: a register disable connection control instruction, a register enable connection control instruction, and a register disable and enable connection operation interval duration instruction; as shown in fig. 5, the step 103 of sending a register connection state control instruction to the CPLD module, so that the register responds to the disable connection operation first and then responds to the enable connection operation according to the received instruction, further includes:

step 1031b, sending a register connection forbidding control instruction to the CPLD module, so that the register responds to connection forbidding operation according to the received instruction; for a specific manner of controlling the register to disable the connection by sending the instruction, refer to step 103 in the above embodiment, and details are not described herein.

Step 1032b, a register enabling connection control instruction and a register disabling and enabling connection operation interval duration instruction are sent to the CPLD module, so that the register responds to enabling connection delay operation according to the received instruction. For a specific way of controlling the register to enable connection by sending an instruction, refer to step 103 in the above embodiment, and are not described herein again.

Illustratively, the register connection state control instruction sent to the CPLD contains three parts of instructions simultaneously: the method comprises the steps of sending a register forbidding connection control instruction to a CPLD module firstly, enabling a register to respond to the forbidding connection operation according to a received instruction, then sending a register enabling connection control instruction and an interval duration instruction of the register forbidding and enabling connection operation to the CPLD module simultaneously, enabling the register to respond to timing operation with certain interval duration firstly and then enabling connection according to the received instruction, realizing delay control on the register enabling connection, ensuring that a PCIE module can reliably finish initialization and retraining operations, and improving the success rate of bandwidth slowdown recovery.

As an optional embodiment of the present invention, the method further comprises: and sending the repair times of the PCIE module bandwidth speed reduction and the repair result corresponding to each repair operation to a register of the CPLD module for storage. And sending the repair times and the repair result corresponding to each repair operation to a register for storage, so that a user can conveniently analyze the bandwidth abnormity repair result by using the repair data recorded in the CPLD module.

As an optional embodiment of the present invention, the method further comprises: and sending the bandwidth speed reduction information of the PCIE module to the CPLD module, so that the CPLD module stores the bandwidth speed reduction information in a register.

Illustratively, the bandwidth throttling information may include, but is not limited to, a bandwidth exception time, a device state when an exception occurs, and a bandwidth throttling exception degree. By storing the bandwidth deceleration information in the register of the CPLD module, a user can conveniently perform statistical analysis on the bandwidth abnormal condition and simultaneously other device modules connected with the CPLD module can conveniently acquire the bandwidth condition of the PCIE module from the CPLD module in time.

By the method described in the embodiment, the problem of bandwidth speed reduction in the chip can be repaired in time, the reliability of the performance of the chip is improved, and the method is convenient to popularize and use in batches in various industries.

The embodiment of the present invention further provides a bandwidth deceleration repairing apparatus, which is used for implementing the foregoing embodiment and optional embodiments, and the description of the apparatus is omitted for brevity. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

As shown in fig. 6, the device is applied to a BIOS module, the BIOS module is connected to one side of the CPLD module and is configured to communicate with the CPLD module, and the other side of the CPLD module is connected to a PCIE module configured with a target bandwidth and is configured to obtain a link bandwidth of the PCIE module; the device includes:

a link bandwidth obtaining module 301, configured to obtain a link bandwidth of the PCIE module from the CPLD module when the device is started;

a speed reduction determining module 302, configured to compare the link bandwidth with a target bandwidth, and determine whether a bandwidth reduction occurs in the PCIE module;

the instruction sending module 303 is configured to send a register connection state control instruction to the CPLD module when the PCIE module has a bandwidth slowdown, so that the register responds to the connection disabling operation first and then responds to the connection enabling operation according to the received instruction.

According to the bandwidth deceleration repairing device provided by the embodiment of the invention, when the BIOS module detects that the PCIE module has the bandwidth deceleration condition at the equipment starting stage, the BIOS module sends the register connection state control instruction to the CPLD module, the control register responds to the connection forbidding operation before the connection enabling operation according to the received instruction, so that the PCIE module link is initialized again and trained to realize the link bandwidth repairing, only millisecond-level time consumption is needed for the connection forbidding and enabling of the register in the whole bandwidth deceleration repairing process, the timeliness of the bandwidth deceleration repairing is improved, and the requirement on the equipment starting time length is met.

As an optional embodiment of the present invention, the instruction sending module 303 includes: the bandwidth configuration information detection module is used for detecting the bandwidth configuration information of the PCIE module when the bandwidth of the PCIE module is reduced; and the execution module is used for executing the operation of sending the register connection state control instruction to the CPLD module when the PCIE module is configured with the bandwidth configuration display card.

As an optional embodiment of the present invention, the apparatus further comprises: the repair result detection module is used for detecting the bandwidth deceleration repair result of the PCIE module; and the instruction repeated sending module is used for repeatedly sending a register connection state control instruction to the CPLD module when the bandwidth deceleration still occurs in the PCIE module, so that the register responds to the steps of disabling the connection operation and then responding to enabling the connection operation according to the received instruction until the target times are reached.

As an optional embodiment of the present invention, the instruction sending module 303 includes: the first instruction sending module is used for sending a register forbidding connection control instruction to the CPLD module, so that the register responds to forbidding connection operation according to the received instruction; and the second instruction sending module is used for responding to the timing operation, and sending a register starting connection control instruction to the CPLD module when the target duration is reached, so that the register responds to starting connection operation according to the received instruction.

As an optional embodiment of the present invention, the register connection state control instruction includes: a register disable connection control instruction, a register enable connection control instruction, and a register disable and enable connection operation interval duration instruction; the instruction sending module 303 further includes: the third instruction sending module is used for sending a register forbidding connection control instruction to the CPLD module, so that the register responds to forbidding connection operation according to the received instruction; and the fourth instruction sending module is used for sending a register enabling connection control instruction and a register forbidding and enabling connection operation interval duration instruction to the CPLD module, so that the register responds to enabling connection delay operation according to the received instruction.

As an optional embodiment of the present invention, the apparatus further comprises: and the first storage module is used for sending the repair times of the PCIE module bandwidth speed reduction and the repair result corresponding to each repair operation to a register of the CPLD module for storage.

As an optional embodiment of the present invention, the apparatus further comprises: and the second storage module is used for sending the bandwidth speed reduction information of the PCIE module to the CPLD module, so that the CPLD module stores the bandwidth speed reduction information in the register.

An embodiment of the present invention further provides an electronic device, as shown in fig. 7, the electronic device may include a processor 401 and a memory 402, where the processor 401 and the memory 402 may be connected by a bus or in another manner, and fig. 7 takes the connection by the bus as an example.

Processor 401 may be a Central Processing Unit (CPU). The Processor 401 may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, or combinations thereof.

The memory 402, which is a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules corresponding to the bandwidth reduction repair method in the embodiments of the present invention. The processor 401 executes various functional applications and data processing of the processor by running non-transitory software programs, instructions and modules stored in the memory 402, that is, the bandwidth slowdown repair method in the above method embodiment is implemented.

The memory 402 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by the processor 401, and the like. Further, the memory 402 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 402 may optionally include memory located remotely from processor 401, which may be connected to processor 401 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The one or more modules are stored in the memory 402 and, when executed by the processor 401, perform the bandwidth throttling repair method in the embodiments shown in fig. 1-5.

The details of the electronic device may be understood by referring to the corresponding descriptions and effects in the embodiments shown in fig. 1 to fig. 5, which are not described herein again.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD), a Solid State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.

Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.