阅读说明：本技术 一种大功率半导体过压保护器件 (High-power semiconductor overvoltage protection device ) 是由 倪侠 邹有彪 王全 徐玉豹 于 2021-07-19 设计创作，主要内容包括：本发明公开了一种大功率半导体过压保护器件,包括N型半导体衬底,所述N型半导体衬底的上方和下方对称设置有P-(2)基区,所述N型半导体衬底与P-(2)基区之间设有N-(1)型区,所述P-(2)基区的一侧扩散有P-(1)基区,所述P-(1)基区为高浓度P型掺杂基区,所述P-(2)基区为低浓度P型掺杂基区,所述N型半导体衬底的上、下表面设有金属化电极区,本发明在常规型和埋层型设计基础上,重新设计了埋层的位置以及阴极的平面形状,使得耐压区的等电位区域大大增加,保证阴极快速进入大面积大注入状态,从而快速使整个面积进入均匀的导通状态,大大增强在高电流上升率应用环境中的防护能力。(The invention discloses a high-power semiconductor overvoltage protection device which comprises an N-type semiconductor substrate, wherein P is symmetrically arranged above and below the N-type semiconductor substrate 2 Base region, N-type semiconductor substrate and P 2 N is arranged between the base regions 1 Type region of P 2 One side of the base region is diffused with P 1 Base region of P 1 The base region is a high-concentration P-type doped base region 2 The invention redesigns the position of a buried layer and the planar shape of a cathode on the basis of the conventional and buried layer designs, so that the equipotential area of a pressure-resistant area is greatly increased, the cathode is ensured to rapidly enter a large-area large-injection state, the whole area is rapidly brought into a uniform conduction state, and the protective capability in a high-current increasing rate application environment is greatly enhanced.)

1. A high-power semiconductor overvoltage protection device comprises an N-type semiconductor substrate (1), wherein P is symmetrically arranged above and below the N-type semiconductor substrate (1)₂Base region (2), N-type semiconductor substrate (1) and P₂N is arranged between the base regions (2)₁A type region (3), characterized in that said P₂One side of the base region (2) is diffused with P₁Base region (4), P₂An equipotential buried layer structure is additionally arranged on the base region (2), and N is₁The type region (3) is provided with a cathode open circuit point structure matched with the equipotential buried layer structure;

the P is₁The base region (4) is a high-concentration P-type doped base region, and P₂The base region (2) is a low-concentration P-type doped base region.

2. A high power semiconductor overvoltage protection device according to claim 1, characterized in that the upper and lower surfaces of said N-type semiconductor substrate (1) are provided with metalized electrode regions (5).

3. A high power semiconductor overvoltage protection device according to claim 2, characterized in that said metalized electrode area (5) comprises four layers, respectively of aluminum, titanium, nickel and silver.

4. A method for manufacturing a high power semiconductor overvoltage protection device according to claim 1, characterized by comprising the steps of:

the method comprises the following steps: wafer preparation

Selecting an MCZ silicon single crystal wafer, wherein the crystal orientation of the MCZ silicon single crystal wafer is less than 111%, the resistivity is 5.0-6.5 omega/cm, and the thickness is 220 mu m +/-10%;

step two: first oxidation

Manufacturing a field oxygen masking layer under the working conditions of furnace temperature 1100 ℃, oxygen 4L/min and hydrogen 5L/min, wherein the thickness of an oxide layer is 1.5 mu m +/-10%;

step three: p₁Base region preparation

Carrying out boron source deposition under the conditions of furnace temperature of 1000 ℃, oxygen of 2L/min and nitrogen of 3L/min, wherein the deposition time is 30min, carrying out boron source propulsion under the working conditions of furnace temperature of 1260 ℃, oxygen of 2L/min and nitrogen of 3L/min, the propulsion time is 2000min, and testing 15 omega +/-10% of diffusion square resistance and 28 mu m +/-10% of junction depth by using a four-probe;

step four: p₂Base region preparation

Carrying out boron source deposition under the working conditions of furnace temperature of 950 ℃, oxygen of 2L/min and nitrogen of 3L/min, wherein the deposition time is 25 min; carrying out boron source propulsion under the working conditions of furnace temperature 1245 ℃, oxygen 2L/min and nitrogen 3L/min, wherein the propulsion time is 900min, and testing the diffusion square resistance by using a four-probe to be 50 omega +/-10% and the junction depth to be 20 mu m +/-10%;

step five: n is a radical of₁Diffusion of the type region to form an emitter

Performing phosphorus source deposition under the working conditions of furnace temperature of 1060 ℃, oxygen of 2L/min, nitrogen of 3L/min and source-carrying nitrogen of 0.8L/min, wherein the deposition time is 20 min; carrying out phosphorus source propulsion under the working conditions of furnace temperature 1120 ℃, oxygen 2.5L/min and nitrogen 4L/min, wherein the propulsion time is 260min, and testing the diffusion square resistance by using a four-probe to be 1 omega +/-10% and the junction depth to be 10 mu m +/-10%;

step six: metallized electrode area

Depositing a metallization layer by an electron beam metallization evaporation table process, wherein the first layer is counted by a contact layer, and the number of the metallization layer is 4, and the metallization layer comprises 1.5 mu m of aluminum, 0.3 mu m of titanium, 0.7 mu m of nickel and 1.5 mu m of silver in sequence.

5. The method for manufacturing a high power semiconductor overvoltage protection device according to claim 4, wherein N in step five₁The type region diffusion is to form N type emitting region diffusion windows on the upper and lower surfaces of the wafer by using an emitting region photoetching plate.

6. The method for manufacturing a high power semiconductor overvoltage protection device according to claim 4, wherein P in step three and step four₁Base region and P₂The preparation of the base region needs to clean the oxide layer on the surface of the wafer, adopts spin-coating dopant as a diffusion source, and simultaneously carries out boron pre-deposition diffusion doping on two sides of the wafer.

Technical Field

The invention relates to the technical field of semiconductor chip design and manufacture, in particular to a high-power semiconductor overvoltage protection device.

Background

With the gradual change of communication/communication technology and the rapid development of high-definition video and high-speed networks, the signal interfaces of related equipment have higher and higher requirements on the capacitance of high-power semiconductor overvoltage protection devices.

The existing semiconductor overvoltage protection devices include a conventional semiconductor overvoltage protection device (as shown in fig. 1) and a conventional semiconductor overvoltage protection device (as shown in fig. 2), but as the application range of the overvoltage protection field is wider and wider, the parameter index of the device is higher and higher, and a large number of fields need to use a high-power semiconductor protection device, such as an external distribution frame of a communication user.

In the industry standard of the original semiconductor overvoltage protection device, the highest protection grade is 8/20&1.2/50 mu s waveform 500A, and in certain high-power application occasions, the peak current of 3000A or even higher is required to be reached, and the influence of the opening speed of a cathode of a chip design is limited, and a large chip device designed by the traditional scheme cannot enter a full-on state when the peak current reaches, so that the large chip device is difficult to adapt to the application occasions.

Disclosure of Invention

The invention aims to provide a high-power semiconductor overvoltage protection device, which redesigns the position of a buried layer and the planar shape of a cathode on the basis of conventional and buried layer designs, so that the equipotential area of a voltage-resistant area is greatly increased, the cathode is ensured to rapidly enter a large-area large-injection state, the whole area is rapidly brought into a uniform conduction state, and the protection capability in a high-current rise rate application environment is greatly enhanced.

The purpose of the invention can be realized by the following technical scheme:

a high-power semiconductor overvoltage protection device comprises an N-type semiconductor substrate, wherein P is symmetrically arranged above and below the N-type semiconductor substrate₂Base region, N-type semiconductor substrate and P₂N is arranged between the base regions₁Type region of P₂One side of the base region is diffused with P₁A base region;

the P is₁The base region is a high-concentration P-type doped base region₂The base region is a low-concentration P-type doped base region.

As a further scheme of the invention: and the upper surface and the lower surface of the N-type semiconductor substrate are provided with metalized electrode areas.

As a further scheme of the invention: the metallized electrode region includes four layers of aluminum, titanium, nickel, and silver, respectively.

A manufacturing method of a high-power semiconductor overvoltage protection device comprises the following steps:

the method comprises the following steps: wafer preparation

Selecting an MCZ silicon single crystal wafer, wherein the crystal orientation of the MCZ silicon single crystal wafer is less than 111%, the resistivity is 5.0-6.5 omega/cm, and the thickness is 220 mu m +/-10%;

step two: first oxidation

Manufacturing a field oxygen masking layer under the working conditions of furnace temperature 1100 ℃, oxygen 4L/min and hydrogen 5L/min, wherein the thickness of an oxide layer is 1.5 mu m +/-10%;

step three: p₁Base region preparation

Carrying out boron source deposition under the conditions of furnace temperature of 1000 ℃, oxygen of 2L/min and nitrogen of 3L/min, wherein the deposition time is 30min, carrying out boron source propulsion under the working conditions of furnace temperature of 1260 ℃, oxygen of 2L/min and nitrogen of 3L/min, the propulsion time is 2000min, and testing 15 omega +/-10% of diffusion square resistance and 28 mu m +/-10% of junction depth by using a four-probe;

step four: p₂Base region preparation

Carrying out boron source deposition under the working conditions of furnace temperature of 950 ℃, oxygen of 2L/min and nitrogen of 3L/min, wherein the deposition time is 25 min; carrying out boron source propulsion under the working conditions of furnace temperature 1245 ℃, oxygen 2L/min and nitrogen 3L/min, wherein the propulsion time is 900min, and testing the diffusion square resistance by using a four-probe to be 50 omega +/-10% and the junction depth to be 20 mu m +/-10%;

step five: n is a radical of₁Diffusion of the type region to form an emitter

Performing phosphorus source deposition under the working conditions of furnace temperature of 1060 ℃, oxygen of 2L/min, nitrogen of 3L/min and source-carrying nitrogen of 0.8L/min, wherein the deposition time is 20 min; carrying out phosphorus source propulsion under the working conditions of furnace temperature 1120 ℃, oxygen 2.5L/min and nitrogen 4L/min, wherein the propulsion time is 260min, and testing the diffusion square resistance by using a four-probe to be 1 omega +/-10% and the junction depth to be 10 mu m +/-10%;

step six: metallized electrode area

Depositing a metallization layer by an electron beam metallization evaporation table process, wherein the first layer is counted by a contact layer, and the number of the metallization layer is 4, and the metallization layer comprises 1.5 mu m of aluminum, 0.3 mu m of titanium, 0.7 mu m of nickel and 1.5 mu m of silver in sequence.

As a further scheme of the invention: in step five, N₁The type region diffusion is to form N type emitting region diffusion windows on the upper and lower surfaces of the wafer by using an emitting region photoetching plate.

As a further scheme of the invention: p in step three and step four₁Base region and P₂The preparation of the base region needs to clean the oxide layer on the surface of the wafer, adopts spin-coating dopant as a diffusion source, and simultaneously carries out boron pre-deposition diffusion doping on two sides of the wafer.

The invention has the beneficial effects that:

on the basis of conventional and buried layer designs, the position of a buried layer and the planar shape of a cathode are redesigned, so that the equipotential area of a pressure-resistant area is greatly increased, the cathode is ensured to rapidly enter a large-area large-injection state, the whole area is rapidly brought into a uniform conduction state, and the protection capability in a high-current-rise-rate application environment is greatly enhanced;

in conclusion, the surge current resistant peak value is improved by about 32% on the basis of ensuring the functions and parameters of the original product.

Drawings

The invention will be further described with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a conventional planar structure of a semiconductor overvoltage protection device in the prior art;

fig. 1-1 is a schematic view of a conventional longitudinal structure of a semiconductor overvoltage protection device in the prior art;

FIG. 2 is a schematic diagram of a buried planar structure of a semiconductor overvoltage protection device in the prior art;

FIG. 2-1 is a schematic diagram of a buried vertical structure of a semiconductor overvoltage protection device in the prior art;

FIG. 3 is a schematic diagram of the longitudinal structure of the semiconductor overvoltage protection device of the present invention;

FIG. 4 is a schematic plan view of the semiconductor overvoltage protection device of the present invention;

FIG. 5 shows a double side P of the present invention₁A structural schematic diagram of the base region;

FIG. 6 shows a double side P of the present invention₂A structural schematic diagram of the base region;

FIG. 7 is a schematic diagram of the diffusion structure of the phosphorus region in the present invention;

fig. 8 is a schematic structural view of double-sided metallization in the present invention.

In the figure: 1. an N-type semiconductor substrate; 2. p₂A base region; 3. n is a radical of₁A type region; 4. p₁A base region; 5. a metalized electrode area.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 3-4, the invention relates to a high power semiconductor overvoltage protection device, wherein P is symmetrically arranged above and below an N-type semiconductor substrate 1₂Base region 2, N-type semiconductor substrate 1 and P₂N is arranged between the base regions 2₁Type region 3, said P₂One side of the base region 2 is diffused with P₁Base region 4 of said P₁The base region 4 is a high-concentration P-type doped base region₂The base region 2 is a low-concentration P-type doped base region, the upper surface and the lower surface of the N-type semiconductor substrate 1 are provided with metalized electrode regions 5, and the metalized electrode regions 5 comprise four layers, namely 1.5 microns of aluminum, 0.3 microns of titanium, 0.7 microns of nickel and 1.5 microns of silver.

In use, at P shown in FIG. 6₂The equipotential buried layer structure shown in figure 5 is added in the base region 2, so that when a semiconductor overvoltage protection device is subjected to avalanche breakdown, large current is rapidly and uniformly diffused to the base region of the whole semiconductor overvoltage protection device through the guidance of the equipotential buried layer structure, and the cathode short-circuit point layout of phosphorus region diffusion shown in figure 7 is matched with the equipotential buried layer structure shown in figure 5, so that the whole cathode can rapidly enter a large injection state, the structure greatly increases the extension speed of base region avalanche breakdown, shortens the time from avalanche breakdown to cathode large injection effect, and reduces surge current rapidWhen the current density is increased, the current density borne by the high-power semiconductor overvoltage protection device improves the capability of the device for resisting large-current surge impact.

The manufacture method of the high-power semiconductor overvoltage protection device comprises the following steps:

the method comprises the following steps: wafer preparation

Selecting an MCZ silicon single crystal wafer, wherein the crystal orientation of the MCZ silicon single crystal wafer is less than 111%, the resistivity is 5.0-6.5 omega/cm, and the thickness is 220 mu m +/-10%;

step two: first oxidation

Manufacturing a field oxygen masking layer under the working conditions of furnace temperature 1100 ℃, oxygen 4L/min and hydrogen 5L/min, wherein the thickness of an oxide layer is 1.5 mu m +/-10%;

step three: p₁Base region preparation, diffusion range as shown in FIG. 5

Carrying out boron source deposition under the conditions of furnace temperature of 1000 ℃, oxygen of 2L/min and nitrogen of 3L/min, wherein the deposition time is 30min, carrying out boron source propulsion under the working conditions of furnace temperature of 1260 ℃, oxygen of 2L/min and nitrogen of 3L/min, the propulsion time is 2000min, and testing 15 omega +/-10% of diffusion square resistance and 28 mu m +/-10% of junction depth by using a four-probe;

step four: p₂Base region preparation, diffusion range as shown in FIG. 6

Carrying out boron source deposition under the working conditions of furnace temperature of 950 ℃, oxygen of 2L/min and nitrogen of 3L/min, wherein the deposition time is 25 min; carrying out boron source propulsion under the working conditions of furnace temperature 1245 ℃, oxygen 2L/min and nitrogen 3L/min, wherein the propulsion time is 900min, and testing the diffusion square resistance by using a four-probe to be 50 omega +/-10% and the junction depth to be 20 mu m +/-10%;

step five: n is a radical of₁The type region is diffused to form an emitter, and the diffusion range is shown in figure 7

Performing phosphorus source deposition under the working conditions of furnace temperature of 1060 ℃, oxygen of 2L/min, nitrogen of 3L/min and source-carrying nitrogen of 0.8L/min, wherein the deposition time is 20 min; carrying out phosphorus source propulsion under the working conditions of furnace temperature 1120 ℃, oxygen 2.5L/min and nitrogen 4L/min, wherein the propulsion time is 260min, and testing the diffusion square resistance by using a four-probe to be 1 omega +/-10% and the junction depth to be 10 mu m +/-10%;

step six: the diffusion range of the metalized electrode area is shown in FIG. 6

The metallization layer is deposited by an electron beam metallization evaporation stage process.

In step five, N₁The type region diffusion is to form N type emitting region diffusion windows on the upper and lower surfaces of the wafer by using an emitting region photoetching plate.

P in step three and step four₁Base region and P₂The preparation of the base region needs to clean the oxide layer on the surface of the wafer, adopts spin-coating dopant as a diffusion source, and simultaneously carries out boron pre-deposition diffusion doping on two sides of the wafer.

The following table shows a comparison of the parameters of the samples made after using this design:

the table shows that the peak value of the surge current resistance is improved by about 32% on the basis of ensuring the functions and parameters of the original product, and the parameter requirements of the high-power semiconductor overvoltage protection device are met.

While one embodiment of the present invention has been described in detail, the description is only a preferred embodiment of the present invention and should not be taken as limiting the scope of the invention. All equivalent changes and modifications made within the scope of the present invention shall fall within the scope of the present invention.